2124 SW TAYLOR STREET UNIT 7 PORTLAND, OR 97205

TEL 503-816-8470 EMAIL JES@OREGONDUCKS.ORG

JASON E. STEPHENS
PROFILE
My career objective is to expand my knowledge & experience in the field of physi
cs by means of acquiring a position in an ethical and professional environment,
which will provide a challenging and innovative role in a research & development
oriented department. In particular, a position in which I can utilize my experi
ence and knowledge of device physics and yield engineering in a challenging and
opportunistic role.
EDUCATION
UNIVERSITY OF OREGON, Eugene, OR - M.S. Applied/Solid-State Physics/2005 (M.S.I.
Accelerated Masters Prgm)
SOUTHERN OREGON UNIVERSITY, Ashland, OR B.S. Physics with Minor in Mathematics
/ 2004
EXPERIENCE
ON SEMICONDUCTOR (SEMICONDUCTOR COMPONENTS,LLC) GRESHAM, OR 10/2004-11/2008
DEVICE DEVELOPMENT INTEGRATION ENGINEER 08/2007-11/2008
Device Development Integration Engineer for The Dual Vertical Gate Trench-FET Te
chnology Development Project. This technology was the first dual vertical gated
trench FET of its kind to be developed within ON Semiconductor.
Played a lead role in the New Technology Development Project of a Dual Vertical
Gate TrenchFET device as the Device Development & Integration Engineer. Responsi
bilities include platform development and integration of optimal device paramete
rs and process manufacturing. This includes but is not limited to ownership and
generation of electrical design rules, full understanding of device TCAD layouts
, device layout and process modeling by means of statistical interpretation of D
OE results/bench testing/research into literature/etc. Routine presentations on
optimal solutions, new ideas, and potential root-cause failure mechanisms with p
lans of action for resolution.
Patents for this technology have been filed by ON Semiconductor under Semiconduc
tor Components, LLC.
Main Development & Integration Project Roles/Responsibilities/Contributions:
Analyzing theoretical, observational and experimental data. Development of DOEs
and investigation approaches for design solutions:
Use & application of quantitative research methods, mathematical principles, sta
tistical theories & methods, and theories/principals of device physics to theore
tical research and technology development.
Conduct investigations & research (including Bench-Testing, E-test data investig
ation, & laboratory research). Designing DOEs or Investigation methods for proce
ss & design troubleshooting and/or optimization.
Si-to-Model Verification.
Understand, compile, and communicate research/data results through technical rep
orts, presentations and integration solution propositions.
Routine presentations to management and design organizations on analysis of data
results from DOE and other research design methods/results.
Interfacing with business units and design organizations, including LVS support,
to resolve issue and enhance overall integration.
High voltage device recommendations supporting integration and process developme
nt of device for device centering & EDR targeting.
Electrical-test engineering support on development, enhancement, and verificatio
n of automated test programs and parameters:
Verification of automated electrical-tests through bench-test validation and cal
culation of theoretical parametric values for test structures.
E-test and Final-Test analysis and documentation.
Added and modified test-structures & tests to enhance options/methods for proces
s/design investigations, as well as optimization of design layouts and process-s
teps.
Routinely updated test conditions and documentation with bench test data for com
parison/validation.
Derived & Calculated theoretical parametric values and limits for test structure
s based on dimensional, material, and device properties. Compared test-structure
results with theoretical calculations for optimizing limits and determining pro
ximity to electrical targets.
Developed, sustained, and revised a database of electrical-test data for develop
ment and DOE/research LOTs, for statistical observations & calculations of param
etric baseline values, as well as design layout & process optimization calculati
ons. This proved to be valuable for selecting design layout configurations and p
rocess-step recipes and narrowing investigations root-cause culprit/s.
Created innovative new test conditions and structure modifications which enabled
a number of critical parameters, both electrical and physical, to be isolated d
uring parametric-testing as well as tested in tandem with multiple configuration
s. Comparing the automated combinations of parametric test results offered a muc
h-needed solution to many ongoing issues.
Worked on all major & minor design/process/integration issue investigations. I o
ffered creative investigation approaches and solutions to IDSS and IGSS paramete
r issues/roadblocks, which resulted in implementation of solutions for process &
design targeting and optimization.
PROCESS/DEVICE YIELD ENGINEER 12/2005 - 08/2007
Planned, Developed, and Taught Trench-FET Device Physics Seminars. Taught classe
s on the devise physics, physical layout, and electrical operation of the newest
Single-Gate Trench-FET device Technology to ~63 engineers. Included device phys
ics/operation of TFETs, incorporating its applications & importance. Presentatio
n illustrated and explained UMOS & DMOS devices. Seminars also focused on import
ant electrical parameters of TFETs, such as the RdsON, ID, VTH, and QG, and how
those improve device efficiency.
TrenchFET Technology Final Outgoing Inspection Development and Implementation. D
eveloped a FAB outgoing inspection equivalent to the backgrind/backmetal/Ass./fi
nal-test site incoming inspection to ensure defect events are detected, understo
od, documented, contained, and permanent solutions researched and/or established
before shipping to that facility. The design, development, and implementation o
f the Final Outgoing Inspection (FOI) into production involved:
Research & first hand observation of the back-end site incoming inspection proce
ss and its effectiveness of detecting defect events.
Researching tool capabilities, and designing experiments to determine the optima
l inspection tool and environment for detecting defects.
Elimination outside light sources on wafers within tool environment, which obstr
uct visual detection of defects during macro-insp. Addition of a camera within t
ool environment, enabling wafer image capture abilities. Automating wafer transf
er to microscope platform for micro-insp. & defect image capturing.
Development of standard conventions and methods for collecting, storing, and doc
umenting accurate and dependable defect data.
Development of the flow and logistics of the production step, wrote a detailed o
perational/procedural spec to ensure consistent and comprehensive inspection and
documentation practices.
Set up training routines and certification processes for specialists, Taught cla
ss on FOI procedures, importance, and defects of interest.
Development of a software application to automate the inspection preparation and
documentation resulting in a more time efficient inspection.
Contributing to the development of an escalation processes for reporting defect
events and corrective actions to ISMF for product incoming to them.
Determining Ave. cycle time impact and cost analysis per inspected. Overall, cyc
le time was reduced by 3 days with the above actions.
0.13*m Tech. FEOL Inspection and KDD Development. Creation, optimization, and st
andardization of KLA 2139 inspection recipe parameters and Automatic Defect Clas
sifiers (ADC) for all 0.13*m FEOL inspection steps. Applied kill ratios to ADC c
lassifier defect categories, unique to each inspection step, for accurate and co
nsistent yield forecasting and layer trending of defect density.
Sustaining Responsibilities and Improvement Activities. Owned FEOL and FOI inspe
ctions/trends and performed corrective actions against problems potentially caus
ing yield fallout. Sustaining involved monitoring inspection data, SPC data, too
l specific yield charts, and involvement with process owners, creating and worki
ng on excursions and defect cases. Involved w/ 0.13*m, 0.18*m CMOS tech. and TFE
T tech. defect investigations. Was instrumental in the documentation, research,
and containment actions for over 11 high impact defect cases.
Developed and maintain the generic defect case standing disposition for the TFET
product FOI. The document provides examples of defects seen at the FOI step and
describes each problem in great detail with links to other standing disposition
s when applicable. The document also includes a generic event and material dispo
sition for new/unknown defects to assure quick containment. New/unknown defect e
vents initiating EXRs/cases are communicated to ISMF if yield is significantly i
mpacted.
Engaged in a case where a process change had been made that leaving residual pol
y defects that damaged the integrity of the barrier layer for the source contact
resulting in IDSS fallout and visual wafer streaking at end of line. Wrote an e
ngineering build request (EBR) for the back-end site to determine the impact of
affected wafers on assembly interruption rates at wafer saw, die bond, and wire
pull, as well as IDSS variations and UIS yield at Final Test for die that passed
pre backrind/backmetal (BG/BM) IDSS limits but fell within the streak signature
. Traveled to Malaysia to work with their engineers on this engineering request.
EBR results were presented in a Corporate wide material review board (MRB) conf
erence, resulting in the salvage of ~203 wafers with an ave. yield of 90% that o
therwise would have been scrapped.
Owner of Automatic Defect Classification (ADC) System. ADC logically samples def
ects from inspected wafers using a trainable algorithm that differentiates betwe
en defect types and assigns them to predefined defect categories. Wrote an in-de
pth procedural spec. on the creation, optimization, and maintenance of ADC produ
ction classifiers. Employed standards for ADC upkeep, DSA settings, naming conve
ntions, and image sampling standards. Developed BKMs for advanced ADC accuracy a
nd purity enhancement.
Assembly Site Experience & Involvement. Traveled to the Malaysia back end proces
sing plant. Learned the manufacturing process at back-end sites. Built relations
, learned the cultural differences in conduct of business. Created presentation
covering the manufacturing process for our back-end facility. Also learned site
process for requesting engineering experiments at the back-end site.
PROCESS/DEVICE INTEGRATION LSI LOGIC/ON-SEMI 10/2004-12/2005
Managed and monitored a 0.13*m BEOL yield vehicle targeting reliability and yiel
d issues/improvements on 0.13*m products. Introduced and integrated the yield ve
hicle into the production environment to use the electrical bit mapping to inlin
e optical production step inspection overlay capabilities for determining detect
able and non-detectable defects, both systematic and random. Analyzed data resul
ts for process characterization and yield improvement/maintenance. This includes
using data results to calculate precise kill ratios, trend dark yield to predic
t missed defects in-line, investigating the source of defectivity, and employing
changes to correct yield fallout.
Electrical characterization/measurements/analysis of GIDL, Sub-threshold voltage
s, substrate sensitivity, mobility, IDSS variations, etc for 0.13 *m and 0.18 *m
CMOS technologies.
ACADEMIC RESEARCH EXPERIENCE
UNIVERSITY OF OREGON 2004/2005
Device processing and characterization for Schottky diodes, MOS cap, P-N diodes,
and MOSFETs at UofO.
SOUTHERN OREGON UNIVERSITY 2003/2004
Research on Ferroelectric Materials program at Southern Oregon University w/ NSF
-Grant.
Senior capstone-thesis was written from research results documenting conclusive
findings.
Presented findings on the properties of K2Cr2O7 at the 2004 Oregon Academy of Sc
ience Conference in 2004.
Published research results in 2004 (see below).
AWARDS & HONORS RECEIVED
PROFESSIONAL AWARDS/HONORS:
Engineering Excellence Award: Quickly Developing and Implementing a Final Outgoi
ng Insp. Method, Procedure, Documentation, and Corrective Action Policy. (02/200
7)
Engineering Excellence Award: Developing & Supporting EBRs, saving ~203 wafers f
rom scrap. (06/2007)
Published-Co-Author of "Phase transitions in K2Cr2O7 and structural redeterminat
ions of phase II" in Acta Crystallographica Section B: Structural Science. (2004
)
ACADEMIC AWARDS & HONORS:
Elected to take part in Ferroelectric Research at Southern Oregon University, fu
nded by the NSF. 2003&2004
Presented ferroelectric research results at the Oregon Academy of Science Confer
ence 2004
Outstanding Achievement Award: Outstanding Research Contribution in the Field of
Ferroelectric Compounds
Outstanding Sophomore in Physics Award
Ida and Eugene Bowman Encouragement Award and Scholarship in Mathematics
Presidential Merit Match Scholarship & Plunkett Memorial Scholarship
Elected into Whos Who Among Students in American Universities And Colleges
Elected into Sigma Xi Research Honor Society
Elected into The National Deans List
Honored with a membership to SIAM (Society for Industrial and Applied Mathematic
s) 2001-2004+
SKILLS
Computer Apps Skills: CalibreDRV, Unix, JMP, C-Sharp, Excel, Visual basic, Perl,
DataPower, MatLab, Statistica, ..
Certified in Operating: SEMs, FIBs, KLA/AIT scanners, KLA-Automatic Defect Class
ifiers, ADC-Tool operation/optimization, ESM scanning tools, Optical Scopes, ele
ctrical bench test equipment & Probe Stations, Sorters, Parametric Analyzers-Agi
lent4156/Keithley4200/similar...
In-Depth characterization working and development of Device physics and processi
ng parameter integration, in particular, knowledge of POWER FET & TFET, UMOS/DMO
S, Planar MOSFET, CMOS/ASIC devices, Bipolar Devices, etc.
Device Development Characterization, Tech. Development, Device Layout & Process
Optimization, assimilation of data results and statistical modeling for process/
device modeling & yield modeling, via data analysis and strategies for modeling
defectivity. Detailed studies and experience with quantitative research methods,
statistical applications, and conduct investigations & research.
Development of principle methods to identify, analyze, and solve problems; Plus
the application of mathematical & device principles to new and existing technolo
gies.
Device physics and processing knowledge of Trench-FET, MOSFET, CMOS, and Bipolar
Devices.
Experienced at writing technical papers and reports based on experimental data r
esults.