SUMMARY OF QUALIFICATIONS

* Expert embedded software engineer with very strong knowledge of hardware/VHDL

design
* Experienced in multi-process and real-time embedded systems.
* Knowledgeable in formal software design practices, including concept/proposal/
architecture/design/code/test reviews
* Strong leadership skills, demonstrated as team lead and as team member on mult
iple projects.
* Able to multitask extremely well due to excellent organization, prioritization
, and time management skills
* Outstanding oral and written communication skills
* Active DoD Secret Clearance
TECHNICAL SKILLS
Languages C/C++, VHDL, Java, scripting (Tcl, Bash, Perl), Matlab, Assembly (Inte
l, 1750, PIC uProc), Fortran
Concepts Software design, multi-process synchronization, full software design li
fe cycle, software profiling and optimization, unit/string/system integration an
d test, UML modeling, hardware design
Operating Systems VxWorks, Windows XP, Windows 2000/XP Embedded, Linux
Hardware Altera Nios II Embedded Processor, Freescale MPC8548E PowerQUICC III (X
Pedite5200), PowerPC 440GX (XPedite1005), Mercury PowerStream 7000, ETX-P3[E/T/M
] (Kontron)
Test Instrumentation Oscilloscopes, Logic Analyzers, Power Meters, Altera Signal
Tap, Altera System Console / FS2 Console, VxWorks System Viewer / WindView, GNU
Profiler,
PROFESSIONAL EXPERIENCE
May 2009 - Present Senior Member Engineering Staff, Lockheed Martin MS2, Moorest
own, NJ
March 2005 - May 2009 Member Engineering Staff
Multi-Mission (Radar) Signal Processor - RF Processor (RFP) Software Developmen
t and RFP I&T Software Lead
* Troubleshoot and prioritize RFP issues discovered during I&T testing and manag
e RFP I&T team members. Frequent use of Logic Analyzers, Oscilloscopes, Altera
SignalTap.
* VxWorks RTOS Kernel and C++ software development using Workbench and Profiling
using System Viewer. C++ code runs on a PowerQUICC processing core.
* Altera Nios II Embedded Processor C++ Software Development and Profiling.
* Model-based/generated code using Telelogic Rhapsody, version control using Rat
ional ClearCase/ClearQuest.
* Wrote bash, Tcl, and Perl scripts for building software and system configurati
on. Wrote programming and configuration procedure for all VxWorks, Altera, Xilin
x, and other devices in the RFP system.
Independent Research and Development (IRAD) of Proposed Radar System - Software
Lead
* Software lead during concept inception and through several follow-on phases, i
ncluding implementation and testing of prototype systems.
* Worked very close with hardware engineers on system/board architecture and VHD
L design.
* Developed and implemented the framework for a testing strategy that enables ea
rly testing of board components and software interfaces prior to formal software
development using Altera's System Console and FS2 Console.
* Designed software test suite capable of being run via Windows command line, Gr
aphical User Interface (GUI), or Matlab interface. All test suite code written
in C++ using Microsoft Visual Studio .NET
AEGIS Ballistic Missile Defense Signal Processor - Software Development
* Six-month interim lead of software "Interfaces" team, which developed common s
oftware communication interfaces used by multiple software components, including
10Gb Ethernet, RapidIO, NTDS-B/E.
* Member of Digital Processor team - DSP Algorithm coding, ran on Mercury PowerS
tream 7000
* Member of RF Processor software team. Responsibilities covered in Multi-Missi
on project above.
PROFESSIONAL EXPERIENCE (continued)
May 2004 - March 2005 Electrical Engineer, NAVSEA, Philadelphia, PA
* Develop code for programmable logic controllers and GUIs used to interface wit
h networked components of shipboard material handling systems.
* Manage contractors in several projects and report progress to Navy sponsors.
* Lead feasibility and return on investment research for proposed systems.
* Received secret clearance in July 2004.
June 2003 - June 2004 Research Assistant, Rowan University, Glassboro, NJ
* Investigate emerging VLSI design and test methods, System-on-Chip (SoC) Design
.
* Contribute to curriculum development through presentation of findings.
May 2001 - Jan. 2002 Technical Intern II, Northrop Grumman Electronic Systems,
College Park, MD
* Created test benches to verify functionality of third-party VHDL models.
* Wrote and presented employee tutorial for QuickSim Pro VHDL and schematic simu
lator.
EDUCATION
May 2013 Master of Science in Computer Science
(Expected Graduation) Stevens Institute of Technology, Glassboro, NJ
Graduate Courses: - Software Testing, Quality, and Maintenance - Jav
a Programming
June 2003 - Master of Science in Electrical and Computer Engineering (42 out of
62 credits required)
Sept 2004 Rowan University, Glassboro, NJ
Thesis: Design and Implementation of a Speaker Verification IP Core
Graduate Courses: - Advanced DSP - Microprocessor Design - Pat
tern Recognition
- Image Processing - Engineering Management
March 2003 Comprehensive VHDL Training
Mentor Graphics Education Services, San Jose, CA - 5 Day/40 hr Course
May 2002 Bachelor of Science in Electrical and Computer Engineering
Rowan University, Glassboro, NJ