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Fourth semester BE Degree Examination,

(IV Sem Common to EC/TC/ML)
Model Paper-I

SUB-CODE :06EC-46 SUB: Linear Integrated Circuits

Duration : 3 Hrs Max Marks: 100

Answer any five questions selecting at least two from each part

Part-A
1a With neat ckt diagram explain the basic operation of an op amp [08]
b An op amp voltage follower is to operate with a minimum i/p voltage of 200mv .if the error
in the output voltage due to amplifier gain is not to exceed 0.005% determine the minimum
voltage gain required for the op amp. [05]
c With a neat circuit diagram, derive the expression of closed loop gain of an inverting

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amplifier [07]

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2a Explain the effect of capacitor in a capacitor coupled voltage follower. [06]
b A capacitor coupled non inverting amplifier is to have Av 90 and Vo=3 V. the load
resistance is 10 k and the lower cutoff frequency is to be 70Hz.Design the suitable circuit.

c
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Discuss the significance of using single polarity supply in op amp circuits.
[08]
[06]
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3a With a help of neat sketches, explain different methods of frequency compensation.

[12]
b Calculate the cutoff freq limited rise time for a voltage follower circuit using 741 op amp.
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Also determine the Slew Rate limited rise time if the output amplitude is to be 5V
[04]
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c Show the slew rate effect on bandwidth and output amplitude [04]
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4a With a neat sketch show the realization of precision voltage source using op amp [06]
b Draw the ckt diagram of current amplifier using op amp and explain its working [06]
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c Design an instrumentation amplifier to have an overall voltage gain of 900. the input signal
amplitude is 15mv,741 opamps are to be used and the supply is +/- 15V [08]

Part –B

5a Sketch the ckt of a non saturating half wave precision rectifier .Draw the input and output
waveforms and explain the ckt operation. [08]
b Design a phase shift oscillator using 741 opamp with a supply of +/- 12 V for the frequency of 2KHz
[06]
c Discuss the design procedure for waveform generator circuit. [06]

6a Design an astable multivibrtor to have an output of +/- 9V with 500HZ frequency using suitable op
amp. Draw the ckt and indicate the designed values [06]
b With a neat ckt diagrams and waveforms derive an expression for pulse width of monostable
multivibrator using op amp. [08]
c Show the realization of antilogarithmic amplifier using op amp and explain [06]

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7a Show how opamp can be used as series regulator [06]

b Draw and explain the functional diagram of 723 IC [08]
c Design a regulator using 7810 IC for output voltage of 15V [06]

8a Define the following terms with respect to PLL .

i) Lock range ii) capture range iii) Free running frequency [06]
b Design a two bit flash ADC [08]
c Design monostable multivibrator using 555 timer for a pulse width of 1msec.Draw the ckt
diagram along with input and output waveforms. [06]

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Fourth semester BE Degree Examination,

(IV Sem Common to EC/TC/ML)
Model Paper-II

SUB-CODE :06EC-46 SUB: Linear Integrated Circuits

Duration : 3 Hrs Max Marks: 100

Answer any five questions selecting at least two from each part
Part-A
1a Define the following parameters of an op amp and mention their typical values for 741:
i) Input and output offset voltages ii) CMRR iii) Slew Rate iv) PSRR
[10]
b An opamp inverting amplifier has a 0.5V input signal and its output is to be 9V.A12 K?
resistor is available for use as Rf.Calculate a suitable resistance value for R
[05]

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c Calculate the input and output impedances of a 741 op amp to function as a voltage
follower.Given: open loop gain =2x105 [05]

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2a How to set the upper cutoff frequency in an inverting amp circuit. [06]
b With a neat ckt diagram explain the working of capacitor coupled difference
Amplifier.
[06]
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c A capacitor coupled non inverting amplifier is to have a +24 V supply, a voltage gain of 100
,an output amplitude of 5 V, a lower cutoff frequency of 75 Hz and the minimum load
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resistance of 5.6 k? Using 741 op amp, design a suitable circuit.

[08]
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3a With a neat sketch, explain Zin MOD compensation.

[10]
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b i) Calculate the slew rate limited cutoff frequency for a voltage follower ckt using a 741 op
amp if the peak of sine wave output is to be 5V
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ii) Determine the maximum peak value of the sinusoidal output voltage that will allow the
741 voltage follower ckt to operate at 800 kHz unity gain cutoff frequency
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[06]
c Define gain bandwidth product of an op amp and explain its significance
[04]

4a Draw the ckt diagram of instrumentation amplifier using 3 op amps and explain the same[06]
b Design a voltage source to provide a constant output voltage of 6V using zener Vz=6.3 V. the
load resistance as a min value of 150ohma and the available supply is +/-12 V. Assume
Iz=20mamps,hfe(min)=20,Ie(max)>42mamps and Vce(max)>Vcc Draw the ckt diagram and
insert the designed values
[10]
c Show the realization of current to voltage converter using op amp.
[04]

Part-B

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5a Show the realization of logarithmic amplifier using opamp.obtain the expression for the
output voltage.
[08]
b With neat sketch explain voltage follower peak detector
[06]
c A +/- 1.5 V signal is to be sampled by a sample and hold circuit. The holding time is 700
µsec, and the output accuracy is to be approximately 0.3%.LM108 op amp are to be used,
and the available FET has a 25? channel resistance and a 300 nA gate source reverse
leakage current. Design the circuit, and determine the minimum acquisition time.
[06]

6a With neat sketch, explain op amp inverting Schmitt trigger. Draw its input output w/f and
transfer curve
[08]
b Design a second order low pass filter to have a cutoff frequency of 1.5 kHz using 741 op amp

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[06]

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c Show how opamp can be used of zero crossing detector
[06]

7a
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Explain the operation of switching regulator using op amp [06]
Give the classification of regulators. Explain current fold back and current boosting techniques in
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regulators [08]
c Design a voltage regulator using 723 IC for output voltage of 3 V
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[06]

8a With neat block schematic, explain the operation of each component in PLL.
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[08]
b Show the realization of ASMV using 555 IC and derive the expression for output frequency
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[06]
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c Determine the output voltage produced by a DAC whose output range is 0-10V for the
following input binary data :
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i)10 ii)1010 iii)10111110.

[06]

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