4 bit Computer Desgin

Design and 
Implementation 

CSE 404N
Digital System Design  Group #1
Sessional
Student No.: 0205002
0205003
0205004
0205014
0205026
0005069
 
 Table of Contents 
 
1. Introduction:................................................................................................................................ 4
2. Instruction Set: ............................................................................................................................ 5
3. Block Diagram: ........................................................................................................................... 6
4. Components of the Computer: .................................................................................................... 7
4.1. Accumulator: .................................................................................................................. 7
4.2. B register: ....................................................................................................................... 7
4.3. ALU unit: ........................................................................................................................ 7
4.4. Output Register and Binary Display: ............................................................................. 7
4.5. RAM/Stack:..................................................................................................................... 7
4.6. Program Counter (PC): ................................................................................................. 7
4.7. Instruction Register (IR): ............................................................................................... 7
4.8. Control ROM: ................................................................................................................ 8
4.9. SP and the SP-Decrement Unit: ..................................................................................... 8
4.10. Address MUX: .............................................................................................................. 8
4.11. B MUX: ........................................................................................................................ 8
4.12. PC MUX: ...................................................................................................................... 8
4.13. Input Port: .................................................................................................................... 8
4.14. Input Switches: ............................................................................................................. 8
5. Opcodes and Control Words: ...................................................................................................... 8
6. Control Signals: ........................................................................................................................ 11
7. Circuit Diagram: ....................................................................................................................... 12
8. Timing Diagrams: ..................................................................................................................... 13
8.1. Fetch: ........................................................................................................................... 13
8.2. LDA address:................................................................................................................ 14
8.3. STA address: ................................................................................................................ 15
8.4. MOV Acc,B: ................................................................................................................. 16
8.5. MOV B, Acc: ................................................................................................................ 17
8.6. MOV Acc, immediate: .................................................................................................. 18
8.7. IN:................................................................................................................................. 19
8.8. OUT:............................................................................................................................. 20
8.9. ADD B / ADC B / SUB B / SBB B / AND B: ................................................................ 21
8.10. ADD immediate / XOR immediate: ............................................................................ 22
8.11. SHL: ........................................................................................................................... 23
8.12. SHR: ........................................................................................................................... 24
8.13. NOP:........................................................................................................................... 24
8.14. CMP B / TEST B: ....................................................................................................... 25
8.15. SUB [address]: ........................................................................................................... 26
8.16. JC address: ................................................................................................................. 27
8.17. JE address: ................................................................................................................. 28
8.18. JMP address:.............................................................................................................. 29
8.19. HLT address: .............................................................................................................. 29
8.20. PUSH: ........................................................................................................................ 30
8.21. POP: ........................................................................................................................... 31
8.22. CALL address:............................................................................................................ 32

2 |  
 
 8.23. RET: ........................................................................................................................... 33
9. Explanation of Instructions: ...................................................................................................... 34
9.1. Fetch: ........................................................................................................................... 34
9.2. Execution:..................................................................................................................... 34
9.2.1. LDA address: ................................................................................................... 34
9.2.2. STA address: .................................................................................................... 34
9.2.3. MOV Acc, B / MOV Acc, imm / IN: ................................................................. 34
9.2.4. MOV B,Acc / OUT: .......................................................................................... 34
9.2.5. ADD B / ADC B / SUB B / SBB B / ADD imm / AND B / XOR imm: .............. 34
9.2.6. CMP B / TEST B:............................................................................................. 34
9.2.7. SUB [address]: ................................................................................................ 35
9.2.8. SHL/SHR: ........................................................................................................ 35
9.2.9. JC address: ...................................................................................................... 35
9.2.10. JE address: .................................................................................................... 35
9.2.11. JMP address: ................................................................................................. 35
9.2.12. PUSH: ............................................................................................................ 35
9.2.13. POP: .............................................................................................................. 35
9.2.14. CALL address: ............................................................................................... 35
9.2.15. RET: ............................................................................................................... 36
9.2.16. NOP: .............................................................................................................. 36
9.2.17. HLT : .............................................................................................................. 36
11. How to Load / Write Programs: .............................................................................................. 36
12. How to Run / Execute Programs:............................................................................................ 36
13. Special Features: ..................................................................................................................... 36
12. ICs used with Count:............................................................................................................... 37
13. Discussion: .............................................................................................................................. 37

3 |  
 
1. Introduction: 
  
The design and implementation of a 4 – bit computer poses a really challenging, yet wonderful
design and implementation concern to the novice hardware designers like us. It requires a good
understanding of various design techniques and a complete realization of the computer architecture. It
also provides a fragrance of a large scale design challenge of designing a whole computer in a small scale
version imposed by the 4-bit data size and a restricted instruction set.

We, the hardware designers often tend to make a language out of the different hardware components.
Whenever we think of logical ANDing, ORing or XORing, the respective logic gates readily provides us
with such functions. We always think of branching in terms of a multiplexer. A for loop or a while loop
often gives us the illusion of using a counter or a flip-flop. These little things form the vocabulary of a
hardware design. An instruction uses this vocabulary to do some definite task. Thus an instruction set
defines the complete specification of the assembly language lying beneath the hardware.

In our computer design, we implemented an instruction set consisting of 28 instructions as suggested by

our course teachers. Our computer has a 4 bit data length and an 8 bit address length. However, the design
is easily extendible to a more powerful computer.

In the following sections, we shall describe the design of our computer under various titles. Section 2
gives the instruction set. In section 3 and 4, we presented the block diagram and the description of
different blocks in that diagram. Section 5 and 6 list and describes the Control Words and signals used. In
section 7, we have given a detailed pin-diagram specification of the circuit. Section 8 addresses the timing
diagrams for all the instructions while section 9 describes the working techniques of these instructions.
Section 10 is a little user manual to show how to program and run our Computer. Section 11 lists some
special features of our Computer. Finally in section 12, all the ICs used with count are listed.

4 |  
 
2. Instruction Set: 
 
Instruction Description
LDA address Acc Å Memory [address]
STA address Memory [address] Å Acc
MOV Acc, B Acc Å B
MOV B, Acc B Å Acc
MOV Acc, immediate Acc Å immediate
In Acc Å input_port
Out Output_port Å Acc
ADD B Acc Å Acc + B
ADC B Acc Å Acc + B + C (Contents of Carry Flag)
SUB B Acc Å Acc – B
SBB B Acc Å Acc - B - Bo(Contents of Carry Flag)
ADD immediate Acc Å Acc + immediate
SUB [address] Acc Å Acc - Memory [ address ]
CMP B Set Flags according to “SUB B”
TEST B Set Flags according to “AND B”
JC address Jumps to the address if the Carry Flag is set
JE address Jumps to the address if equal i.e. the Zero Flag is set
PUSH Pushes the contents of the accumulator to the stack
POP Pops off the top of the stack to the accumulator
CALL address Calls a subroutine at the address unconditionally
RET Returns from the current subroutine to the caller
JMP address Jumps unconditionally to the address
HLT Halts execution
NOP No Operation
SHL Acc Å Acc << 1, C ÅAcc [MSB], Acc [LSB] Å0
SHR Acc Å Acc >> 1, C ÅAcc [LSB], Acc [MSB] Å0
AND B Acc Å Acc. B
XOR immediate Acc Å Acc xor immediate

5 |  
 
3. Block Diagram: 

Immediate Data (4-bit)

 

8(2x1) 8
8 MUX
5-
Control Bit 8
Rom
IR PC SP Inc/Dec
13 13-bit 8-bit 8-bit Unit
32 x 24 
8 8 8 8

8(4x1) MUX
24 8
8

Control
Word RAM/Stack

Output Immediate Data

Register 4 4 Data In
4
B-Reg
Data In 4-bit
4

4 4 4
4
4 4(4x1) MUX
Accumulator
4-bit
Binary
Display
FLAGS

 
Fig: Block Diagram of 4-bit Computer

6 |  
 
4. Components of the Computer: 
4.1. Accumulator: 
Accumulator is a register that stores intermediate results during a computer run. In arithmetic and
logic operations, one operands must be the accumulator and the result of the operation is also stored here.
The PUSH, POP, IN, OUT and MOV instructions also involves Accumulator register. In the block
diagram, Accumulator output goes to the A input of the ALU and the output of the ALU unit comes as the
input of the Accumulator.

4.2. B register: 
B is another register that is used in various two-operand arithmetic and logic operations. its output
goes to the B MUX and its input is provided from the result of the ALU unit

4.3. ALU unit: 
ALU unit provides the necessary arithmetic and logic operations. One of its input comes from the
output of the Accumulator and the other input comes from the B MUX. Its output goes to the input of
Accumulator, B register, Output register and RAM/Stack.

4.4. Output Register and Binary Display: 
After the execution of OUT command, the value of Accumulator is stored in the output register and
is displayed in the binary display consisting of4 LEDs.

4.5. RAM/Stack: 
RAM stores the Opcode, immediate data / address and also provides the space for the DATA
segment for the user. Stack gives the user the provision of stacking various data and later popping them. It
also saves PC value pointing the instruction to be executed next on the Caller subroutine so that it can be
retrieved after the execution of the RET instruction in the Callee subroutine.
RAM and Stack are placed together and they are differentiated through the unused MSB address
bits. Also, Control ROM provides the signal /Mem-Stack to specify whether RAM or Stack should be
addressed.
RAM/Stack input comes from three sources: ALU result, PC output and Input switches. Its output
goes to B MUX as well as to the IR input. It is addressed by the Address MUX.

4.6. Program Counter (PC): 
PC is a counter that points to the memory address that stores the next instruction to be executed. At
the start of the execution, PC is always reset to 0. During the normal sequential flow, after every fetch
cycle, PC value is incremented by 1. When a jump is required, PC value is loaded on the rising edge of
the execution clock cycle by the value provided from PC MUX. Its output goes to the Address MUX so
that it can provide the addressing to the RAM during fetch cycle.

4.7. Instruction Register (IR): 
IR stores the Opcode and immediate data/address of the instruction that is currently being executed.
When its value is 0, it specifies that fetch cycle is being performed. At the start of the computer run, it is
reset to 0. During fetch cycle, it is loaded from the RAM location addressed by the PC value. After every
execution cycle, it is once again reset to 0. Its output provides the necessary addressing to the Control
ROM so that it can provide the Control Signal appropriate to the Opcode currently being executed. Its
output also goes to the Address MUX to provide immediate addressing of the RAM as needed.

7 |  
 
4.8. Control ROM: 
Control ROM is addressed by the Opcode currently being stored in IR and it provides the 24 – bit
Control Signal to run the computer correctly. The Control Signals are described in section 5 and 6.

4.9. SP and the SP­Decrement Unit: 
SP is an up-down counter that points to the top of the Stack. Initially it is reset to 0. After the
execution of a PUSH or CALL instruction, its value is incremented by 1 and after the execution of a POP
or RET instruction, its value is decremented by 1. Its output goes to the Address MUX to provide
addressing of the stack during push or CALL instruction.
The output of SP also goes to the SP-Decrement unit to provide decremented value of SP a-priori
of the execution of the POP and RET instruction via the Address MUX.

4.10. Address MUX: 
The Address MUX provides the proper addressing of the RAM / Stack among several addresses:
PC, IR, SP, SP-1, Input address switches. The Control Signals AddS1 and AddS0 and the RUN-/PROG
input make up the selectors of this MUX.

4.11. B MUX: 
The B MUX provides the B input of the ALU unit among 4 options: B register, RAM, input port
and immediate data from IR. The Control Signals BS1 and BS0 make up the selectors of this MUX.

4.12. PC MUX: 
The PC MUX provides the input of the PC between 2 options: Stack ( during RET ) and immediate
data from IR. The Control Signal PCS makes up the selector of this MUX.

4.13. Input Port: 
Input port provides the input data during the execution of IN instruction via the B MUX.

4.14. Input Switches: 
These Switches provides the addressing, Opcode and immediate data/address during the program
mode of the computer.

5. Opcodes and Control Words: 

8 |  
 
 Control Word ( Binary )
1 2 3 4 5 6
OpCode ( Decimal ) 

OpCode( Binary ) 
_ _ _

Control Word
Hexadecimal
P P P P M I R A A A B B A A A A A A A B F O I H

Command
C C C C e n / L d d S S L L L L L c c i l U R L
i i i S m c _ U d d 1 0 U U U U U c c n a T R T
n n n / / W 0 S S 1 2 3 4 5 S S g i
U C Z S D 1 0 1 0 i n
t e n
k c

00  00000 Fetch 0  0  0  0  0  0  1  0  1  1  0  0  0  0  0  0  0  0  0  0  0 0  1  0  02C002

01  00001
02  00010
03  00011
04  00100
05  00101
06  00110
07  00111
08  01000
09  01001
10  01010
11  01011
12  01100
13  01101
14  01110
15  01111
LDA address 0  0  0  0  0  0  1  1  1  0  1  0  1  0  0  0  1  1  1  0  0 0  0  0  03A8E0
STA address 0  0  0  0  0  0  0  1  1  0  0  0  1  1  0  1  1  0  0  0  0 0  0  0  018D80
MOV Acc, B 0  0  0  0  0  0  1  1  0  0  0  1  1  0  0  0  1  1  1  0  0 0  0  0  0318E0
MOV B, Acc 0  0  0  0  0  0  1  1  0  0  0  0  1  1  0  1  1  0  0  1  0 0  0  0  030D90
MOV Acc,
imm
0  0  0  0  0  0  1  1  0  0  1  1  1  0  0  0  1  1  1  0  0 0  0  0  0338E0
IN 0  0  0  0  0  0  1  1  0  0  0  0  1  0  0  0  1  1  1  0  0 0  0  0  0308E0
OUT 0  0  0  0  0  0  1  1  0  0  0  0  1  1  0  1  1  0  0  0  0 1  0  0  030D84
ADD B 0  0  0  0  0  0  1  0  0  0  0  1  0  1  0  0  1  1  1  0  1 0  0  0  0214E8
ADC B 0  0  0  0  0  0  1  0  0  0  0  1  0  1  1  0  1  1  1  0  1 0  0  0  0216E8
SUB B 0  0  0  0  0  0  1  1  0  0  0  1  0  0  0  1  0  1  1  0  1 0  0  0  031168
SBB B 0  0  0  0  0  0  1  1  0  0  0  1  0  0  1  1  0  1  1  0  1 0  0  0  031368
ADD imm 0  0  0  0  0  0  1  0  0  0  1  1  0  1  0  0  1  1  1  0  1 0  0  0  0234E8
SUB [addr] 0  0  0  0  0  0  1  1  1  0  1  0  0  0  0  1  0  1  1  0  1 0  0  0  03A168
CMP B 0  0  0  0  0  0  1  1  0  0  0  1  0  0  0  1  0  0  0  0  1 0  0  0  031108
TEST B 0  0  0  0  0  0  1  1  0  0  0  1  1  1  1  0  1  0  0  0  1 0  0  0  031E88

9 |  
 
 Control Word ( Binary )
1 2 3 4 5 6
OpCode ( Decimal ) 

OpCode( Binary ) 
_ _ _

Control Word 
Hexadecimal
P P P P M I R A A A B B A A A A A A A B F O I H

Command
C C C C e N / L d d S S L L L L L c c i l U R L
i i i S m c _ U d d 1 0 U U U U U c c n a T R T
n n n / / W 0 S S 1 2 3 4 5 S S g i
U C Z S D 1 0 1 0 i n
t e n
k c

16  10000 Fetch 0  0  0  0  0  0  1  0  1  1  0  0  0  0  0  0  0  0  0  0  0 0  1  0  02C002 

17  10001
18  10010
19  10011
20  10100
21  10101
22  10110
23  10111
24  11000
25  11001
26  11010
27  11011
28  11100
29  11101
30  11110
31  11111
JC address 0  1  0  1  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  520000 
JE address 0  0  1  1  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  320000 
PUSH 0  0  0  0  1  0  0  1  0  1  0  0  1  1  0  1  1  0  0  0  0 0  0  0  094D80
POP 0  0  0  0  1  1  1  1  0  0  1  0  1  0  0  0  1  1  1  0  0 0  0  0  0F28E0 
CALL
address
1  0  0  1  1  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0  0 0  0  0  984000 
RET 1  0  0  0  1  1  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  8E0000 
JMP
address
1  0  0  1  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  920000 
HLT 0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  1  1  020003 
NOP 0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  020000 
SHL 0  0  0  0  0  0  1  1  0  0  0  0  1  1  0  1  1  1  0  0  1 0  0  0  030DC8
SHR 0  0  0  0  0  0  1  1  0  0  0  0  1  1  0  1  1  0  1  0  1 0  0  0  030DA8
AND B 0  0  0  0  0  0  1  1  0  0  0  1  1  1  1  0  1  1  1  0  1 0  0  0  031EE8 
XOR imm 0  0  0  0  0  0  1  1  0  0  1  1  1  0  1  1  0  1  1  0  1 0  0  0  033B68 
NOP 0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  020000 
NOP 0  0  0  0  0  0  1  0  0  0  0  0  0  0  0  0  0  0  0  0  0 0  0  0  020000 

10 |  
 
6. Control Signals: 
 
Signal Description Comment Instructions
PCinU 1 Jump unconditionally JMP, CALL, RET
0 No unconditional jump
PCinC 1 Jump if C=1 JC
0 Do not jump on C
PCinZ 1 Jump if Z=1 JE
0 Do not jump on Z
PCS 0 Popped address from Selects the PCMUX ; JMP,CALL,RET
Stack output Significant only if
PCinU=1
1 Immediate address from
IR
____ 0 RAM Acts as count enable 0 RAM operations, fetch
Mem/Stack of SP as well
1 Stack 1 PUSH,POP,CALL,RET
__ 0 SP ÅSP + 1 Significant only if 0 PUSH,CALL
Inc/Dec Stack=1
1 SP Å SP – 1 1 POP,RET
__ 0 Write Memory/Stack RAM and Stack operations,
R/W 1 Read Memory/Stack fetch

ALU0-5 S0=ALU2 Selects ALU All instructions working on

S1=ALU0 Operational Mode data
S2=ALU4
S3=ALU5
Cin=ALU2 xor (ALU3.C)
M=ALU1
AddS1-0 00 SP – 1 Select the Address All instructions of RAM and
01 SP MUX Stack
10 IR
11 PC
BS1-0 00 Input port Select the B MUX All operations involving data
01 B register
10 RAM/Stack
11 Immediate data (IR)
AccS1-0 00 No change Select Accumulator All operations involving data
01 Shift Right operations
10 Shift Left
11 Load
Bin 1 Load B MOV B, Acc
0 Do not load B
Flagin 1 Load Flags All operations where Flags
0 Do not load Flags are affected

11 |  
 
Signal Description Comment Instructions
Outin 1 Load Output OUT
0 Do not load Output
___ 0 Reset IR Fetch, HLT
IRR 1 Do not reset IR
HLT 1 Halt HLT
0 Do not halt

7. Circuit Diagram: 
 
Attached at the end of the report
 
 
 
 
 
 
 

12 |  
 
 U3 V7
5V
74LS157 +V U1
S 74LS163A
I1a CEP MR
I0a Ya CET
I1b CP
I0b Yb PE TC
I1c D3 Q3
I0c Yc D2 Q2 U19
I1d
I0d Yd
D1
D0
Q1
Q0
AdM3 74LS126
4C
E U10 4Y 4A
3C
V5
5V IRL PCMU PCU 74LS153
I3a Ea 3Y 3A
I2a 2C
+V U2 I1a Ya 2Y 2A
74LS273 I0a 1C
1Y 1A
MR
CP
S1
S0 AdR/PM1
D7
D6
Q7
Q6
I3b
I2b Yb U14 3-state-2
D5 Q5 I1b 74LS157
D4 Q4 I0b Eb S
D3 Q3 U11 I1a
D2 Q2 74LS153 I0a Ya
D1
D0
Q1
Q0
I3a
I2a
Ea I1b
I0b Yb
RAM-U
I1a Ya I1c U16
I0a I0c Yc 1K RAM
U6 S1 I1d
S0 I0d Yd A9 CS
74LS191 I3b E A8 WE
CE I2b Yb A7 IO7
CP I1b A6 IO6
PL RC I0b Eb A5 IO5
U/D TC A4 IO4
D3 Q3 SPALU-U A3 IO3
D2
D1
Q2
Q1
AdM2 A2 IO2
U8 A1 IO1
D0 Q0 A0 IO0
74LS83
V9 A4
5V SPU A3
A2
+V A1 s4
B4 s3
B3 s2
B2 s1
B1
Cin Cout 3-state-1
U22 74LS126
4C
RAM-L 4Y 4A
3C
3Y 3A
U17 2C
U5 U12 1K RAM 2Y 2A
74LS157 U4 74LS153 1C
S 74LS163A I3a Ea AdR/PM0 A9 CS 1Y 1A
I1a CEP MR I2a A8 WE
I0a Ya CET I1a Ya U15 A7 IO7 U23
I1b CP I0a 74LS157 A6 IO6 74LS126
I0b Yb PE TC S1 S A5 IO5 4C
I1c D3 Q3 S0 I1a A4 IO4 4Y 4A
I0c Yc D2 Q2 I3b I0a Ya A3 IO3 3C
I1d D1 Q1 I2b Yb I1b A2 IO2 3Y 3A
I0d Yd D0 Q0 I1b I0b Yb A1 IO1 2C
E I0b Eb I1c A0 IO0 2Y 2A
PCL I0c Yc 1C
PCML AdM1
I1d
I0d Yd
1Y 1A
E 3-state-0

U39D U13
74LS153
IR1 IR0

74LS163A

74LS163A
CEP
CET
CP
PE
D3
D2
D1
D0

CP
PE
D3
D2
D1
D0
CEP
CET
I3a Ea
I2a
I1a Ya U40
U25
I0a
U41A

MR

TC
Q3
Q2
Q1
Q0
S1

MR

TC
Q3
Q2
Q1
Q0
U7 S0 U43B U41B
74LS191 I3b
CE U20D I2b Yb
CP I1b
PL RC I0b Eb
U/D TC
D3 Q3 U41D
D2 Q2 AdM0 U44A
D1 Q1

CS
CS

A4
A3
A2
A1
A0

CS

A4
A3
A2
A1
A0
D0 Q0

PROM32
PROM32

PROM32
SPALU-L U27 U26
U36C SPL V3
74LS83
5V
O7
O6
O5
O4
O3
O2
O1
O0

O7
O6
O5
O4
O3
O2
O1
O0
+V A4
A3 U46
A2 ROM0 ROM1 ROM2
A1 s4
U39C B4 s3
B3 s2
U20C B2 s1
B1
Cin Cout

U39B

0V 0V 0V 0V 0V 5V 5V 0V
0V 5V
A7 A6 A5 A4 A3 A2 A1 A0
CLK RUN
Input Address Switch
 RAM-M2 U29
74LS194
U9 74LS153 D3 CP
Ea I3a D2
I2a D1 S1
Ya I1a D0 S0
I0a
S1 Q3 DSR
S0 Q2 DSL
I3b U28 Q1
Yb I2b 74LS181 Q0 MR
I1b Cn S3
Eb I0b M S2 Acc
U18 S1
74LS153 Cn+4
S0
A3 BMUX1
Ea I3a A=B A2 U31 74LS153
I2a G A1 Ea I3a
Ya I1a P A0 I2a
I0a F3 B3 Ya I1a
S1 F2 B2 I0a
S0 F1 B1 S1
I3b F0 B0 S0
Yb I2b I3b
I1b D-ALU Yb I2b
Eb I0b I1b
74LS181 Eb I0b
RAM-M1 Cn S3
74LS257 M S2 V6
S U45 S1 5V
U21 I1a S0 +V
Ya I0a Cn+4 A3 74LS153 U32
I1b A=B A2 Ea I3a
Yb I0b G A1 I2a
I1c P A0 Ya I1a
Yc I0c F3 B3 I0a
I1d F2 B2 S1
Yd I0d F1 B1 S0
OE F0 B0 I3b
O-ALU Yb I2b
I1b
U42
RAM-M0 Eb I0b

CP
S1
S0
DSR
DSL
MR
74LS194
U20E U44B BMUX0 B Reg

D3
D2
D1
D0
Q3
Q2
Q1
Q0
U43A U38A

Output Reg
FMUX1
I3a
I2a
I1a
I0a
S1
S0
I3b
I2b
I1b
I0b

I3a
I2a
I1a
I0a
S1
S0
I3b
I2b
I1b
I0b
74LS153

74LS153

74LS194
D3 CP
U33 U34 D2 U30 V8
D1 S1 5V
Ea
Ya

Yb
Eb

Ea
Ya

Yb
Eb

D0 S0 +V
U35D
C O FMUX0 S Z Q3 DSR
Q2 DSL
Q1
Q0 MR
U36B
U35C

U41C

5V 5V 0V 0V 0V
Q0
Q1
Q2
Q3
D0
D1
D2
D3

I4 I3 I2 I1 I0
74LS194

L4 L3 L2 L1
Opcode Input Flag U37
Output Display
A4
A3
A2
A1
A0

DSL
DSR

ZF
MR

S0
S1
CP

L5
U24
SF
O7
O6
O5
O4
O3
O2
O1
O0

L6

L7 OF
L8 CF

Flag Display

4-bit Computer Design

0V 5V 0V 5V 0V 5V 0V 0V
D7 D6 D5 D4 D3 D2 D1 D0 Group # 01
Immediate Data/Address Input
Student no # 0205002
0205003
0205004
0205014
0205026
0005069
8. Timing Diagrams: 
8.1. Fetch:  

CLK

CS

__
R/W

ADS1

ADS0

RAM

IR

PC

Control

 
 
 

13 |  
 
8.2. LDA address: 

CLK

ADS1

ADS0

IR

CS

_____
MEM

__
R/W

AccS1

AccS0

RAM

Acc

 
 
 

14 |  
 
8.3. STA address: 

CLK

ADS1

ADS0

IR

CS

_____
MEM

__
R/W

Acc

RAM

 
 
 
 
 
   
 
 
 

15 |  
 
8.4. MOV Acc, B: 

CLK

IR

ALU

AccS1

AccS0

Acc

 
 
 
 
 
 
 
 

16 |  
 
8.5. MOV B, Acc: 

CLK

IR

ALU

Bin

Acc

 
 
 
 
 
 
 
 
 
 
 
 

17 |  
 
8.6. MOV Acc, immediate: 

CLK

IR

ALU

AccS1

AccS0

Imm

Acc

 
 
 
 
 
 
 
 

18 |  
 
8.7. IN: 

CLK

IR

ALU

AccS1

AccS0

Input

Acc

 
 
 
 
 
 
 
 

19 |  
 
8.8. OUT: 

CLK

IR

ALU

Outin

Acc

 
 
 
 
 
 
 
 
 
 
 
 

20 |  
 
8.9. ADD B / ADC B / SUB B / SBB B / AND B: 

CLK

IR

ALU

AccS1

AccS0

Flagin

Acc

Flag

 
 
 
 
 

21 |  
 
8.10. ADD immediate / XOR immediate: 

CLK

IR

ALU

AccS1

AccS0

Flagin

Imm

Acc

Flag

 
 
 
 

22 |  
 
8.11. SHL: 

CLK

IR

ALU

AccS1

AccS0

Flagin

Acc

Flag

 
 
 
 
 
 
 
 
 
 
 

23 |  
 
8.12. SHR: 

CLK

IR

ALU

AccS1

AccS0

Flagin

Acc

Flag

 
 

8.13. NOP: 

CLK

IR

PC
 

24 |  
 
8.14. CMP B / TEST B: 

CLK

IR

ALU

AccS1

AccS0

Flagin

Acc

Flag

 
 
 
 

25 |  
 
8.15. SUB [address]: 

CLK

ADS1

ADS0

IR

CS

_____
MEM

__
R/W

AccS1

AccS0

Flagin

RAM

Acc

Flag

26 |  
 
8.16. JC address: 

CLK

IR

PCinC

CF

PC

CF

PC

 
 
 
 
 
 
 

27 |  
 
8.17. JE address: 

CLK

IR

PCinZ

ZF

PC

ZF

PC

 
 
 
 
 
 
 
 

28 |  
 
8.18. JMP address: 

CLK

IR

PCinC

PC

 
 

8.19. HLT address: 

CLK

IR

HLT

PC

 
 
 

29 |  
 
8.20. PUSH: 

CLK

ADS1

ADS0

IR

CS

___
Inc

STK

__
R/W

AccS1

AccS0

Acc

Stack

SP

 
 

30 |  
 
8.21. POP: 

CLK

ADS1

ADS0

IR

CS

Dec

STK

__
R/W

AccS1

AccS0

Stack

Acc

SP

 
 

31 |  
 
8.22. CALL address: 

CLK

ADS1

ADS0

IR

CS

___
Inc

STK

__
R/W

PC inU

PC

Stack

SP

 
 
 

32 |  
 
8.23. RET: 

CLK

ADS1

ADS0

IR

CS

Dec

STK

__
R/W

PC inU

Stack

PC

SP

 
 
   

33 |  
 
9. Explanation of Instructions:
9.1. Fetch:
During fetch cycle, Address MUX selects the PC output to address RAM. Also, Control signals
select RAM in reading mode. At the end of fetch the next instruction’s Opcode and immediate
data/address from the RAM is loaded into IR and the corresponding Control Signals are generated.
Finally, the PC value is incremented before the end of the fetch cycle.

9.2. Execution:
During execution cycle Control signals corresponding to the instruction being executed controls the
data and control flow of the computer according to the instruction. For every execution cycle except that
of HLT, /IRR = 0 is generated and as a result, at the end of the cycle, IR is reset and the Control Signal
for the fetch cycle is generated by the Control ROM

9.2.1. LDA address:

During the execution cycle of this instruction, RAM read operation is selected and RAM is
addressed by immediate address from IR through the Address MUX. BMUX selects the RAM data
to be selected on the B input of the ALU unit. This data is transferred through the ALU unit with
the help of ALU0-5 Control Signals and is stored in the Accumulator.

9.2.2. STA address:

For this instruction, RAM write operation is selected and RAM is addressed by the immediate
address from IR. The Accumulator data is transferred through ALU unit with necessary ALU0-5
Control Signals and is loaded into the RAM.

9.2.3. MOV Acc, B / MOV Acc, imm / IN:

B MUX selects B / immediate / input port data to go to the B in put of the ALU unit. This data is
transferred through ALU and is loaded into Accumulator.

9.2.4. MOV B,Acc / OUT:

The Accumulator data is passed through the ALU and is loaded into the B / Output register.

9.2.5. ADD B / ADC B / SUB B / SBB B / ADD imm / AND B / XOR imm:
BMUX selects B register output / immediate data from IR to pass to the B input of ALU unit. On
the A input of the ALU unit, Accumulator data is given. By means of the Control Signals ALU0-5,
the corresponding ALU operation is selected and the result is loaded into the Accumulator. Flagin
is also set to 1 and for all 4 flags ( ZF, SF, OF and CF ), the necessary input is generated by the
hardware depending on the result of the ALU operation. These values are then loaded into the
Flags.

9.2.6. CMP B / TEST B:

BMUX selects the B register output to be on the B input of the ALU unit. On the A input,
Accumulator value is supplied and the necessary ALU operation (SUB for CMP and AND for
TEST) is selected through ALU0-5. Depending on the result the Flag inputs are generated via
hardware and are loaded into the Flag register by setting Flagin into 1. But the ALU output is not
loaded into the Accumulator; rather the Accumulator data remains unchanged.

34 |  
 
 9.2.7. SUB [address]: 
RAM read operation is selected and immediate address from IR addresses RAM through Address
MUX. The output of the RAM is passed onto the B input of the ALU unit. On the A input, the
Accumulator data resides and SUB operation is selected by ALU0-5. The ALU result is then
loaded into the Accumulator and depending on the result necessary flag input is generated and
loaded into the Flag register.

9.2.8. SHL/SHR: 
AccS1 and AccS0 is so set that shift left / shift right operation is selected. Moreover, Accumulator
data is transferred through ALU unit and from its output the corresponding Flag input is generated
and loaded into the Flag register.

9.2.9. JC address: 
PCinC Control signal is set to 1 and as such it enables the parallel loading in the PC counter
provided that CF = 1. PCS is also set to 1 so that immediate address from IR is selected through PC
MUX. Hence, PC value is loaded with the immediate address when CF = 1 and effectively the
control flow jumps to the corresponding address.

9.2.10. JE address: 
PCinZ Control signal is set to 1 and as such it enables the parallel loading in the PC counter
provided that ZF = 1. PCS is also set to 1 so that immediate address from IR is selected through PC
MUX. Hence, PC value is loaded with the immediate address when ZF = 1 and effectively the
control flow jumps to the corresponding address.

9.2.11. JMP address: 
PCinU Control signal is set to 1 and as such it enables the parallel loading in the PC counter
unconditionally. PCS is also set to 1 so that immediate address from IR is selected through PC
MUX. Hence, PC value is loaded with the immediate address and effectively the control flow
jumps to the corresponding address.

9.2.12. PUSH: 
Stack write operation is selected and Stack is addressed by SP with the help of Address MUX. The
Accumulator data is transferred through ALU unit and the result is loaded into the Stack. At the
end of the cycle, SP is incremented by 1 since /Inc-Dec is kept at 0.

9.2.13. POP: 
Stack read operation is selected and Stack is addressed by ( SP-1 ) with the help of Address MUX.
This stack output is transferred through ALU unit and the result is loaded into the Accumulator. At
the end of the cycle, SP is decremented by 1 since /Inc-Dec is kept at 1.

9.2.14. CALL address: 
Stack write operation is selected and Stack is addressed by SP with the help of the Address MUX.
PC value is Stored into the Stack during the negative edge of the clock. Meanwhile PCinU is set to
1 so that PC is loaded unconditionally. PCS = 1 selects the immediate address to be loaded into the
PC. This address is loaded during the Rising edge of the clock and effectively transfers the control
flow at the start of the subroutine addressed by the immediate address. At the end of the cycle SP is
incremented by 1.

35 |  
 
 9.2.15. RET: 
Stack read operation is selected and Stack is addressed by (SP -1) with the help of the Address
MUX. Meanwhile PCinU is set to 1 so that PC is loaded unconditionally. PCS = 0 selects the
Popped address from the Stack to be loaded into the PC. This effectively transfers the control flow
to the caller subroutine at the point where it left off. At the end of the cycle SP is decremented by 1.

9.2.16. NOP: 
The RAM is in the read mode and for every register. Load is disabled by the Control signal. So, no
effective operation is done.

9.2.17. HLT: 
HLT signal is generated that stops the PC counting and /IRR is also set to 1 so that IR is not reset
to be in the fetch cycle. So, effectively, the computer just halts because it can not change its state.

11. How to Load / Write Programs:

For writing and loading a program into the computer, The RUN-/PROG switch is hold at 0.
Then the RAM address is selected via input address switches, the Opcode is given by the input
Opcode switches and the immediate data/address is provided by the input data / address
switches. Then at each clock pulse one instruction or one data is loaded into the memory

12. How to Run / Execute Programs:

Each instruction in our computer takes only two cycle to run: one cycle for being fetched
and the other for being executed. When the RUN-/PROG input is at 1 level, the computer is in
running mode. At the start of the running mode, the PC value is 0. Then, at each pair of clock
pulse, one instruction is executed until a HLT instruction is executed.

13. Special Features:

1. The Computer runs each instruction in only two clock cycles: one for fetching and one for
executing
2. RAM needs 200ns for its read/write. Hence, 250 ns for each half clock cycle is a safe
estimate. This fact ensures that the computer can run as fast as
3. 1 / 2 * 250ns= 2 MHz
4. Data length is 4 bit. for unsigned operations data range is 0 to 15 and for signed operation the
range is-8 to +7
5. 8 bit addressing makes up 256 blocks of available memory
6. Practically infinite stack. Stack is also addressed by 8 bits. So, 256 blocks of stack space is
provided for 256 blocks of memory, which is normally more than enough.
7. 4 Flag is kept to provide the user with the information regarding the status of the computer.
These 4 Flags are Sign Flag (SF), Zero Flag (ZF), Overflow Flag (OF) and Carry Flag (CF).

36 |  
 
14. ICs used with Count:
 
IC number Description Count
7404 Hex Inverter 2
7408 Quad 2-input AND 2
7427 Tri 3-inout NOR 1
7432 Quad 2 input OR 1
7486 Quad 2-input XOR 2
7483 4-bit full Adder 2
74126 Quad 4-bit buffer 3
74153 Dual 4x1 MUX 10
74157 Quad 2x1 MUX 4
74163 4 bit Up Counter with Synchronous reset and load 4
74181 4-bit ALU 2
74191 4-bit Up-down Counter with Asynchronous load 2
74194 4-bit universal shift register with synchronous load and 4
asynchronous reset
74257 Quad 2x1 tri-state MUX 1
74273 Octal D flip-flop with asynchronous reset 1
6116 2K x 8-bit RAM 2
2716 2K x 8-bit EPROM 3
Total 46

15. Discussion:

The design and implementation challenges were wonderful, excellent although sometimes
they created almost hopeless situations. We thoroughly enjoyed the task and furthermore this
assignment gave us the satisfaction of facing some challenges worthy of taking in real life as a
hardware designer. However, it has peeped into our mind that as a hardware designer, it might
have been enough to do the design with necessary simulation. The implementation challenges are
sometimes unnecessarily imposed. In spite of that, we were thrilled in every bit of the making of
the computer.

37 |