Analysis of Low-Dropout Regulator Topologies
for Low-Voltage Regulation
Sai Kit Lau, Ka Nang Leung, Member, IEEE and Philip K. T. Mok, Senior Member, IEEE
AbsIract-The design considerations of integrated CMOS
low-voltage lowdropout regulators are addressed in this paper.
The Limitations of a generic LDO based on dominant-pole
compensation are discussed Then, LDO with a voltage-bufler
stage and the corresponding problems in low-voltage design are
discussed. Finally, an advanced compensation technique based
on nested Miller compensation for achieving high performances
is presented.
I. INTRODUCI'ION
ORTABLE equipment such as cellular phones, PDAs
P
and laptop computers are in great demand in today's
market. This has intensified the focus of system designers on
reducing the size, minimizing power loss and optimizing the
performance of the power supplies. Of all the power supplies
in the market, they can be divided into two classes:
switching-mode power converters (SMPC)and linear voltage
regulators [I]-[ 121. Switching-mode power converters have
demonstrated high efficiency. However, switching noise
generated by SMPCs will superimpose into the supply voltage
and pass to the control circuits of the portable equipment
causing interference problem. Linear voltage regulators. on
the other hand, can convert an input voltage into a very stable
supply voltage, and the output noise is generally low. These
advantages make linear voltage regulators widely used in
noise-sensitive portable equipment, especially in wireless
telecommunication systems.
Nevertheless, the efficiency of the linear voltage regulators
are generally low [1]-[7], and the lifetime of the re-chargeable
battery is therefore greatly reduced. In order to increase the
lifetime of the re-chargeable battery and regulate the input
voltage when the voltage of the battery drops gradually,
low-power-consumption lowdropout regulators (LDOs)
have been developed [11-[121. The lowdropout feature can
effectively increase the lifetime of the rechargeable battery.
When the D O is implemented in CMOS technologies, the
low-ground-current feature is an advantage to portable
applications [1]-[7].
In this paper, the design of LDO in CMOS technology is
investigated. The stability issues of LDO are introduced and
discussed. The discussion on stability will firstly focus on the
conventional LDO with dominant-pole compensation scheme.
the LDO using a voltage buffer and the LDO using advanced
nested Miller compensation scheme are then presented.
X i s work was supported by the Research Grant Council of Hong Kong,
under project HKUST60ZUOIE.
The authors are with the Dep%tment of Electrical & Electronic
Engineering. the Xong Kong Uluvemiry of Science & Technolo~y.Clear
Water Bay, Hong Kong (E-mail: eedennir@ee.urt.h!c eealeung@ee.un.M
and eemok@ee.ust.hk)
0-7803-7749-4/03/$17.0002003 IEEE
II. STRUCTURE OF GENERICCMOS LDO
The structure of a generic CMOS LDO, which delivers a
load current (Ir).is shown in Fig. 1 [1]-[121. The regulator is
basically composed of a ptype pass transistor with voltage
gain A,, an error amplifier with a voltage gain A,, a set of
resistive feedback network R,, and 4.a load resistor RI., a
voltage reference V,, and a filtering capacitor CL with
equivalent series resistance RESR.
lL$Tf,:
Regulated output voltage..V
REsR
-
Fig. 1. Structure of a generic CMOS-LDO.
There are two poles and one zero in the LDO. The poles are
given bypl = l / C L(RL+REsR)andp, = l/C,Rl while the ESR
zero is given by ZEsR= I/CLRaR, where C , is the input
capacitance of the power pass transistor and RI is the output
resistance of the error amplifier.
It should be noted that as the pass transistor is in
common-source configuration with a negative voltage gain,
the feedback signal is connected to the positive input of the
error amplifier in order to achieve a negative feedback loop.
The bulk of the power PMOST is shorted to the source to
eliminate the substrate leakage. The error amplifier and
voltage reference have the same supply voltage (Vjn). In
addition, the voltage reference is a bandgap voltage reference
[ 13]-[21], a zener voltage reference or a buried-zener voltage
reference. However, zener and buried-zener voltage
references require a supply voltage greater than 5V. Thus.
bandgap reference is commonly used in low-voltage LDOs.
U. STABLIWOFLDO USNG DOMINANT-POLE
COMPENSATION
The value of ESR determines the output performance
during the load transient. The smaller the ESR value, the
better the performance with less overshoots and undershoots
during the load transient. In this paper, minimum ESR value
will be chosen. Thus, the ESR zero would not be involved in
the discussion since it locates at a very high frequency.
Generic LDO is compensated by the dominant pole pI to
achieve stability. As shown in Fig. 2, the position of the first
379
pole is located at a very low frequency (dominant pole PI). In
order to do so, the required value of C, is huge. In addition,
the change of the load current will change the position ofp,.
The dominant polep] is shifted to a higher frequency for
a higher load current and the LDO may he unstable at a certain
load as p2 may locate before the unity-gain frequency.
Therefore. the generic LDO should be compensated at the
maximum load current (the worst case). Smce p2 is generally
at low frequency as RI is large, the unity-gain frequency of the
loop gain is constrained by p2 and the loop response of the
LDO is slow.
load current incrraseJ
Fig. 2. Loop gain of a LDO using dominant pole
compensation with different load.
Fromthe above analyses, the W O using the dominant-pole
compensation usually has a narrow bandwidth and requires a
huge capacitor. As a large value of filtering capacitor is
required for frequency compensation, the possibility of
integration of LDOs is greatly reduced.
The above LDO (also the LDOs discussed later) has been
simulated using a standard 0.18-pm CMOS process
parameters. The considered output c w e n t range is from 51x4
to 2OmA. The quiescent current is 50w. The simulation
parameters are shown in Table 1 and the results are
summarized in the Table 2.
IV. STASUIY OF LDO USING BUFFER
In generic D O ,the unity-gain frequency is limited by the
high-impedance node that creates p2 since RI and C , are
usually quite large. In order to increase the unity-gain
frequency of the D O , a buffer stage can be interposed
between the output of the error amplifier and the input of the
power pass transistor, as shown in Fig. 3.
-
Unregulated inpur voltage Vjm
I implemented by the NMOS uansistor.
I nested Miller compensation technique for low-voltage
Fig. 3. Structure of LDO with voltage buffer.
380
By doing so, the low-frequency p2 is split into two higher
frequency poles p2’ andp2”. The two split poles are given by
p2’ = I/CprRb@andp2“ = l/Ch,RI, where Rh,is the output
resistance of the voltage buffer and Cw is the input
capacitance of the voltage buffer.
In general, Rbyand Cba,are much smaller than R, and C,,
respectively. Thus,p2’ and pz*’are much higher than p2 (i.e.
p2’andp~”>>pt).Moreover, the value of C,is usually quite
large (due to power MOS); therefore p2’, generally, is lower
thanp2”.
Since the two split poles are at much higher frequencies, a
smaller filtering capacitor C, can be used where the new
dominant pole PI” is at a higher frequency. Thus, the
unity-gain frequency of LDO increases, as shown in Fig 4.
Similar to the case using the dominant-pole compensation, the
LDO with a buffer stage should be compensated at the
maximum load current (the worst case).
The above LDO with a buffer has also been simulated and
the results are shown in Tables 1and 2. The filtering capacitor
used for the LDO with a buffer is smaller than that for the
generic LDO.Moreover, the unity-gain frequency of the LDO
-
with buffer stage is higher than that of the generic LDO for the
same load current
with smaller C,
UGF with buffer
\ IJGF \ /
\-
-/,.-..----*--
“e
P2’ frequency
P2 ---PP
Fig. 4. Loop gain of a LDO after adding buffer stage.
V. PROBLEMS OF LDO WlIM BUFFER IN LOW-VOLTAGE
DESIGN
A simple way to implement the buffer stage is to use a
PMOS or NMOS transistor in source-follower configuration.
However, there is one VGs voltage drop across the buffer.
Therefore, especially for the low-voltage design. say V,
=1.2V, the power pass transistor cannot be either fully tumed
ON or fully tumed OFF due to the extra VGsvoltage drop
across the buffer.
The power pass transistor cannot be fully tumed ON if the
buffer stage is implemented by the PMOS transistor. In
contrast, it cannot be fully w e d OFF if the buffer stage is
In addition, if the buffer implemented by PMOS Uansistor,
when ILincreases, the output transistors of the error amplifier
are forced to operate in biode region. R, value decreases and
low-frequency loop gain decreases as indicated in Table 2.
If the buffer stage is implemented by a simple PMOS or
NMOS transistor, either at low load or at heavy load condition,
the performance of the load regulation, line regulation and
load transient would be greatly degraded due to the reduction
of the loop gain. Therefore, a three-stage topology using
lowdropout regulator has been proposed.
 VI. ADVANTAGESAND STABarrY OFNEsTEDMlLLER Table 2: UGF, PM and low-frequency loop gain of the LDO
COMPMSAnON FOR LOW-VOLTAGE LDOS
In this section, W O based on the nested Miller
compensation is introduced. One of the structures based on
this compensation scheme is shown in Fig. 5 [121.

I
-
Unregulated input voltage V,,
T

Regulated output voltage V.

-
Fig. 5. LDO structure using nested Miller compensation
scheme.
In this smcture, an error amplifier with two gain stages is
used to provide a sufficient voltage gain. The power transistor
is considered as the third gain stage. Nested Miller
compensation technique with nulling resistor is used in this
scheme to achieve stability.
For this scheme, compensation capacitors C,, and Cm2are
4pF and IpF, respectively, as shown in Table 1. Moreover, a
IOOpF filtering capacitor is assumed to be the capacitance
from the power line. As no large filtering capacitor is required,
the whole LDO including the filtering capacitor can be
integrated into a single chip.
The simulated loop gains using the dominant-pole,
compensation, a voltage buffer stage and nested Miller
compensation are shown in Figs. 6.7 and 8,respectively. The
simulation results show that the unity-gain frequency of the Fig. 6. Loop responses of the LDO using
D O using nested Miller compensation is the highest for the dominant-pole compensation in different loads.
same load current. Moreover, with nested Miller
compensation, the LDO achieves almost constant loop gain _U-

and phase margin for the load current range under

consideration.

Vn. CONCLUSION
The stability of the LDO using dominant-pole
coqxnsation and using a voltage buffer stage have been
reviewed. A LDO based on three-stage amplifier using nested
Miller compensation has also been presented. This greatly
improves the unity-gain frequency and has been proven by .- , .. - -..- -
-I
,. ,_ ,.
simulations. As no large filtering capacitor is required, the
whole LDO including the filtering capacitor can be fully
integrated into a single chip. Therefore, it is well suited for
D O S low-voltage applications such as cellular phones,
pagers and PDAs.

Table 1: Parameters of the LDO with different compensation

scheme.
I I GenericLDO I LDOwitha I Three-staee I
.- . ,. ,- I
.
--y_
._ ._ ..
Fig 7 Loop responses of the LDO using a buffer stage
in different loads.

38 I

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