________________________________________________________________________

MR. ANGEL J. MARIANO, JR.

1735 WOLVISTON WAY
SAN DIEGO, CA 92154
(619) 575-6875
________________________________________________________________________________
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JOB OBJECTIVE:
A technical writing position where strong communications skills -- both oral and
written -- and a well rounded technical background would be fully utilized to f
urther the goals of the organization.
AREAS OF EFFECTIVENESS
COMMUNICATION: To train Engineering design teams, I wrote the following documen
ts: (1)Integrated Circuit (IC) Design Guidelines; (2)Easy-to-understand guidelin
es for performing Current Density and IR bus drop analyses on integrated circuit
s; (3) Procedures for building integrated circuits using automated CAD tools; an
d (4) Specifications for two classified defense programs. Also trained new hire
s; good with people.
ANALYTICAL: As a chip layout designer, proficient in designing high speed libra
ry CMOS cells utilizing detailed current density calculations. Involved strikin
g a delicate balance between meeting high current density requirements and perfo
rmance. Can interact well with Design Engineers on technical issues. Made writ
ten recommendations to managers on how to improve overall turn-around time & eff
iciency, which were implemented.
LEADERSHIP: (1)United States Naval Officer with 4 years commissioned service.
Billets included Communications Officer, Electronics Material Officer, and COMSE
C Custodian managing cryptographic equipment & supplies. An effective division
officer, my division was awarded Communications Green aCa Award for excellence i
n Navy Communications Operations and received outstanding marks in all Refresher
Training Exercises. Received Honorable Discharge at the Grade of O-3 (Lieutena
nt, U. S. Navy). TOP SECRET CLEARANCE HELD.
EDUCATION
Four-Year Naval ROTC Scholarship to the University of Southern California (USC).
Bachelor of Science in Electrical Engineering awarded in June 1979.
Hughes Aircraft Masters Fellowship to the University of California, Irvine (UCI)
.
Master of Science in Engineering awarded in June 1987.
UNDERGRADUATE HONORS: Tau Beta Pi & Eta Kappa Nu National Engineering Honor Soc
ieties.
GRADUATE HONORS: Hughes Aircraft Company Fellowship & Rotation Student, 1984-19
88
PROFESSIONAL WORK EXPERIENCE:
Qualcomm Incorporated, Senior Layout Designer 06/2008 thru 04/2009
a Utilized Cadence Design Systems Software and Virtuoso XL (schematic-driven lay
out tool) to perform custom layout in TSMC13 Hardware: Linux Workstation.
a Brainstormed, spearheaded, and developed a design methodology to accommodate a
 new design rule driven CAD tool; led this design task. Saved the company time
& money on current and future projects. Received commendation from management.

Applied Micro Circuits Corp. (AMCC), Staff Layout Designer 11/2000 thru 05/2008
a Utilized Cadence Design Systems Software and Virtuoso XL (schematic-driven lay
out tool) to perform custom layout in the following technologies --- TSMC65, TSM
C90, TSMC13, & UMC13. Hardware: Linux Workstation.
a Proficient in designing high speed library CMOS cells utilizing detailed curre
nt density calculations.
a Wrote IC Design Guidelines and papers on IR Bus Drop & Current Density analysi
s for training purposes. Successfully trained new hires.
a Responsible for PG (tape-out) release of chips to manufacturing. Required wor
king knowledge of Synchronicity Database Management System, coordination with th
e chip fab, & communication skills.
a During my 8-year tenure at AMCC, company retained me during all Reductions-In-
Work-Force, totaling over 7 layoffs.
Texas Instruments (formerly Silicon Systems Inc.), Mask Design Engineer Level II
5/1994 thru 11/2000
a Utilized Mentor Graphics ICgraph Software & Schematic Driven Layout (SDL) to p
erform custom layout for bipolar technologies.
a Led 3 re-design projects.
a Awarded Texas Instruments Presidentas Achievement Award in 1996.
a Was proficient in ICblocks/CCT Automatic Place & Route (APR) tool to route top
level designs.
a Compiled written procedures for building integrated circuits using automated C
AD tools.
a Supported Device Structure and Design Automation (DA) Engineers in performing
test cases.
Hughes Aircraft Company (now Raytheon Corp.), Member Technical Staff Level II
7/1984 thru 11/1991
a Design & development of digital Silicon-On-Sapphire (SOS) ASICs using standard
cells.
a Completed verification & tapeout of three Hughes Space & Communications chips
using Cadence Edge Automatic Place & Route (APR) tool & Dracula Verification sof
tware.
a Wrote IC Design Guidelines for Hughes Space & Communications Group EHF Satelli
te Program.
a Designed front-end board for testing Focal Plane Array (FPA) infrared detector
s.
a Designed, built, and tested pre-amp buffering circuits for diagnostic testing
of FPA.
a Systems Engineering Specification Writer for classified military communication
s program.
a SECRET CLEARANCE HELD.
General Dynamics Convair Division, Systems Engineer 10/1983 thru 5/1984
a Systems Engineering Specification Writer for classified military weapons proje
ct.
a SECRET CLEARANCE HELD.
Lieutenant, United States Navy 6/1979 thru 7/1983
a COMSEC Custodian of cryptographic equipment & material.
a Communications Officer & Electronic Materials Officer. Managed Radiomen, Elec
tronic Technicians, & Fire Control (Missile Systems) Technicians.
a Awarded Communications Green aCa for excellence in Navy Communications Operati
ons and grades of aOUTSTANDINGa in all Refresher Training Exercises.
a TOP SECRET CLEARANCE HELD.

REFERENCES: Available Upon Request.