VIDEO SOLUTIONS

Rev. 1.1
LATTICE AT A GLANCE

• Founded 1983; IPO 1989 (NASDAQ: LSCC)

• ~750 employees
• Develops programmable products which allow the end customer to
determine functionality
• $297.8M revenue in 2010, $194.4M in 2009
• Customers are primarily in the communications, computing, video,
consumer, and industrial end markets
• Product development, manufacturing, and sales offices worldwide
• World class quality certifications: ISO 9000, ISO/TS 16949, AEC-Q100

In the last ten years

Lattice has sold over
1 Billion
programmable devices

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LATTICE HDR-60 VIDEO CAMERA DEVELOPMENT KIT
Overview

Fully
Production-
Ready HD
Video
Camera
Major
with HDR Application:
Security &
Surveillance
Other Cameras
Applications:
Traffic,
Automotive,
Video Full HD
Conferencing 1080p60
Capable HDR
Image
Signal
Processing Industry
(ISP) Pipeline Leading Auto
Exposure,
High Dynamic
Range &
Auto White
Balance
Price $399

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LATTICE HDR-60 VIDEO CAMERA DEVELOPMENT KIT
Kit Contents

• Lattice HDR-60 Video Camera Main Board

• Lattice Nanovesta Sensor Board
• 1 x HDMI Cable
• 1x HDMI – DVI Adapter
• 2 x Standard USB Programming Cables
• Universal Power Supply
• Quick Start Guide Lattice HDR-60
Video Camera Development Kit

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LATTICE VIDEO CAMERA DEVELOPMENT KIT DEMO SETUP
Plug-and-Play Demo

HDMI / DVI Monitor

HDMI / DVI cable

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LATTICE VIDEO CAMERA DEVELOPMENT KIT
Color Image Signal Processing (ISP) Pipeline from Helion

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HELION AT A GLANCE

• Founded 2003 as a spin-off company from the

Fraunhofer Institute
• More than 15 years experience in HDR/WDR and
image pre-processing
• Engineering Services in customized digital cameras and display
systems
• Complete image processing solution from sensor to display, called
IONOS™
• Consulting in image sensor configuration and FPGA programming
• Solutions in the field of Automotive, Medical, Security, Industrial
• Inventor of the WDR/HDR-BLENDFEST™ technology and the IONOS™
IP suite
More than
90
Image Processing IP cores available

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HDR: High Dynamic Range

Intensity of brightest area

Dynamic Range = Ratio of Intensity of darkest area
expressed in dB
HDR
Higher the dynamic range the better we can see detail in both light
and dark areas. HDR combines multiple exposures of different
duration and blends to form a clear image for both light and dark areas

• High Dynamic Range Processing With Tone Mapping

• Builds internal image statistics (histogram, average and
median values) to calculate for each frame two
adaptive global tone map transfer curves and uses local
tone mapping for contrast enhancements.

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CMOS SENSOR INTERFACING ROADMAP

• Sensors resolutions and frame rates have increased vastly

– Previously dominant CMOS parallel interface is no longer able to handle the
bandwidth requirements.
– Sensor manufactures have resorted to high-speed serial interfaces
– e.g. Aptina Imaging has introduced HiSPi
– HiSPi can operate from 1 to 4 lanes of serial data and 1 clock lane
– Each lane can operate up t0 700Mbps

• Need for serial to parallel sensor interface bridging

– Majority of ISP devices support traditional CMOS parallel sensor interfaces
– They usually lack interfaces that support serial
– Therefore a bridge device is required to convert the serial data to a parallel
format.

• The Lattice XP2-5 non-volatile FPGA provides an efficient and cost-effective

solution for HiSPi to parallel bridging.

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SUMMARY
Lattice HDR-60 Video Camera Development Kit

Fully production ready design

HDR 1080p60 capable FPGA stream

processing

Industry-leading features:
- Fast auto exposure
- 120dB+ High Dynamic Range
- Support for up to 16MP sensors

Comprehensive Image Signal

Processing library

Low cost BOM

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CMOS SENSOR INTERFACING
Ideal Fit for Lattice XP2

• Small Form Factor and Non-Volatility Ideal for tight

inside-camera real-estate requirements

• Sub-LVDS Support Well-Documented (TN1210)

• XP2-5 and XP2-8 devices support the required Orion Nanovesta Board
price-points and code footprints

• Hi-Spi Design already developed,

XP2 interfaces between the Aptina HiSpi
sensor and a parallel bus to the TI DM385.
Productization Q1 2011

• Other Sensors in Roadmap

• Easy to Leverage Orion Board for Sensor I/F Eval

– Replace Orion’s Nanovesta Sensor Board with
available XP2 sensor I/F Board Orion Baseboard

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Video Interface Solutions

• HDMI/DVI Physical Interface

• Single-Link DVI Standard = 1.65 Gbps / Channel

• Single-Link HDMI Standard = 3.4 Gbps / Channel

• Validated on Lattice Devices = 1.65 Gbps / Channel

• 7:1 LVDS Physical Interface

– LCD display panel interface
– 750 Mbps / LVDS pin pair in ECP3 FPGAs

• SMPTE SDI Tri-rate Interface

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LATTICE HDMI PHYSICAL INTERFACE (RD1097)

HDMI Physical Interface Reference Design (RD1097)

Interface TMDS Interface

Serializer Word &
with Encoding TMDS with
for De-serializer Channel
HDMI for HDMI Data De-coding HDMI
Efficiency Alignment
Digital IP Reliability Digital IP

Transmitter Receiver On GDA

Roadmap

• Requires SERDES Channels with PLLs for Reliable Data Recovery

– To Eliminate Inter-channel Skew
– Both Transmitter and Receiver Solution
– Available for LatticeECP3 and LatticeECP2M

• Physical Layer Interface for Reliable and Efficient Communication

– Reliability
• TMDS Encoding of Video Data for EMI Reduction
• TERC-4 Encoding of Voice Data for EMI and Error Reduction
• PCS Logic for Data Alignment within a Channel
• Hsync and Vsync Control Characters for Channel Alignment
– Efficiency
• Data Serialization and De-serialization Using Precision SERDES
– Common Interface with HDMI Protocol / Content Processors
• To Interface with 3rd Party HDMI Digital IP Cores (e.g., from GDA)

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 LATTICE 7:1 LVDS PHYSICAL INTERFACE (RD1030)

7:1 LVDS Physical Interface Reference Design (RD1030)

4-Bit LVDS Data High-speed 1 bit

7:4 IO DDR IO DDR 4:7
LVDS
Serializer Registers Registers De-serializer
Buffers

(7*4) Bit (7*4) Bit

Parallel LVDS Clock Parallel
LVTTL PLL (*3.5) PLL (*3.5) LVTTL
Data Data

Transmitter Receiver

• Leverages Pre-engineered I/O Components in all Lattice FPGA Families

– Source Synchronous LVDS I/Os (up to 900 Mbps Performance)
– LVDS Buffers, DDR Registers, Configurable PLLs, and Gearbox Logic
– Available for LatticeECP3, LatticeECP2M, and LatticeXP2

• Physical Layer Interface for Reliable and Efficient Transmission

– Reliability
• Data Capture
– High-speed LVDS Buffers
– DDR Registers for Data Capture on both Rising and Falling Edges
• Skew Minimization
– Logic for Skew Minimization between Data and Clock Channels
– Efficiency
• Data Serialization and De-serialization using Precision PLLs
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SMPTE SDI

• Tri-rate RX/TX SD-SDI, HD-SDI and 3G-SDI interfaces

• Support for 3G source formats, including 3G Level-B format: SMPTE

425M [10]

• Word alignment and timing reference sequence (TRS) detection

• Field, vertical blanking (vblank) and horizontal blanking (hblank) timing

signals generation

• CRC computation, error checking and insertion for HD/3GLine number

(LN) decoding and encoding for HD/3G

• Video Payload Identifier (VPID) insertion and extraction for HD/3G

• 10-bit parallel input/output support for SD

• Soft-logic based low data-rate (LDR) serializer for SD transmission

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VIDEO INTERFACES DEVELOPMENT KIT
Available To Demonstrate* Capabilities Of 3 Video Interfaces

• 4 Evaluation Boards
– ECP3 Video Protocol Evaluation Board (Board #1)
– 7:1 LVDS to DVI Converter Board (Board #2)
– DVI to 7:1 LVDS Converter Board (Board #3)
– HDMI Mezzanine Card
– All Necessary Cables and Power Supplies

• 3 Pre-built Demo Systems

– DVI to 7:1 LVDS Video Conversion Demo
– HDMI / DVI Loopback Demo
– HDMI Transmission Demo

• Documentation
– User’s Guides for Reference Designs, IP Core, Eval
Boards, & Demos
– Instructions to Setup and Operate the Demos
– Lattice Sales Tools on eLearn
• Customer Presentation, Lobby Pitch, Marketing
Bulletin, etc.

*
These are “Loaner Kits” Only, for Lattice FAEs in Various Regions
They are not meant for Customer Purchase
Please Contact Your Local HDBU Marketing Rep for Obtaining the Kit

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ECP3 VIDEO PROTOCOL BOARD +
HDMI MEZZANINE CARD
• Used To Demonstrate HDMI / DVI Loopback Demos
• Simple Pass Through Demos with both Video and Audio
• HDMI Mezzanine Card has 2 Rx Connectors and 1 Tx Connector
• Only Single Link HDMI and DVI
Ch_algn_err Rx_format
Ch_algned Tx_plol
Word_algn_err Rlol
Rsvd
Word_algned Rlos

LED

HDMI
OUT
Lvl
Shft

HDMI
Enc

Tx

IN2
Dec

Rx

HDMI
IN1
EQ

From left to right:

Rawdata_loopback,
Audio_Mute,
B Red_Fill, Green_Fill, Blue_Fill
3 VP I
ECP . C Rsvd HDM ne
Rev a i
n
Me z z . B
Rev

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Summary of Lattice FPGA Value in
Video Camera Front End
• FPGA offers a flexible method to implement image processing
algorithms using
– Existing IPs or
– Custom-built IP created by end-user
– ECP3 offers the proper mix of DSP blocks, memories, and IOs for cost
effective video design

• Integration of most common types of video interfaces within the FPGA

– HDMI/DVI
– LVDS
– SMPTE SDI

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THANK YOU
 Back Up Slides

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 LatticeECP3 Family Overview

Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

LUTs (K) 17 33 67 92 149
EBR SRAM Blocks 38 72 240 240 372
EBR SRAM (Kbits) 700 1,327 4,420 4,420 6,850
Distributed RAM (Kbits) 36 68 145 188 303
18x18 DSP Multipliers 24 64 128 128 320
3.2Gbps SERDES Channels 4 4 12 12 16
Maximum User I/O Pins 222 310 490 490 586
PLLs + DLLs 2+2 4+2 10+2 10+2 10+2

Key Features:

•Full Featured sysDSP Blocks running at > 400 MHz

•Up to 320 18x18 multipliers
•Cascadable, slice-based architecture
•Up to 6.85Mbit Block RAM

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Benefits of FPGAs in Video Processing Applications

• Video processing uses DSP functions

• FPGA DSP implementation is more deterministic than DSP processor.

• DSP Processors need to operate ~ 100x the Sample Rate of a System. FPGAs
can be used in High Sample Rate Applications where Parallelism is present.

• FPGAs use smaller independent memory elements, removing data bottlenecks and
faster access.

• Evolving maturity of design tools for FPGA based DSP designs.

• FPGA programmability allows designers to trade-off device area vs. performance

by selecting the appropriate level of parallelism to implement their functions.

• FPGAs can exceed the computing power of DSPs with their inherent parallelism,
breaking the paradigm of sequential execution and accomplishing more per clock
cycle.

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Lattice ECP3 sysDSP vs. XP2/ECP2/M sysDSP

XP2/ECP2/M: 18

1. No Dual Slice or Cascade capabilities 18

2. Need external FPGA resources to create adder
tree M M M M
3. Accumulator excludes other multiplier—need
additional DSP or Fabric Logic A A

ECP3:
1. Has Dual Slice and Cascade
capabilities
2. Internal accumulate or cascade to next
slice for wider tree 18
3. New Modes (MMAC, Adder Tree, Wide
18 18
Mux, Barrel Shifter)
4. 54-bit Cascadable ALU supports
rounding and truncation. M M M
M
5. Neighboring ALU output chainable as 54
third input for ternary adders A 54
A
6. Total DSP capability of up to 128,000
Million Multiply accumulates per second
(MMACs) SLICE 0 SLICE 1

Single sysDSP block

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 XP2/ECP2/M vs. ECP3 FIR Filter Comparison
Transposed FIR Filter using MULTADDSUB and ADDER Tree (XP2, ECP2 and ECP3)

Data_A
z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1

+ + + +
slice ‘3’ slice ‘2’ slice ‘1’ slice ‘0’
ECP3: 370 MHz for sysDSP
MULTADDSUB
ECP3: ~260 MHz for Fabric
+ +
ECP2: ~260 MHz for Fabric
Lower Latency
+

ADDER TREE

Transposed FIR Filter using MULTADDSUBSUM and Cascading (ECP3)

Data_A
z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1

+ z-1 + z-1 + z-1 +

slice ‘3’ slice ‘2’ slice ‘1’ slice ‘0’

MULTADDSUBSUM
ECP3:400 MHz, Higher Latency

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Common Video Resolution

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