KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

INTRODUCTION
100 QFP-1420 The KS0107B is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display system. This device provides 64 shift register and 64 output driver. It generates the timing signal to control the KS0108B segment driver. The KS0107B is fabricated by low power CMOS high voltage process technology and compose of the liquid crystal display system in combination with the KS0108B segment driver.

FEATURES
Dot matrix LCD common driver with 64 channel output. 64 bits shift register ot internal LCD driver circuit. Internal timing generator circuit for dynamic display. Selectable master/slave mode. Applicable LCD duty: 1/48, 1/64,1/96,1/128 Power supply voltage: + 5V 10% LCD driving voltage: 8V~17V(V -VEE) DD Interface Driver COMMON Other KS0107B SEGMENT KS0108B MPU controller

High voltage CMOS process. 100QFP and bare chip available.

KS0107B
BLOCK DIAGRAM

64CH COMMON DRIVER FOR DOT MATRIX LCD

C1 C2 C3

C62 C63 C64

V0L V1L V4L V5L

64 bits LCD driver

V0R V1R V4R V5R

64 bits bidirection shift register

DIO1 PCLK2 SHL

Data shift direction Phase selection control circuit

DIO2

M CL2 C R CR Timing generator cirecuit

OSC

FRM CLK1 CLK2

VDD

VSS

VEE

DS 1

DS 2

MS

FS

Fig. 1. KS0107B Functional block diagram

64CH COMMON DRIVER FOR DOT MATRIX LCD

V1R

V4R

V5R

CL2 V OR V EE NC 58 57 56 55 54 53 52

C 43

C 44

C 45

C 46

C 47

C 48

C 49

C 50

C 51

C 52

C 53

C 54

C 55

C 56

C 57

C 58

C 59

C 60

C 61

C 62

C 63

C 64

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

51

NC

C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 97 98 99 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82

81

50 49 48 47 46 45 44 43 42 41

DIO2 PCLK2 NC M FRM NC CLK1 CLK2 MS NC

KS0107B

40 39 38 37 36 35 34 33 32 31

VSS SHL

CR NC R NC C DS2 DS1

PIN CONFIGURATION

C25 C24 C23 100

KS0107B

1 C 22

2 C 21

3 C 20

4 C 19

5 C 18

6 C 17

7 C 16

8 C 15

9 C 14

10 C 13

11 C 12

12 C 11

13 C 10

14

15

16

17

18

19

20

21

22

23 V EE

24 V1L

25 V4L

26 V5L

27 V0L

28 V DD

29 DIO1

30

FS

C9

C8

C7

C6

C5

C4

C3

C2

C1

Fig. 2. 100 QFP Top View

NC

KS0107B
PIN DESCRIPTION
PIN(NO) 28 40 23,58 27, 54 24, 57 25, 56 26, 55 SYMBOL VDD VSS VEE V0L, V0R V1L, V1R V4L, V4R V5L, V5R

64CH COMMON DRIVER FOR DOT MATRIX LCD

INPUT/OUTPUT DESCRIPTION Power For internal logic circuit (+5V10%) GND (0V) For LCD driver circuit Power Bias supply voltage terminals to drive LCD. Select Level V0L(R), V5L(R) Non-Select Level V1L(R), V4L(R)

42

MS

Input

39

SHL

Input

V0L and V0R is connected by the same voltage. Selection of master/slave mode i) Master mode (MS=1) DIO1, DIO2, CL2 and M is output state. ii) Slave mode (MS=0) SHL=1 DIO1 is input state(DIO2 is output state) SHL=0 DIO2 is input state(DIO1 is output state) CL2 and M is input state. Selction of data shift direction. SHL H L Data shift direction DIO1C1 ... C64DIO2 DIO2C64 ... C1DIO1

49

PCLK2

Input

Selection of shift clock (CL2) phase. PCLK2 H L shift clock(CL2) phase data shift at the rising edge of CL2 data shift at the falling edge of CL2

30

FS

Input

31 32

DS1, DS2

Input

Selection of oscillation frequency. i) Master mode When the freme frequency is 70Hz, the oscillation frequency should be fosc=430KHz at FS=1 (VDD) fosc=215KHz at FS=0 (VSS) ii) Slave mode Connect to VDD. Selectiom of display duty. i) Master mode DS1 L L H H DS2 L H L H Duty 1/48 1/64 1/96 1/128

ii) Slave mode : Connect to VDD.

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

PIN DESCRIPTION (continued)

PIN(NO) 33 35 37 SYMBOL C R CR INPUT/OUTPUT RC Oscillator i) Master mode
KS0107 R Rf CR Cf open external clock open

DESCRIPTION

KS0107B
C R

KS0107B
CR

KS0107 C

ii) Slave mode

R CR C

open

V DD

open O PEN

44, 43

CLK1, CLK2 FRM

Output

46

Output

47

Input/Output

52

CL2

Input/Output

29 50

DIO1 DIO2

Input/Output

Operating clock output for the KS0108B i) Master mod Connection to CLK1 and CLK2 of the KS0108B ii) Slave mode Open Synchronous frame signal. i) Master mode Connection to FRM of the KS0108B ii) Slave mode Open Alternating signal input for LCD driving. i) Master mode: output state Connection to M of the KS0108B ii) Slave mode: input state Connection to the controller Data shift clock i) Master mode: output state Connection to CL of the KS0108B ii) Slave mode: input state Connection to shift clock terminal of the controller. Data input/output pin of internal shift register. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input

22~1 100~59

C1~C64

Output

Common signal output for LCD driving. DATA L L H H M L H L H OUT V1 V4 V5 V0

34,36,38,41 45,48,51,53

NC

No Connection

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

MAXIUM ABSOLUTE LIMIT

Characteristic Operating Voltage Supply Voltage Driver Supply Voltage Symbol VDD VEE VB VLCD T OPR T STG Value -0.3~+7.0 VDD-19.0~VDD+0.3 -0.3~VDD+0.3 VEE-0.3~VDD+0.3 -30~+85 -55~+125 Unit V V V V C C Note *1 *4 *1,2 *3,4 -

Operating Temperature Storage Temperature *1. Based on VSS=0V *2. Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)) *3. Applies to V0L(R), V1L(R), V4L(R) and V5L(R). *4. Voltgae level: VDD V0L=V0R V1L=V1R V4L=V4R V5L=V5R VEE.

ELECTRICAL CHARACTERISTICS
DC Characteristics DD=+5V 10%, VSS=0V,l VDD-VEE l =8~17V, Ta=-30 ~ +85C) (V Characteristic Symbol condition Min Typ Max Unit Note Input High VIH 0.7VDD VDD V *1 Voltage Low VIL VSS 0.3VDD Output Hogh VOH IOH=-0.4mA VDD-0.4 V *2 Voltage Low VOL IOL=0.4mA 0.4 Input Leakage Current ILKG VIN=VDD~VSS -1.0 1.0 *1 A OSC Frequency fOSC 315 450 585 KHz Rf=47K2% Cf=20pf5% On Resistance RON VDD-VEE=17V 1.5 K (Vdiv-Ci) Load current 150A Operating Current IDD1 Master mode 1.0 mA *3 1/128 Duty IDD2 Slave mode 200 *4 A 1/128 Duty Supply Current IEE Master mode 100 *5 1/128 Duty Operating fop1 Master mode 50 600 KHz External clock Frequency fop2 Slave mode 0.5 1500 *1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. *3. This value is specified about current flowing through VSS. Internal oscillation circuit: Rf=47k, Cf=20pF Each terminals of DS1, DS2, FS, SHL and MS is connected to V and out is no load. DD *4. This value is specified about current flowing through VSS. Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to V , MS is connected to VSS and CL2, DD M, DIO1 is external clock. *5. This value is specified about current flowing through VEE. Dont connect to VLCD (V1~V5).

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

AC Charcteristics(VDD=5V10%, Ta=-30C~+85C)
(1)Master mode(MS=VDD, PCLK2=VDD, Cf=20pF, Rf=47K)
CL2
0 . 7 V DD 0 . 3 V DD

tW L C tW H C tS U tD H ts u tW H C tD

DIO1 ( SHL = VDD ) D I O 2 ( S H L = VSS

)

DIO2 ( SHL = VDD ) D I O 1 ( S H L = VSS

)

tD tD F

FRM tD M tD M M tF tR tW H 1 0.7VDD 0 . 3 VD D

CLK1

tW L 1

tD I 2 tD 2 1

CLK2 tW H 2

tF

tR

Characteristic Data Setup Time Data Hold Time Data Delay Time FRM Delay Time M Delay Time CL2 Low Level Width CL2 High Level Width CLK1 Low Level Width CLK2 Low Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise/Fall Time

Symbol tSU tDH tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/tF

Min 20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 -

Typ -

Max 2 2 150

Unit

ns

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

tF CL2 tR

tWLC1 - 0.7VDD - 0.3VDD

( PLK2 = VSS ) tSU tWHC2 CL2 ( PLK2 = VDD ) tR DIO1 ( SHL = VDD ) DIO2 ( SHL = VSS ) Input Data tH tF tD
tDH hcl
- 0.7VDD - 0.3VDD

tWHC1 tWLC

DIO1 ( SHL = VDD ) DIO2 ( SHL = VSS ) Output Data

(2) Slave mode(MS=VSS)

- 0.7VDD - 0.3VDD

Characteristics CL2 Low Level Width CL2 High Level Width CL2 Low Level Width CL2 High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time CL2 Rise/Fall Time *1; Connect load CL=30pF

Symbol tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR/tF

Min 450 150 150 450 100 100 10 -

Typ -

Max 200 30

Unit ns ns ns ns ns ns ns ns ns

Note PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD

*1

OUTPUT 30pF

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

FUNCTIONAL DESCRIPTION
1.RC Oscillator The RC Oscillator generates CL2, M,FRM, of the KS0107B and CLK1, CLK2 of the KS0108B by the oscillation resister R and capacitor C. When selecting the master/slave, oscillation circuit is as following: 1) Master Mode

KS0107B R Rf
2) Slave Mode

KS0107B

CR

C Cf

CR

open external clock

open

KS0107B R CR C

open V DD

open Open

2. Timing Genertion Circuit It generates CL2, M, FRM, CLK1, and CLK2 by the frequency from oscillation circuit. 1) Selection of Master/Slave (M/S) When M/S, is H, it generates CL2, M, FRM, CLK1, and CLK2 internally. When M/S isL, it operates by receiving M, CL2 from master device. 2) Frequency Selection (FS) To adjust FRM by 70Hz, the oscillation frequency should be as following: FS H L Oscillation Frequency fOSC=430KHz fOSC=215Khz

In the slave mode, it is connected to VDD. 3) Duty Selection (DS1, DS2) It provides various duty selection according to DS1, DS2. DS1 L H DS2 L H L H DUTY 1/48 1/64 1/96 1/128

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

3. Data Shift & Phase Select Control 1) Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according to PCLK2. PCLK2 H L Phase Selection Data shift on rising edge of CL2 Data shift on falling edge of CL2

2) Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input Direction of Data C1C64 C64C1 DIO1C1C64DIO2 DIO2C64C1DIO1

KS0107B
TIMING DIAGRAM

64CH COMMON DRIVER FOR DOT MATRIX LCD

(1) 1/48 duty timing (Master mode) Condition: DS1=L, DS=L, SHL=H(L), PCLK2=H

C CLK1 1 CLK2 2 3 63 64

CL2 FRM DIO1 ( DIO2 ) M C1 ( C48 ) V1

46

47

48

46

47

48

V0 V1 V4 V4 V0 V4 V1 V0 V1 V5 V5 V1

V0

C2 ( C47 ) V1

V4

C47 ( C2 ) V5 C48 ( C1 ) V1 DIO2 ( DIO1 ) V5

V4 V4

V4

V1 V5 V1

V1

V4

V0

V4 V5

- relation of CL2 DIO1 ( DIO2 )

CLK2 CL2

DIO1 ( DIO2 )

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

(2) 1/128 duty timing (Master mode) - Condition: DS1=H, DS2=H, SHL=H(L), PCLK2=H

C CLK1 1 CLK2 2 3 23 24

CL2 FRM DIO1 ( DIO2 ) M C1 ( C48 ) V1

126

127

128

126

127

128

V0 V4 V4 V0 V4 V1 V0 V1 V5 V5

V0 V1

C2 ( C47 ) V1

V1

V4

C47 ( C2 ) V5 C48 ( C1 ) V1 DIO2 ( DIO1 ) V5

V4 V4

V4

V1 V5 V1

V1

V4

V0

V4 V5

- relation of CL2 DIO1 ( DIO2 )

CLK2 CL2

DIO1 ( DIO2 )

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

(3) 1/48 duty timing (Slave mode) - Condition: PCLK2=L, SHL=H(L)

1 CL2

46

47

48

46

47

48

DIO1 ( DIO2 )

C1 ( C48 ) V1

V0 V4 V5

V1

V0

C2 ( C47 )

V1 V4

V0 V4 V1 V5

V1 V4

V0 V1 C47 ( C2 ) V4 V4 V5 V0 V4 C48 ( C1 ) V5 V5 V1 V4 V1 V1 V4

DIO2 ( DIO1 )

KS0107B
(4) Power driver circuit

64CH COMMON DRIVER FOR DOT MATRIX LCD

VDD

V0 V0L/R R1 V1 V1L/R R1 V2 R2 V3 R1 V4 V4L/R R1 V5 V5L/R VR KS0108B

VDD

KS0107B

VEE

VEE

elation of duty & bias DUTY BIAS Rdiv 1/48 1/8 R2=4R1 1/64 1/9 R2=5R1 1/96 1/11 R2=7R1 1/128 1/12 R2=8R1 *When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1+R2)=1/8 R1=3K, R2=12K

V DD 15

KS0107B

15

RS

R/W

CS3

R/W E

CS1B

CS2B

CS1B

RSTB

FRM M CLK1 CLK2 CL Rf Cf V SS VSS S1~S64 S1~S64 VEE CL KS0108B V5R/L CLK2 KS0108B V3R/L CLK1 V2R/L M

FRM

RSTB

CS2B V0R/L V2R/L V3R/L V5R/L VEE

DB0 ~ DB7

DB0 ~ DB7

APPLICATION CIRCUIT

V0R/L

FS

VDD

SHL

MS

DS2

DS1

CR

V SS V OR/L C64 V IR/L V 4R/L V 5R/L V EE FRM CLK1 CLK2 M CL2 DIO2 DIO1 open open M CL2 DIO1 FRM C64 PCLK2 FS DS1 DS2 R CR C FRM CLK1 CLK2 SHL CLK1 CLK2 RS R/W E CL VDD VSS RSTB KS0107B (Slave) M V EE V0R/L KS0108B V2R/L V3R/L V5R/L CS1B CS2B CS3 COM128 KS0107B (Master)

PCLK2

-1/128 duty Segment drive(KS0108B) Interface circuit

C1 COM1

LCD PANEL

5 VDD VOR/L VIR/L V4R/L V5R/L VEE VSS MS DIO2 C1

CS3 VEE V0R/L V2R/L V3R/L V5R/L CS2B CS3

VDD

VDD

RS

FRM M CLK1 DB0 ~ DB7 CLK2 RS R/W

RSTB CL VDD V SS 15 RS R/W E RSTB DB0 - DB7 CS1B CS2B CS3 15

DB0 ~ DB7 15

5 open V DD open open open open

V0

V1

V2

V3

V4

V5 V EE MPU

CS1B

64CH COMMON DRIVER FOR DOT MATRIX LCD

S1~S64 KS0108B

S1~S64

KS0107B
PAD DIAGRAM

64CH COMMON DRIVER FOR DOT MATRIX LCD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80 79 78 77 76 75 74 73 72

KS0107B

71 70 69 68

Y ( 0, 0 ) X

67 66 65 64 63 62

CHIP SIZE : 3450 4000 PAD SIZE : 100 100 UNIT : m

61 60 59 58 57 56 55 54

28

29

30

31

32

33

35

37

39

40

42

43

44

46

47

49

50

52

* There is mark of KS0107B on the center in chip

KS0107B

64CH COMMON DRIVER FOR DOT MATRIX LCD

PAD LOCATION
PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 PAD NAME C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2 C R COORDINATE X -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -979.6 -827.6 -677.6 -527.6 -377.6 Y 1775.4 1630 1505 1380 1255 1130 1005 880 775 630 505 380 255 130 5 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 -1775 -1775 -1775 PAD NUMBER 37 39 40 42 43 44 46 47 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PAD NAME CR SHL VSS MS CLK2 CLK1 FRM M PCLK2 DIO2 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 COORDINATE X -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 Y -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 5 130 255 380 505 630 755 880 1005 1130 1255

UNIT (m)
PAD NUMBER 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD NAME C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 COORDINATE X 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 Y 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4