VHDL

1. In VHDL, a port is A. a type of entity B. a type of architecture C. an input or output D. a type of variable

2. A VHDL component A. can be used once in each program B. is a predefined description of a logic function C. can be used in multiple times in a program D. is part of a data flow description E. answers (B) and (C) 3. A component is called for use in a program by using a A. signal B. variable C. component instantiation D. architecture declaration

4. Which of the following is the most accurate statement about VHDL entities and architectures? A. A component can have many entity declarations and many architectures. B. A component can have many entity declarations but only one architecture. C. A component can have only one entity declaration and many alternative architectures. D. A component can have only one entity declaration and only one architecture.

5. With reference to the VHDL behavioral model code segment below, which of the following statements is most accurate? ARCHITECTURE test_behav OF test IS VARIABLE x : BIT := 1 ; BEGIN PROCESS ( in_sig, y)

SIGNAL y : BIT := 0; BEGIN X := in_sig XOR y; Y <= in_sig XOR x ; END PROCESS; END test_behav; A. B. C. D. A variable (x) is incorrectly declared in the process declaration section A signal (y) is incorrectly defined in the architecture declaration section Both the Variable and Signal declarations are incorrect. The code segment is error free

6. A VHDL Model which uses abstract constructs (such as If-Then-Else) most likely represents which of the following styles of VHDL model? A. Behavioral Specification B. Data Flow Specification C. Structural Specification

7. Which style of VHDL Model is most appropriate for use during the early stages of a design? A. Structural model (because components can be easily added and removed) B. Data Flow (RTL) model (because logic equations can be easily manipulated for design modifications) C. Behavioral model (because it is implementation independent) D. Mixture of all three methods (because the appropriate level of abstraction can be chosen which is best suited for our design)

8. The following fragment of code illustrates the use of what VHDL

construct? IF clockevent AND clock = 1 THEN output <= input +1 END IF; A. attributes

B. clocks C. comments D. identifiers

9. Which of the following statements most accurately identifies any

errors in the VHDL Code fragment below? ENTITY test is PORT (a, b: IN BIT; y, z: OUT BIT; clock: INOUT BIT); END test; ARCHITECTURE example OF test IS BEGIN a <= y AND z AND clock; b <= y NOR z AND clock; clock <= NOT clock; END example; A. B. C. D. Signals y and z are incorrectly used as inputs within the architecture Signals a and b are incorrectly assigned values within the architecture Both (a) and (b) Code is error free.

10. Which of the following statements are true?

A. B. C. D.

All VHDL processes execute concurrently Concurrent signal assignment statements are one-line processes Statements in a process execute sequentially All of the above

11. Which of the following is not a VHDL data object

A. signal B. variable C. wire

D. constant
12. A VHDL Model that exclusively uses concurrent signal assignment

statements to describe the functionality of the design most likely represents which of the following styles of VHDL model? A. Behavioral Specification B. Data Flow Specification C. Structural Specification
13. Designing a combinational circuit requires state minimization. TRUE / FALSE 14. Designing a combinational circuit requires the use of a flip-flop or memory element. TRUE / FALSE 15. Designing a sequential circuit requires the use of a feedback path. TRUE / FALSE