Introduction to VLSI

Chapter 1 Digital Systems and VLSI

Table of Contents
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Why VLSI? Integrated circuit manufacturing CMOS technology Integrated circuit design techniques Circuit and system representations A Look into the Future

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Why VLSI?
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Integration improves the design:

Lower Parasitics = higher speed; Lower power; Physically smaller.

Integration reduces manufacturing cost(almost) no manual assembly.

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VLSI and You

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Microprocessors:
Personal computers; Microcontrollers

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DRAM/SRAM. Special-purpose processors.

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Integrated Circuit Manufacturing

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IC Design Technology

Schematic

Stick diagram

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Moores Law
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Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

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Moores Law

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Moores Law and Intel Microprocessors

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The Cost of Fabrication

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Current cost: about $1 billion. Typical fab. line occupies about 1 city block, employs a few hundred people. Most profitable period is first 18 months-2 years. Currently > 15 new fab. lines coming on line worldwide.

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Cost Factors in ICs

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For large-volume ICs:

Packaging is largest cost; Testing is second-largest cost.

For low-volume ICs, design costs may swamp all manufacturing costs.

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Bopolar, nMOS and CMOS Inverter

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The VLSI Design Process

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May be part of larger product design. Major steps:

Specification; Architecture; Logic design; Circuit design; Layout.

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Hierarchy of Design abstractions for ICs

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The Steps
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Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics.

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The Step 1: Logic, Function

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The Step 2: Schematic

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The Step 3: Stick Diagram

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The Step 4: Layout

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Design Validation
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Must check at every step that errors havent been introduced-the longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of lessand more-abstract stages. Back annotation: copy performance numbers to earlier stages.

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Manufacturing Test
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Not the same as design validation: just because the design is right does not mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade.

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Circuit and System Representations

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Behavioral representation Structural representation Physical representation

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Digital Design Domains & Levels of Abstraction

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Topics
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Combinational logic functions Static complementary logic gate structures

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Combinational Logic Expressions

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Combinational logic: function value is a combination of function arguments. A logic gate implements a particular logic function. Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

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Gate Design
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Why designing gates for logic functions is nontrivial:

May not have logic gates in the library for all logic expressions; A logic expression may map into gates that consume a lot of area, delay, or power.

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Completeness
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A set of functions f1, f2, ... is complete if every Boolean function can be generated by a combination of the functions. NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. complete Transmission gates are not complete. complete If your set of logic gates is not complete, you can design arbitrary logic. t
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Static Complementary Gates

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Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. Static: do not rely on stored charge. Simple, effective, reliable; Hence ubiquitous.

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Static Complementary Gate Structure

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Pullup and pulldown networks:

VDD

pullup network inputs pulldown network

VSS

out

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Pullup/pulldown Network Design

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Pullup and pulldown networks are duals. To design one gate, first design one network, then compute dual to get other network. Example: design network which pulls down when output should be 0, then find dual to get pullup network.

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Dual Network Construction

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CMOS Logic Inverter

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The Inverter

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CMOS Logic NAND Gate

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CMOS Logic NAND Gate

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CMOS Logic NAND Gate

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CMOS Logic NAND Gate

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CMOS Logic Compound

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CMOS Logic NOR Gate

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CMOS Logic NOR Gate

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CMOS Logic NOR Gate

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CMOS Logic NOR Gate

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CMOS Logic Compound

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CMOS Logic Compound

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CMOS Logic Compound

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Complex Logic Gates

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Example:

Z = A+ B + C D

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CMOS Logic Multiplexers

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AOI/OAI Gates
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AOI = and/or/invert; OAI = or/and/invert. Implement larger functions. Pullup and pulldown networks are compact: smaller area, higher speed than area NAND/NOR network equivalents. AOI312: AND 3 inputs, AND 1 input AOI312 inputs (dummy), AND 2 inputs; OR together these inputs terms; Then invert. invert
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AOI Example
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AOI21
out = a b + c
invert

symbol
or

circuit

and

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CMOS XNOR Gates

A B = A B + A B = A B + A B = A B A B = A B (A + B)

OAI21
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