Professional Documents
Culture Documents
Jaeger/Blalock 10/15/03
McGraw-Hill
Chapter Goals
Introduce CMOS logic concepts Explore the voltage transfer characteristics CMOS inverters Learn to design basic and complex logic gates Discuss static and dynamic power in CMOS logic Present expressions for dynamic performance of CMOS logic devices Present noise margins for CMOS logic Introduce dynamic logic and domino CMOS logic techniques Introduce design techniques for cascade buffers Explore layout of CMOS logic gates Discuss the concept of latchup
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
CMOS Inverter
(a) Circuit schematic for a CMOS inverter (b) Simplified operation model with a high input applied (c) Simplified operation model with a low input applied
Jaeger/Blalock 10/15/03 McGraw-Hill
McGraw-Hill
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
P LH = RON p C ln 4
VDD + VT P VH
2VT P V H + VT P
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
McGraw-Hill
Power-Delay Product
The power-delay product is given as:
Jaeger/Blalock 10/15/03
McGraw-Hill
Reference Inverter
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Reference Inverter
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
P7.58
Jaeger/Blalock 10/15/03
McGraw-Hill
P7.59
Jaeger/Blalock 10/15/03
McGraw-Hill
P7.46
Jaeger/Blalock 10/15/03
McGraw-Hill
P.7.63
Design a CMOS logic gate that implements the following function Y=(ABC+DE) Based on the CMOS reference inverter. Select transistor sizes to obtain the same delay.
Jaeger/Blalock 10/15/03
McGraw-Hill
P.7.64
Design CMOS L.G. to implement
Y=[A(B+C(D+E))] Select sizes to obtain same delay as reference inverter.
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Practice Problems
Chapter 7 probs. 8, 9, 11, 14, 15, 16, 17, 23, 28, 35, 57 to 69, 75, 77, 79, 81 to 84
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Cascade Buffers
- Sometimes large capacitances (CL~50pF) must be driven - use even numbers of inverters to drive load
Jaeger/Blalock 10/15/03
McGraw-Hill
Cascade Buffers
The taper factor determines the increase of the cascaded inverters size in manner shown of the previous image.
where Co is the unit inverters load capacitance The delay of the cascaded buffer is given by the following: o is the unit
inverters propagation delay
Jaeger/Blalock 10/15/03 McGraw-Hill
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
Example 7.4
Design a cascade buffer to drive a load cap of 50pF if C0=50 fF. Find overall delay for a 3.3-V supply with VTN= 0.75V and VTP= -0.75V
Jaeger/Blalock 10/15/03
McGraw-Hill
McGraw-Hill
Jaeger/Blalock 10/15/03
McGraw-Hill
CMOS Latchup
There is one major downfall to the CMOS logic gate Latchup There are many safeguards that are done during fabrication to suppress this, but it can still occur under certain transient or fault conditions
Jaeger/Blalock 10/15/03
McGraw-Hill
CMOS Latchup
Latchup occurs due parasitic bipolar transistors that exist in the basic inverter as shown below
Jaeger/Blalock 10/15/03
McGraw-Hill
CMOS Latchup
The configuration of these bipolar transistors create a positive feedback loop, and will cause the logic gate to latchup as shown to the left By using heavily doped material where Rn and Rp exist, there resistance will be lowered thereby reducing the chance of latchup occurring
Jaeger/Blalock 10/15/03 McGraw-Hill
End of Chapter 7
Jaeger/Blalock 10/15/03
McGraw-Hill