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Richard C. Jaeger Travis N. Blalock

Jaeger/Blalock 10/15/03

McGraw-Hill

Chapter Goals

Introduce CMOS logic concepts Explore the voltage transfer characteristics CMOS inverters Learn to design basic and complex logic gates Discuss static and dynamic power in CMOS logic Present expressions for dynamic performance of CMOS logic devices Present noise margins for CMOS logic Introduce dynamic logic and domino CMOS logic techniques Introduce design techniques for cascade buffers Explore layout of CMOS logic gates Discuss the concept of latchup

McGraw-Hill

Jaeger/Blalock 10/15/03

Complementary MOS, or CMOS, needs both PMOS and NMOS devices for their logic gates to be realized The concept of CMOS was introduced in 1963 by Wanlass and Sah, but it did not become common until the 1980s as NMOS microprocessors were dissipating as much as 50 W and alternative design technique was needed CMOS still dominates digital IC design today

Jaeger/Blalock 10/15/03

McGraw-Hill

The CMOS inverter consists of a PMOS stacked on top on a NMOS, but they need to be fabricated on the same wafer To accomplish this, the technique of n-well implantation is needed as shown in the figure which shows the crosssection of a CMOS inverter

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS Inverter

(a) Circuit schematic for a CMOS inverter (b) Simplified operation model with a high input applied (c) Simplified operation model with a low input applied

Jaeger/Blalock 10/15/03 McGraw-Hill

When vI is pulled high (VDD), the PMOS inverter is turned off, while the NMOS is turned on pulling the output down to VSS When vI is pulled low (VSS), the NMOS inverter is turned off, while the PMOS is turned on pulling the output up to VDD

Jaeger/Blalock 10/15/03

McGraw-Hill

Two methods of laying out a CMOS inverter are shown The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the psubstrate Polysilicon is used to form common gate connections, and metal is used to tie the two drains together

Jaeger/Blalock 10/15/03

McGraw-Hill

The figure shows the two modes of static operation with the circuit and simplified models Notice that VH = 5V and VL = 0V, and that ID = 0A which means that there is no static power dissipation

Jaeger/Blalock 10/15/03 McGraw-Hill

The VTC shown is for a CMOS inverte r that is symmetrical (KP = KN) Region 1: vO = VH vI < VTN Region 2: |vDS| |vGS VTP| Region 4: vDS vGS VTN Region 5: vO = VL vI > VDD |VTP|

Jaeger/Blalock 10/15/03

McGraw-Hill

Simulation result shows the varying VTC of the inverter as VDD is changed. Minimum voltage supply: 2VTln(2)

Jaeger/Blalock 10/15/03

McGraw-Hill

The simulation result shows the varying VTC of the inverter as KN/KP = KR is changed For KR > 1 the NMOS current drive is greater and it forces vI < VDD/2 For KR < 1 the PMOS current drive is greater and it forces vI > VDD/2

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03 McGraw-Hill

P LH = RON p C ln 4

VDD + VT P VH

2VT P V H + VT P

Jaeger/Blalock 10/15/03 McGraw-Hill

The rise and fall times are given by the following expressions:

Jaeger/Blalock 10/15/03

McGraw-Hill

Design a reference inverter to achieve a delay of 250ps with a 0.1pF load given the following information:

Jaeger/Blalock 10/15/03

McGraw-Hill

Assuming the inverter is symmetrical and using the values given in Table 7.1:

Jaeger/Blalock 10/15/03

McGraw-Hill

Solving for RonN:

Jaeger/Blalock 10/15/03

McGraw-Hill

Ideal step used to derive previous delay equations, but this is not possible to implement Using the following circuit in SPICE, it is possible to deduct more accurate equations

Jaeger/Blalock 10/15/03

McGraw-Hill

The output of the previous circuit looks is shown below. Delay for the non-ideal step input ~ twice than the ideal case

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS logic: no static power dissipation DC current driving a capacitive load is zero This is not completely accurate since MOS transistors have leakage currents associated with the reverse-biased drain-to-substrate connections

Jaeger/Blalock 10/15/03

McGraw-Hill

Two components contribute to dynamic power dissipation: Capacitive load charging at a frequency f given by: PD = CVDDf Current flowing through both N- and PMOS that occurs during switching which can be seen in the figure Peak current occurs when vi = vout=VDD/2 for symmetrical design

Jaeger/Blalock 10/15/03

McGraw-Hill

Power-Delay Product

The power-delay product is given as:

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03 McGraw-Hill

Reference Inverter

Size transistors to keep delay times the same as the reference inverter.

the on-resistance on the PMOS branch of the NOR gate must be the same as the reference inverter For a two-input NOR gate, the (W/L)p must be made twice as large

Jaeger/Blalock 10/15/03

McGraw-Hill

Since the bottom PMOS body contact is not connected to its source, its threshold voltage changes as VSB changes during switching

Once vO = VH is reached, the bottom PMOS is not affected by body effect, thus the total on-resistance of the PMOS branch is the same However, the rise time is slowed down due to |VTP| being a function of time

Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

It is possible to extend this same design technique to create multiple input NOR gates

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03 McGraw-Hill

Reference Inverter

The same rules apply for sizing the NAND gate as the did for the NOR gate, except for now the NMOS transistors are in series The (W/L)N will be twice the size of the reference inverters NMOS

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Design a CMOS logic gate for (W/L)p,ref=5/1 and for (W/L)n,ref=2/1 that exhibits the function: Y = A + BC +BD By inspection (knowing Y), the NMOS branch of the gate can drawn as the following with the corresponding graph, while considering the longest path for sizing purposes:

Jaeger/Blalock 10/15/03

McGraw-Hill

By placing nodes in the interior of each arc, plus two more outside the graph for VDD (3) and the complementary output (2), the PMOS branch can be realized as shown on the left figure Connect all of the nodes in the manner shown in the right figure, and the NMOS arc that PMOS arc intersects have the same inputs

Jaeger/Blalock 10/15/03

McGraw-Hill

From the PMOS graph, the PMOS branch can now be drawn for the final CMOS logic gate while once again considering the longest PMOS path for sizing

Jaeger/Blalock 10/15/03

McGraw-Hill

Design a CMOS gate that implements the following logic function using the same reference inverter sizes as the previous example: Y = AB +CE + ADE + CDB The NMOS branch can be realized in the following manner using bridging NMOS D to implement Y. The corresponding NMOS graph is shown to the right.

Jaeger/Blalock 10/15/03

McGraw-Hill

By using the same technique as before, the PMOS graph can now be drawn

Jaeger/Blalock 10/15/03

McGraw-Hill

By using the PMOS graph the PMOS branch can now be realized as the one shown on the left. The longest path was used to select sizing.

Jaeger/Blalock 10/15/03

McGraw-Hill

P7.58

Jaeger/Blalock 10/15/03

McGraw-Hill

P7.59

Jaeger/Blalock 10/15/03

McGraw-Hill

P7.46

Jaeger/Blalock 10/15/03

McGraw-Hill

P.7.63

Design a CMOS logic gate that implements the following function Y=(ABC+DE) Based on the CMOS reference inverter. Select transistor sizes to obtain the same delay.

Jaeger/Blalock 10/15/03

McGraw-Hill

P.7.64

Design CMOS L.G. to implement

Y=[A(B+C(D+E))] Select sizes to obtain same delay as reference inverter.

Jaeger/Blalock 10/15/03

McGraw-Hill

With CMOS technology, there is a area/delay tradeoff that needs to be considered If minimum feature sized are used for both devices, then the PLH will be decreased compared to the symmetrical reference inverter

Jaeger/Blalock 10/15/03

McGraw-Hill

The following shows the layout of a complex minimum size logic gate

Jaeger/Blalock 10/15/03

McGraw-Hill

Practice Problems

Chapter 7 probs. 8, 9, 11, 14, 15, 16, 17, 23, 28, 35, 57 to 69, 75, 77, 79, 81 to 84

Jaeger/Blalock 10/15/03

McGraw-Hill

technique to help decrease power in MOS logic circuits is dynamic logic uses pre-charge and evaluation phases that are controlled by a system clock to eliminate the dc current path in single channel logic circuits Early MOS logic required multiphase clocks to accomplish this, but CMOS logic can be operated dynamically with a single clock

Jaeger/Blalock 10/15/03

McGraw-Hill

The figure demonstrates the basic concept of domino CMOS logic operation

Jaeger/Blalock 10/15/03

McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Domino CMOS circuits only produce true logic outputs To overcome this problem use with registers that have both true and complemented output to complete the function

Jaeger/Blalock 10/15/03

McGraw-Hill

P7.75 (a) draw a diagram of a dynamic domino CMOS logic OR gate (b) same for AND P7.82 Draw a dynamic domino CMOS logic circuit that implements Z=AB+CD

Jaeger/Blalock 10/15/03

McGraw-Hill

Cascade Buffers

- Sometimes large capacitances (CL~50pF) must be driven - use even numbers of inverters to drive load

Jaeger/Blalock 10/15/03

McGraw-Hill

Cascade Buffers

The taper factor determines the increase of the cascaded inverters size in manner shown of the previous image.

where Co is the unit inverters load capacitance The delay of the cascaded buffer is given by the following: o is the unit

inverters propagation delay

Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock 10/15/03

McGraw-Hill

Optimum cascaded buffer But: you MUST use integer N - below or above NOPT (NI) that gives lower

Jaeger/Blalock 10/15/03

McGraw-Hill

Example 7.4

Design a cascade buffer to drive a load cap of 50pF if C0=50 fF. Find overall delay for a 3.3-V supply with VTN= 0.75V and VTP= -0.75V

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS transmission gate (T-gate): useful circuits for both analog and digital applications Acts as a switch that can operate up to VDD and down to VSS

Jaeger/Blalock 10/15/03

McGraw-Hill

Needs to consider the equivalent on-resistance which is given by the following expression:

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS Latchup

There is one major downfall to the CMOS logic gate Latchup There are many safeguards that are done during fabrication to suppress this, but it can still occur under certain transient or fault conditions

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS Latchup

Latchup occurs due parasitic bipolar transistors that exist in the basic inverter as shown below

Jaeger/Blalock 10/15/03

McGraw-Hill

CMOS Latchup

The configuration of these bipolar transistors create a positive feedback loop, and will cause the logic gate to latchup as shown to the left By using heavily doped material where Rn and Rp exist, there resistance will be lowered thereby reducing the chance of latchup occurring

Jaeger/Blalock 10/15/03 McGraw-Hill

End of Chapter 7

Jaeger/Blalock 10/15/03

McGraw-Hill

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