The T1/E1 Interface, Tutorial

The E1 and the T1 interfaces are two different, independent standardized TDM technologies. These technologies enable transmission of several (multiplexed) voice/data channels simultaneously on the same transmission facility. The E1 standard is mostly deployed in Europe and the T1 standard is mostly deployed in America and Asia. E1/T1 lines mostly connect between PABXs and COs. E1 and T1 belong to the physical layer in the OSI reference model, thus layer 2 technologies such as ATM and FR are carried over it.

Clk Data Data Clk PBX PBX

Figure 1: T1/E1 Network Diagram

Time Division Multiplexing

Clearly there is a need to transfer much more than a single channel between two sites. However, stretching a separate line for every channel is clearly not a good solution. Multiplexing is a way of sending several channels over a single line. One way of doing it is by using TDM - Time Division Multiplexing. Suppose we have 32 channels, each with a rate of 64Kbs, that we wish to transfer to the other end. The multiplexer takes from each of the 32 lines a single byte and sends them one after the other. After doing so, it takes the next byte from every channel, and so on. The multiplexer must be able to send all the 32*8 bits from

the 32 channels without the second byte of the first channel getting lost. This implies that the output rate of the multiplexer should be at least 32*64Kbs or 2048 Kbs. This method is called Time Division Multiplexing (TDM) because the multiplexer took the 1/8000 sec needed for transferring a single byte of a single channel, and divided it between the 32 channels by increasing the rate so that each byte of a channel will take 1/(8000 * 32) sec to send.

Mux
Byte A2 Byte A1

Byte B2

Byte B1

A1

B1

C1

A2

Byte C2

Byte C1

Figure 2: Time Division Multiplexing

Clocks
Clock synchronization is a major issue for TDM links. Figure 1 shows a basic diagram for E1 or T1 link were each PBX is master for its own clock. Another method, called loop timing, creates one clock domain for the whole network. This method is preferred and recommended. Please contact system_design@hardware-guru.com for more details.

E1 Interface
The E1 interface provides a 2048 kbit/s access rate. It can support up to 32 user channels, each of 64 kbit/s access rate, though mostly only 30 are used as

dedicated user channels. The 64 kbit/s channels are usually used for delivering PCM encoded phone calls, but of course can carry pure data. An E1 line connects two points in one of which the information is multiplexed and in the second demultiplexed. In order to provide a reliable and accurate service the E1 interface supports several mechanisms for synchronization, error correction and detection, management and performance messages and signaling. These mechanisms and their way of operation will be explained in the following sections. The E1 interface supports 3 different kinds of bit structures : Frame, Multiframe, and Unframed. The mode of operation dictates how the bits are structured and as consequent the way it will be interpreted. The Frame Structure As a consequence of the TDM methodology, each of the E1s channels is practically carried in one time slot of the 32 time slots the E1s bandwidth is divided to. The concatenation of 32 consecutive time slots is named an E1 frame. The E1 frame length is 256 bits (32 TS * 8 bit each TS). The Frame rate is 8kHz. The time slots in each frame are numbered 0 to 31: 1. TS0 is dedicated for synchronization, alarms and messages (future use), unless configured differently. 2. TS16 is usually used for signaling, but can carry data as well. 3. TS1-TS15 and TS17-TS31 are used for carrying user data. The structure of an E1 frame is demonstrated below:
TS0 TS1
CH1

TS2
CH2

TS16

TS29
CH28

TS30
CH29

TS31
CH30

Figure 3: E1 Frame Structure Si bit reserved for international use. A Remote alarm indication.

Sa4 Sa8 Additional spare bits. See the section 3.5. The MultiFrame Structure 16 consecutive frames form a new structure called a Multiframe. The frames in a Multiframe are considered numbered 0 to 15. Multiframe structure is used for two purposes CAS signaling and CRC. Each of these modes is independent from the use of the other. CAS is carried in TS16 (as will be explained later) and CRC is carried in TS0. Within Seabridge the convention is to use the name Multiframe for the CAS mode only. CRC functionality is considered as added functionality to the Framed structure. The Synchronization Mechanism In order to verify that the received bits are mapped to the correct channels, a synchronization mechanism is activated. To not be confuse this mechanism is independent of any clock, and does not synchronize the clocks. Clock recovery is achieved by the shape of the signal. The synchronization information is carried in TS0 of any second frame. Such a frame is called FAS. This is demonstrated in the structure of an E1 frame. A FAS carries the unique pattern 0011011 (bits 1 7), that specifies the alignment of the frame. It is important to mention that even when the channel is not allocated the channel is not idle physically but keeps carrying an idle signal. Thus, since broadcasting over the line is continuo alignment sync errors occur very rarely. The Error Correcting Code Mechanism This mechanism is operated using a cyclic redundancy check (CRC 4). When this mechanism is activated, the Si bit in every FAS, carries the results of the computation. This computation is done twice in each Multiframe, One computation for each Sub Multiframe (SMF).

Sub-multiframe (SMF)

Frame number
0 1 2

3 4 5 6

Multiframe

7 8 9 10

II

11 12 13 14 15

Bits 1 to 8 of the frame 1 2 3 4 1 C1 0 0 Sa4 0 1 A 1 C2 0 0 Sa4 0 1 A 1 C3 0 0 Sa4 1 1 A 1 C4 0 0 Sa4 0 1 A 1 C1 0 0 Sa4 1 1 A 1 C2 0 0 Sa4 1 1 A 1 C3 0 0 Sa4 E 1 A 1 C4 0 0 Sa4 E 1 A

5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5

6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6

7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7

8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8

NOTES 1 2 3 4

E = CRC-4 error indication bits . Sa4 to Sa8 = Spare bits. C1 to C4 = Cyclic Redundancy Check-4 (CRC-4) bits. A = Remote alarm indication .

Table 1: TS0 Structure

The Signaling Mechanism Signaling mechanisms provide a wide range of functions and their protocol is application specific. Two modes of signaling are optional: CCS Common Channel Signaling. In this mode of operation one or more channels of 64 kbit/s are dedicated for signaling and the information carried in them asynchronously serves for all other channels. TS16 is usually used for this purpose. CAS Channel Associated Signaling. In each Multiframe, each channel has a predetermined frame (see Table 14/G.704). In this frame half of TS16 is dedicated for this channel signaling information. The use of TS16 in each specific frame is shown in the following diagram:

Time slot 16 of frame 0 0000xyxx

Time slot 16 of frame 1 abcd channel 1 abcd channel 16

Time slot 16 of frame 2 abcd channel 2 abcd channel 17

Time slot 16 of frame 15 abcd channel 15 abcd channel 30

NOTES 1 Channel numbers refer to telephone channel numbers. 64 kbit/s channel time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered from 1 to 30. 2 This bit allocation provides four 500-bit/s signaling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signaling distortion of each signaling channel introduced by the PCM transmission system, will not exceed 2 ms. 3 When bits b, c or d are not used they should have the values: b = 1, c = 0, d = 1. It is recommended that the combination 0000 of bits a, b, c and d should not be used for signaling purposes for channels 1 to 15. 4 x = Spare bit, to be set to 1 if not used. y = Bit used for alarm indication to the remote end. In undisturbed operation, set to 0; in an alarm condition, set to 1.

Table 2: TS16 Structure As can be seen in the diagram above, each channel has 4 bits (abcd) with which it can transfer and signal other parties about its state. 4 bits can represent up to 16 states but not always all are in use. The number of bits that are in use dictates the CAS method which is in use: A signaling using only one bit. Can represent 2 states: Hook on/off. A, B signaling using only two bits. Can represent 4 states. A, B, C, D signaling using all four bits. Can represent in fact only 15 states because 4 consecutive zeros are not allowed. In the past the CAS bits were used for transferring the number dialed. This method resulted in a very slow connection establishment. Today DTMF (Dual Tone Multi Frequency) is mostly in use. In DTMF the information about the number dialed is carried inband, that is, it carried using the users TS. No conflict is made with the users data because the frequencies used

for this signaling are higher than human speech frequencies. Fault Conditions and Consequent Actions The consequent action for a fault condition can be dependent on the scope in which this fault condition occurred (Multiplex/ Demultiplex equipment, FR over E1 etc.). Below are the definitions of the conditions that are considered fault followed by t e list of possible h consequent actions. The equipment is responsible for these conditions detection and actions to be taken. Fault Conditions 1. 2. 3. 4. 5. 6. 7. Failure of power supplies. Failure of codex. Loss of incoming signal at the 64Kbit/s input port. Loss of incoming signal at 2048Kbit/s. Loss of frame alignment. Excessive bit error ratio detected by monitoring the frame alignment signal. Alarm indication received from the remote PCM multiplex equipment.

Consequent Actions 1. Service Alarm Indication. Signifies that the service provided by the PCM multiplex is no longer available. 2. Maintenance Alarm Indication. Signifies that the performance is below acceptable standards, and maintenance attention is required locally. 3. Alarm indication to the remote end. Transmitted by changing bit 3 of channel TS-0 from 0 to 1. 4. Transmission suppressed at the analogue outputs. 5. AIS applied to TS-16. 6. AIS applied to all TSs. Modes of Operation When using the E1 interfaces several modes of operation are available. These modes are listed below: Unframed (UNF): A stream of bits at 2048 Kbs. No channels are associated to

any specific group of bits. None of the mechanism described above is used. Framed (FR): All 32 slots are used to transfer data, detection of the frame boundaries (synchronization) is achieved using TS0. Multiframe (MF): TS0 is used for the synchronization of the Multiframes. All other channels are unaffected. MF: Same as MF + One channel that is dedicated for signaling - CAS. MF + CRC: Using the Si bits of each FAS to deliver the CRC 4 MF + CAS/CCS +CRC

General Characteristics The digital interface signal has a nominal rate of 2048 kbit/s. Line code is AMI or HDB3 The 2048 kbit/s interface specification is defined in Table 3.

Pulse shape (nominally rectangular) Pair(s) in each direction Test load impedance Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative pulses at the centre of the pulse interval Ratio of the widths of positive and negative pulses at the nominal half amplitude Maximum peak-to-peak jitter at an output port

All marks of a valid signal must conform with the mask irrespective of the sign. The value V corresponds to the nominal peak value. One coaxial pair 75 ohms resistive 2.37 V 0 0.237 V 244 ns 0.95 to 1.05 0.95 to 1.05 Refer to clause 2/G.823 One symmetrical pair 120 ohms resistive 3V 0 0.3 V

Table 3: Digital Interface at 2048 kbit/s

T1 Interface

The T1 interface provides a 1544 kbit/s access rate. It can support up to 24 user channels, each of 64 kbit/s access rate. It is very similar to the E1 interface in its functionality but very different from the E1 in its implementation and its physical characteristics. The T1 interface supports 4 different bit structures, dictated by the mode of operation: Frame, Super Frame, Extended Super Frame, and Unframed. These bit structures like in E1 determine how the bits are interpreted. The Frame Structure A T1 frame is constructed of 24 time slots plus 1 framing bit added to them. Each TS is regarded as a channel of 64 kbit/s bandwidth. Frame length is 193 bits (24*8 + 1), and the frame rate is 8 kHz. The Framing bit creates a channel of 8kbit/s and is used for messages, synchronization, and alarms. The Frame is the basic building block for the SF and the ESF. The Super Frame (SF) Structure A Superframe is structure constructed of 12 Frames, Numbered: 1 12. Two mechanisms can be activated when using SFs: synchronization mechanism, which is always activated, and signaling mechanism, which is optional.

The Synchronization Mechanism The 12 framing bits, which are the leading bits of each frame, form a unique pattern. With this pattern synchronization is achieved and verified. The Framing bits that form this pattern are divided into two categories: 1. Terminal framing bits (Ft) - used to identify the frame boundaries. 2. Signaling framing bits (Fs) used to identify the SF boundaries. Within this pattern there are two sub-patterns, with th which every 6 and 12th frame are recognized. These

frames are used to carry Channel Associated Signaling (CAS) bits (A, B), when this mode of operation is in use.

F-bit Assignments Bit number(s) in each channel time slot

Frame number within multiframe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FAS DL CRC

a)

Bit number within multiframe 1 194 387 580 773 966 1159 1352 1545 1738 1931 2124 2317 2510 2703 2896 3089 3282 3475 3668 3861 4054 4247 4440

FAS 0 0 1 0 1 1

DL m m m m m m m m m m m m

CRC e1 e2 e3 e4 e5 e6

For character signal a) 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7

For signallinga) 8 8 8 8

Signalling channel designationa)

Frame alignment signal (. . . 001011 . . .). 4 kbit/s data link (message bits m). CRC-6 block check field (check bits e 1 to e6). Only applicable in the case of channel associated signalling (see 3.1.3.2).

Table 4: Multiframe Structure for the 24 Frame Multiframe

Below is a diagram that illustrates the structure of a SF:

Frame Number 1 2 3 4 5 6 7 8 9 10 11 12

FT 1 0 1 0 1 0 -

FS 0 0 1 1 1 0

Information bits 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7

Signaling bit

Signaling channel

Table 5: Superframe Structure The Signaling Mechanism As mentioned in the last paragraph, if CAS is in use, every 6th frame contains one robbed bit in each byte of information (channel). This robbed bit carries the information of this specific channel. By robbed bit we mean that the last bit of each TS is robbed for the purpose of signaling. These robbed bits forms a channel with capacity of 10.666 kbit/s. When delivering voice this robbed bit does not affect the quality the conversation. But when delivering data it does affect it, forcing the use of only 7 out of 8 bits in each channel in all the frames, resulting in channel of only 56 kbit/s.

If CCS is in use, then one TS, usually TS24, is dedicated for this purpose. In this case it becomes very similar to E1 CCS. The Extended Super Frame (ESF) Structure Also known as D5 frame or Fe. Each extended superframe consists of 24 frames. The ESF knows 3 different framing types: 1. Synchronization: bit sequence 001011 in frames 4, 8, 12, 16, 20, 24 2. Data Link: frames 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23 3. CRC-6: frames 2, 6, 10, 14, 18, 22 One of 8 bits of each DS-0 channel is robbed for signaling in 6th, 12th, 18th, and 24th frame. This is also called A/B/C/D signaling. The options define up to 16 features. 6 out of 24 S-bits are used for synchronization. They are called Fe bits. The remaining bits are used for a 4 kbps data link and an ESF block check as shown in the table below.

Frame Number

S-bits

Bit use in each Signaling-bit channel time slot Use options

Fe DL CRC Traffic Signaling T 2 4 16 1 2 3 4 5 6 7 8 9 10 11 12 - m C1 C2 C3 1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 8 - A B B 8 - A A A

- m 0 - m -

- m 0 - m -

- m 1 -

13 14 15 16 17 18 19 20 21 22 23 24

- m -

C4 C5 C6 -

1-8 1-8 1-8 1-8 1-8 1-7 1-8 1-8 1-8 1-8 1-8 1-7 8 - A B D 8 - A A C

- m 0 - m -

- m 1 - m -

- m 1 -

Table 6: Extended Superframe Structure

The Synchronization Mechanism As technology developed, fewer bits were necessary in order to achieve synchronization of the bit and the 8 bit words they construct. These unused bits could now serve for the error correcting code mechanism and the FDL mechanism. Thus, synchronization when working with ESF is achieved by checking the 6 bits length pattern that is created from every 4th framing bit. The CRC6 Mechanisms This mechanism provides the ability to monitor the transmission quality of the DS1 facility. The CRC 6 will detect 100% of all errors of less than 6 bits and 98.4% of the errors of more than 6 bits. This mechanism will also protect from a mistake in the synchronization of the frame, which can occur if taking an identical pattern to the synchronization pattern that is not the right one. This mechanism uses every 4th bit of the framing bits in the ESF, beginning at the second one. The CRC6 delivered in the Nth ESF was

computed based on the N-1st ESF taking all its framing bits as ones. The Signaling Mechanism This mechanism is very similar to the signaling mechanism of the SF, described above, except from the fact that it can be used for ABCD signaling using four different bits. The FDL mechanism This mechanism operates using every second framing bit, beginning at the first frame of the ESF. These bits create a 4000 bps data link called the Facility Data Link. This channel is used for delivering maintenance information, supervisory control, and other future needs. Two kinds of messages are carried on the FDL channel, each using a different format: Scheduled messages This message is transmitted once per second. These messages carry information indicating on the quality of the transmission, CRC errors, frame Sync error, severely error framing, line code violation, and controlled. These messages are transmitted in LAP D Format. Unscheduled messages These messages can interrupt any Scheduled message, as their codewords start with the 11111111 prefix, which is the abort signal in the LAP D protocol. These messages are also divided into two categories: Priority messages These messages indicate that some condition that is service effecting, exist. These messages are transmitted in continuo repetition, for at least one second of duration. This category contains the Yellow

alarm (RAI), and the loopback retention messages. Command & Response messages These messages are used to initiate actions in various pieces of the equipment. They are transmitted in 10 repetitions of the appropriate codeword. A continues signal of repeated 01111110, is the IDLE signal. A continues signal of ones, 11111111, is the AIS signal, which represent loss of signal between the source and the sink.

Modes of Operation When using the T1 interfaces several modes of operation are available. These modes are listed below: 1. Unframed (UNF): A stream of bits at 1544 Kbs. No channels are associated to any specific group of bits. None of the mechanism described above is used. 2. Superframe (SF): Data transferred using the SF format. 3. SF + CAS: The CAS is carried over the robbed bits of each 6th and 12th frame detected by the SF format. 4. ESF 5. ESF + CAS 6. ESF + FDL 7. ESF + CAS/CRC/FDL 8. CCS: Can be used in each of the framed formats, by dedicating one channel (usually TS24) for delivering the signaling messages, in a predetermined protocol.

General Characteristics The digital interface signal has a nominal rate of 1544 kbit/s. The 1544 kbit/s interface specification is defined in the following table..

Parameter Nominal line rate Line rate accuracy Line code 1544 kbit/s

Specification In a self-timed, free running mode, the line rate accuracy shall be 50 bits/s (32 ppm) or better. Either (1) AMI with no more than 15 consecutive zeros, and at least N ones in each and every time window of 8(N + 1) digit time slots (where N can range from 1 to 23), or (2) B8ZS (Note 1). No frame structure is required for 1544 kbit/s transmission or higher level multiplexing to higher level DSN signals. One balanced twisted pair shall be used for each direction of transmission. A resistive test load of 100 ohms 5% shall be used at the interface for the evaluation of pulse shape and the electrical parameters specified below. The amplitude (Note 2) of an isolated pulse shall be between 2.4 V and 3.6 V. The shape of every pulse that approximates an isolated pulse (is preceded by four zeros and followed by one or more zeros) shall conform to the mask. For an all-one signal, the power in a 3 kHz 1 kHz band centered at 772 kHz shall be between 12.6 dBm and 17.9 dBm. The power in a 3 kHz 1 kHz band centered at 1544 kHz shall be at least 29 dB below that at 772 kHz. In any window of seventeen consecutive bits, the maximum variation in pulse amplitudes shall be less than 200 mV, and the maximum variation in pulse widths (half amplitude) shall be less than 20 ns. There shall be no DC power applied at the interface. Access to the signal at the interface shall be provided for verification of these signal specifications.

Frame structure Medium Test load impedance Pulse amplitude Pulse shape Power level

Pulse imbalance

DC power Verification access

NOTE 1 B8ZS is one method of providing bit sequence independence. Bit sequence independence in turn allows unconstrained clear channel capability. Zero Byte Time Slot Interchange (ZBTSI) is another method of providing clear channel transmission. NOTE 2 While both voltage and power requirements are given to assist in qualification of signals at the interface, the values are not equivalent. Voltage specifications are given for isolated pulses, while power levels are specified for all-ones signal.

Table 7: Digital Interface at 1544 kbit/s

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