M.SC. (TECH.) DSP & ESD QUESTION BANK FOR II MID EXAMINATION, 2009-2010.

PAPER: DS404 EMBEDDED SYSTEMS DESIGN 1. Which of the following is NOT a part of a typical embedded system? A. C. Processor Power supply D B. D. Memory Hard disk

Ans: 2.

Indicate the INCORRECT statement of the following: A. C. Standard outputs drive signals high or low Tristating is a low impedance state C B. D. Tristated outputs drive the signals high, low or float. Open collector outputs drive the signals low or float

Ans: 3.

A memory chip is labeled as 8X512 KB 60 ns then indicate the INCORRECT statement of the following A. C. It has 512 KB storage locations of 8 bits each Each memory location has a response time of 60 nanoseconds B B. D. It has 512 KB storage locations of 8 bytes each It has 524288 bytes of storage locations

Ans: 4.

Indicate the INCORRECT statement of the following: A. C. Masked ROMs are the cheapest type of permanent memory EEPROMS are the fastest type of memory suitable for storing programs and data permanently C B. D. Flash is useful to store programs as well as data permanently RAMs are very fast type of memory that best suitable for reading/writing temporarily

Ans: 5.

Indicate the INCORRECT statement regarding DMA A. C. DMA is a software code used for data transfer between memory and I/O DMA is a hardware circuitry used for data transfer between memory and I/O A B. D. DMA stands for Direct Memory Access DMA can either be level triggered or edge triggered

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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With IRQ signal from an external interrupt device microprocessor A. C. Temporarily stops current sequence of execution after completing the current instruction Resumes the interrupted execution after the completion of ISR D B. D. Executes corresponding Interrupt Service Routine Do (A), (B) and (C) of the above in sequence

Ans: 7.

The responsibilities of a typical Embedded systems software Engineer must include A. C. Should understand the hardware in order to write correct software Should be able to read the hardware schematic and suggest corrections D B. D. Must be able to install the software on the hardware All of the above

Ans: 8.

Indicate the INCORRECT statement of the following A. C. Microprocessor is a single chip microcomputer system (MCS) Microcontroller is a single chip microcomputer system (MCS) A B. D. Microprocessor is a single chip CPU Embedded system is any computer system hidden inside a product other than a computer

Ans: 9.

A typical microcontroller consists of (select the most appropriate answer) A. C. CPU CPU, Memory and I/O subsystems D B. D. CPU and Memory CPU, Memory, I/O subsystems and counters/timers

Ans: 10.

Which of the following is NOT an 8-bit microcontroller? A. C. Intel 8051 Intel 8086 C B. D. Atmel 89C51 Microchip PIC16XX

Ans: 11.

Which of the following is NOT a feature of Intel 8051 microcontroller? A. C. 128 bytes of on-chip RAM and 4 KB of on-chip ROM 2 timer/counters and 5 interrupt sources B B. D. RISC architecture 1 serial port and 32 I/O pins

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Indicate the correct statement on I/O operations A. C. I/O device sets a hardware handshake line when it is ready to transfer data When CPU reads/writes data port the I/O handshake line is reset D B. D. CPU checks I/O device status by reading I/O handshake line (A), (B) and (C) of the above are correct

Ans: 13.

The I/O transfer technique which involves highest hardware complexity and lowest CPU overhead is A. C. Programmed I/O DMA C B. D. Interrupt driven I/O None of the above

Ans: 14.

An interrupt is generated when A. C. An I/O device finishes its operation and wants to inform the CPU of the completion An executing program performs an incorrect operation and raises an exception D B. D. An executing program needs some service from the OS Any of (A), (B) and (C) above

Ans: 15.

In an instruction execution cycle CPU checks for the interrupt when A. C. After execution of the current instruction Before executing the instruction A B. D. After fetching the instruction Never checks for the interrupt

Ans: 16.

Interrupt handling mechanism involves A. C. Asserting INTR and INTA signals Executing ISR D B. D. Saving and retrieving the context All of the above

Ans: 17.

The last instruction of every ISR must be A. C. RETURN POP A B. D. PUSH RST

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Divide error is A. C. Hardware interrupt Exception software interrupt C B. D. Normal software interrupt None of the above

Ans: 19.

Power-failure interrupt is: A. C. Maskable interrupt Periodic interrupt B B. D. Non-maskable interrupt Synchronous interrupt

Ans: 20.

The time taken by the system to respond to external interrupt is: A. C. Interrupt latency Interrupt sequence A B. D. Interrupt priority Interrupt context

Ans: 21.

Identify the simplest software architecture of the following A. C. Function-queue-scheduling Round-robin with interrupts D B. D. Real Time Operating Systems Round-robin

Ans: 22.

Identify the most complex software architecture of the following A. C. Function-queue-scheduling Round-robin B B. D. RTOS None of the above

Ans: 23.

Interrupts, shared data, priorities and deadlines are applicable to: A. C. RTOS Round-robin A B. D. Function-queue-scheduling Round-robin with interrupts

Ans: 24.

An Operating System is A. C. An organized collection of software extensions of hardware that control routines for operating a computer An environment for execution of programs D B. D. One that manages computer system resources (A), (B) and (C) of the above

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Which of the following features is NOT applicable to an embedded RTOS? A. C. Program Interface File system manipulation C B. D. I/O operations All of the above

Ans: 26.

In a multi-user operating system the term protection refers to A. C. The system is safe from weathering Access to the system resource is controlled C B. D. Users need a password to login Access is denied to external I/O devices

Ans: 27.

CPU executes OS kernel functions in A. C. User mode Supervisor mode C B. D. Normal mode Abnormal mode

Ans: 28.

The switch-over from kernel space to user space is done by means of A. C. A hardware interrupt A software trap C B. D. A Mutex A semaphore

Ans: 29.

The function of OS upper kernel is A. C. File System Scheduler Memory protection A B. D. User process interface Multiplexing of Physical HW

Ans: 30.

The most appropriate tool when considering Embedded System Software Development is A. C. Native Compiler Native Assembler B B. D. Cross-Compiler None of the above

Ans: 31.

Task scheduler in a multi-tasking OS A. C. Supports communication between different tasks Block running tasks D B. D. Performs necessary bookkeeping to start a task Determines which task will run next

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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A real time system is characterized by A. C. A fair access to all the resources Processing speed as a major concern D B. D. Bug fixing is easy Ability to meet timing constraints

Ans: 33.

In a drive by wire RT system the highest priority task is A. C. Control system commands Control inputs A B. D. Sensor data acquisition Actuators

Ans: 34.

The response time in an RT system is not equal to the execution time. This is due to A. C. Release time jitter Multi-tasking C B. D. Low processor speed Complexity of job

Ans: 35.

An RT system is feasible, if A. C. All the tasks are able to meet deadlines Tasks are scheduled with equal priority A B. D. The system runs without halt Some tasks miss their deadlines

Ans: 36.

Nuclear power plant control is a A. C. Fast & hard RT system Slow & hard RT system C B. D. Fast & soft RT system Slow & soft RT system

Ans: 37.

Voice over packet switched networks is a A. C. Fast & hard RT system Slow & hard RT system D B. D. Slow & soft RT system Fast & soft RT system

Ans: 38.

Blocking of a high priority task due to a shared resource while a low priority task is running is A. C. Priority sharing Priority inheritance D B. D. Priority conversion Priority inversion

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Find the ODD one out A. C. Windows XP Vx Works A B. D. Windows CE C/OS-II

Ans: 40.

The correct sequence of Embedded Tool-Chain is A. C. ROM CHIP.HEX.EXE.OBJ.ASM .HEX.ASM.OBJ.EXEROM CHIP D B. D. .EXE.OBJ.ASM.HEXROM CHIP .ASM.OBJ .EXE.HEXROM CHIP

Ans: 41.

If you are servicing an 8051 based product which uses an 11.059 MHz crystal, you might expect to find port 3 being used as A. C. The high-order memory address bus connections A general-purpose 8-bit parallel I/O port B B. D. A serial port using standard baud rates Any one of the above, since the crystal frequency has no effect on how the I/O port is used

Ans: 42.

A microcontrollers serial port is full-duplex port. This means that A. C. The microcontroller uses a buffer to control the serial port. The serial port can transmit data at the same time it is receiving data. C B. D. The serial port can be receiving a second transmission before the first one is read. The serial port can either transmit or receive data but not both simultaneously

Ans: 43.

Clock stability is the highest for A. C. RC oscillator IC clock oscillator D B. D. Ceramic resonator Crystal oscillator

Ans: 44.

Power saving in an embedded system can NOT be achieved with A. C. Clever reduction of the clock rate Clever enabling and disabling of certain structural units in the processor by wait and stop instructions D B. D. Optimizing the codes Increasing clock rate

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Intel 8051 is a _______ type of processor A. C. CISC RISC A B. D. DISC ASIC

Ans: 46.

Flash/EEPROM chips need _____ power supply A. C. +5V +9V D B. D. + 3.3 V +12 V

Ans: 47.

A processor goes to STOP state when A. C. Receives STOP instruction Operates in auto-shutdown mode D B. D. Clock input is disabled Any of the above

Ans: 48.

The functions of OS kernel include: A. C. Task scheduler Inter-task communication D B. D. Task dispatcher All of the above

Ans: 49.

Task management in RTOS involve A. C. Task creation Task deletion D B. D. Task scheduling All of the above

Ans: 50.

The main components of a typical embedded system include A. C. Hardware Real Time Operating System D B. D. Application software All of the above

Ans: 51.

Identify the feature which is not applicable to Digital Signal Processor A. C. Low computational power and high communication capability Very Large Instruction Word capability A B. D. Multiply Add Accumulate Units Single Instruction Multiple Data

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Identify the odd one out of the following A. C. Microchip PIC16F84 Motorola 68HC11xx B B. D. Texas Instruments TMS320Cxx Atmel 89C51

Ans: 53.

Identify an Application Specific System Processor (ASSP) out of the following A. C. Intel 8051 IIChip W3 100A C B. D. Motorola 68HC11xx ARM 7

Ans: 54.

The highest power consuming part out of the following in a typical embedded system is A. C. CPU Main Memory B B. D. Backlight and Inverter System bus

Ans: 55.

Identify the incorrect statement regarding memory architectures A. C. 80x86 processors have Harvard architecture for main memory 8051 family microcontrollers have Harvard architecture A B. D. Separate memory addresses allocated for program and data in Harvard architecture ARM 7 has Princeton architecture for main memory

Ans: 56.

Identify the incorrect RAM; ROM; Flash; Cache status out of the following exemplary embedded systems A. C. Data acquisition system: 256 bytes; 8 kb; 512 bytes; No cache Robot: 16 bytes; 4 kB; No flash; No cache C B. D. Mobile phone: 1 MB; 1 MB; 32 kB; with cache Speech processor: 1 MB; 1 MB; 4 MB; with cache

Ans: 57.

Identify the incorrect statement out of the following A. C. In pipelining instruction execution is split in parts such as fetch, decode, execute and write Instruction decoder and scheduler plays an important role in superscalar processors B B. D. Instruction dependencies will not affect pipelining Superscalarity means using multiple execution units to achieve instruction level parallelism

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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Identify a module that is not a structural unit inside the processor A. C. ALU BIU D B. D. MAR DMA

Ans: 59.

Indicate which is not a performance metric for processors A. C. Baud rate MFLOPS A B. D. MIPS Dhrystone

Ans: 60.

Identify the incorrect statement of the following A. C. Instruction size varies in CISC Instruction size varies in RISC C B. D. Fixed instruction size in RISC Fixed instruction size in VLIW

Ans: 61.

Shared data can be protected with A. C. Disabling Interrupts Disabling task switches D B. D. Taking semaphores Any of the above

Ans: 62.

Identify the incorrect statement out of the following A. C. Global variables are stored in static memory Local variables, passing parameters to functions, etc. are stored in runtime stack D B. D. Dynamically allocated memory is called as Heap Initialized variables are stored in BSS segment

Ans: 63.

MODEM belongs to which of the following? A. C. Input Device Input Output Device C B. D. Output Device None of the above

Ans: 64.

Software development for an embedded system will be takes place in A. C. Host system Communication System A B. D. Target System Receiving system

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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65.

Identify the incorrect statement of the following regarding data rate of devices A. C. 56K MODEM: 7 kbits/sec ISA Bus: 16.7 MB/sec B B. D. USB: 15 Mbits/sec PCI Bus: 528 MB/sec

Ans: 66.

Identify the incorrect statement of the following A. C. In serial communication high data rates through long distances possible Serial communication is cheaper and less bulky, but interfacing logic is more complex D B. D. In parallel Communication high data throughput at short distance possible Parallel communication is very economical at longer distances.

Ans: 67.

Identify the incorrect statement of the following A. In simplex mode of transfer data stream can be transmitted in only one direction In full duplex mode data stream can be transmitted and received in both the directions simultaneously. D B. In half-duplex mode data is transmitted and received in either direction, but in only in one direction at one time. Modem is an example for Full duplex serial communication

C.

D.

Ans: 68.

Identify the incorrect statement of the following A. In synchronous communication the receiver clock maintains constant phase difference with the transmitter clock In asynchronous communication clocks of receiver and transmitter are independent B B. Transmitter does not transmit any clock rate information with the stream of data in synchronous communication Iso-synchronous is a special scheme where data frame may have variable maximum time interval.

C.

D.

Ans: 69.

The bus that connects processor and memory modules is A. C. Extension bus Expansion bus B B. D. System bus None of the above

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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70.

Bus that works asynchronously with the CPU is A. C. Local Bus Expansion Bus C B. D. System Bus Any of the above

Ans: 71.

Identify the incorrect statement of the following A. C. PCI is a high speed serial expansion bus I2C is a serial expansion bus A B. D. CAN is a serial expansion bus ATM is an advanced high speed serial bus

Ans: 72.

Identify the incorrect combination of the following: A. C. I2C: SDL & SCL USB: VBUS, D+, D- & GND D B. D. CAN: CSMA/CD+AMP I2C: RTR, VBUS, D+ and D-

Ans: 73.

Different sensors and actuators in an automobile can be interfaced with A. C. UART USB B B. D. CAN Bus I2C Bus

Ans: 74.

Indicate which of the following is platform independent A. C. ISA Bus Device Driver B B. D. PCI Bus Board Support Package

Ans: 75.

A platform for embedded system implies A. C. Chipset + OS bundled together Kernel + Drivers together A END OF QUESTION BANK B. D. RTOS + sensors together Chipset + Application Programs together

Ans:

DS404 EMBEDDED SYSTEMS DESIGN / Dr. B. MALLESWARA RAO/ USIC & DSD/ 2009-2010

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