BASE BAND MODEM HARDWARE DESIGN

P. Antognoni (1), E. Sereni (1), S. Cacopardi (1), S. Carlini (2), M. Scafi (2)
(1)

CNIT DIEI University of Perugia Via G. Duranti 93, 06125 Perugia Italy {antognoni, sereni, cacopardi}@diei.unipg.it Digilab 2000 s.r.l. Via A. Vici 4, Foligno PG 06034 Italy {carlini, scafi}@digilab2000.it
(2)

ABSTRACT In this paper the base band CDMA (Code Division Multiple Access) modem hardware design is described. The implemented design has been developed within the University research project sponsored by ASI (Italian Space Agency) in collaboration with CNIT (National Interuniversity Consortium for Telecommunications) Integration of Multimedia Services on Satellite Connected Heterogeneous Networks. The aim of this project is to connect more University sites in order to establish videoconferencing, data exchange and other multimedia high bit rate communications. So to have this link, we have designed an high performance modem, able to grant a full duplex data flow. The challenge is that to implement a CDMA modem, developing both the hardware platform and the software performing the data processing. Obviously, the most innovative idea is to implement multi user detection algorithms at the reception, where it is required an high processing capacity due to the large quantity of operations needed to reject the other users interference, and, to enhance the performance of the user to be detected. 1 INTRODUCTION DSP technology has performed in last years a significant improvement, allowing the design and implementation of real time communication systems such as the cellular handsets and base stations running at higher and higher bit rates. The CDMA access technique is very processing consuming, so to grant system flexibility we have chosen to develop the modem around a DSP core, based on the most powerful devices from Texas Instruments. So, the hardware design presented in this paper can be considered a Software Radio Development System to test and verify a lot of communication systems algorithms, different from CDMA too [1]. Indeed the whole board is software configurable, so fitting with every kind of base band modem testing and development environment. To allocate the radio frequency section, which performs the transmitter up conversion, and the receiver down conversion, we have included in our board some expansion connectors, but the main interests have concerned with digital base band design. In order to satisfy both the high performance requests, and the full software programmability, the devices selection has leaded to the hardware architecture illustrated in the following section. 2 HARDWARE ARCHITECTURE 2.1 General Description The whole architecture can be conveniently subdivided in three main parts: Microcontroller section. DSP1 section. DSP2 section. The DSPs are devoted to signal processing; while the microcontroller is involved with data flow transfers, asynchronous events management, and board boot and devices initialisation. A block diagram of the designed board is represented in Fig. 1: the main logical data flow and connections are evidenced.

To external interface RESET Serial port 2 SCIF Serial port 0 PLL BSC To external interface From external interface

Clock Circuitry

PLL

Micro Controller
SCIF

DSP 1
RESET EMIF HPI

RX_FIFO RX_FIFO

Serial port 1

SCI

(32 bit, 125 MHz) (32 bit, 125 MHz)

DP-SRAM 2 DP-SRAM 2

RS 232 RS 232
To PC

To external

SRAM SRAM
(16-bit) (16-bit)

SRAM SRAM
(16-bit) (16-bit) (32 bit, 25 MHz) (32 bit, 25 MHz)

HPI EMIF

Serial port 2

interface

DP-SRAM 1 DP-SRAM 1

DSP 2
Serial port 1 Serial port 0 RESET PLL To external interface

FLASH FLASH memory memory

To external interface

TX_FIFO TX_FIFO

Fig. 1. Modem hardware architecture block diagram. 2.2 Microcontroller Functionalities The hardware platform intelligence consists of a Micro Controller Unit (MCU) SH7709A from Hitachi [2]. It is devoted to initialise and synchronize the DSPs, exchange board data with the PC, regulate data flow between DSPs and memories, control bus accesses for all devices on the main bus, and allow communications between local memories and external devices located on peripheral boards. In the following paragraphs, the description of the microcontroller specifications is carried out. Therefore, the MCU control technique, i.e. the software that is not data-flow oriented (signal processing), but management oriented (interrupts service routines), is described. The architecture shown above influences microcontroller choice, which must include some well-defined features: Interfacing capability to various devices to support handshaking protocols management with all the on-chip processing units. Faculty to boot the DSPs getting their firmware from non-volatile memory and data from exchange static memories. Interrupt servicing capacity, acting as both source and target, for all the devices to be controlled. Computational power to manage data exchange with the PC. Some general-purpose signals, enough to communicate with all the units to be managed. Control-oriented software primarily aims at resource allocation and interrupts management. Typically, runtime interrupt routines are used to handle exceptional events that can occur, thus causing an interruption and deviation from the ordinary processing flow. The processor then activates an emergency procedure, and takes the necessary precautions to resume the process from the suspension point, saving the process "context" (i.e. all the variables defining the processor state and the values involved in the current process). After the interrupt requests have been served, the CPU restores the previous context and resumes the original process. Typically, the most of program functionalities, and in particular algorithms, are contained into the main function. A different interrupt service routines usage enables the implementation of a modular programming technique, where modular units are constituted by the interrupt routines themselves. Program functionalities are distributed into several interrupt procedures, having poor interfaces and being each other independent: the main function has only to configure registers and initialise variables. This interrupt management technique provides an efficient method for the microcontroller to synchronize and control algorithms execution.

Moreover, by virtue of the DSP interrupt controller architecture, the microcontroller can be always notified about the execution status of each DSP algorithm. 2.3 Data Bus Management One main point of the hardware architecture is the local (in the designed board) bus. Bus transactions occur between the bus master, which is the SH7709A MCU, and the targets, i.e. the two DSPs, the Dual Port Static RAM1 (DPSRAM1), the other static RAM, the FLASH memory, and the external bus interface (the interface toward other identical boards). Due to the high number of devices located on the bus, some switches from IDT are used to overcome the electrical loading limits. To access a resource, the microcontroller provides the communication path by turning on the involved switches, necessary to establish the electrical connection (for example, to access the static RAM, the memory area switchs and the SRAM switchs must be turned on). All unexploited bus switches are placed in a high impedance mode. Such architecture supports external accesses, toward any bus resource, from a secondary bus master. The microcontroller provides internal arbitration for up to four secondary bus masters (i.e. bus masters located on external modems), allowing a total of five potential bus masters for the primary bus (the bus where the arbiter is located on). The arbitration scheme on the primary bus for priority bus-master handling is outlined below. The designed modem implements bus request and bus grant (H_IRQ4 and H_IRQ5, PORT_OUTA and PORT_OUTB in the schematics design) signals for bus arbitration. These request and grant signals are connected to the internal arbiter, the MCU, respectively through the IRQ4-IRQ5 interrupt pins and the PTG4-PTJ7 general-purpose pins [2]. The microcontroller from an external identical CDMA modem, acting as a master, asserts H_IRQ4 or H_IRQ5, to initiate a transaction toward the internal bus of another modem. At the same time, the initiator sends a coded word. The microcontroller located on the initiated modem, acting as the local arbiter, in response to a H_IRQ4 or H_IRQ5, asserts PORT_OUTA and PORT_OUTB. Then the external device is enabled to initiate a transaction toward the primary bus. This interrupt based arbitration scheme improves performance in systems in which master devices do not all require the same bandwidth. A high priority level can be assigned to any master that requires ordinary bus use [4]. 3 MAIN BOARD FEATURES The first board prototype photo is depicted in Fig. 2. In order to have full test and debug features, some connectors have been installed, further some switches allowing separating the three main sections have been inserted. In this manner the prototype dimensions have increased up to reach 260 x 230 millimetres. To realize a full modem device, the previously mentioned Radio Frequency (RF) stage should be attached to our board, including a digital to analog converter (DAC), and a modulator (mixer or up converter) for the transmitter side, and the dual devices, down converter and analog to digital converter (ADC) at the reception, but this board has not yet been designed, giving an higher priority to the base band board debugging. The board routing has leaded to a ten layers printed circuit board realization due to the dual BGA packages and to high devices density. In order to reduce signal degradation some precautions have adopted like: Blind and buried holes. Ground planes to isolate the most speed critical signals. Signal regenerator devices to avoid excessive amplitude attenuations.

DSP 1 MCU DSP 2

Fig. 2. First CDMA modem prototype photo. 3.1 Devices List and description Besides the microcontroller unit, whose main features have been detailed previously, the following main devices are included in our modem: TMS320C6202 250 MHz DSP from Texas Instruments. Dual port memories and FIFOs from IDT. Static RAM from Alliance semiconductor. FLASH memory from Micron. Obviously the DSPs concerns with the most of signal processing, but this paper does not deal with this matter, so our attention is mainly dedicated to its hardware characteristics [3]: High fixed point performance up to 2400 MIPS (Million Instructions Per Second). Eight independent functional units. 3 Mbit on chip RAM. Glueless interface to synchronous and asynchronous memories. Small BGA (ball grid array) package thanks to 0.18 m Level Metal Process. Dual port memories allow high speed transfers between the DSPs, and between DSP2 and the microcontroller; in the first case a maximum clock frequency of 125 MHz can be reached, so reducing dangerous bottlenecks in real time systems such as multi user detection and synchronization. The FIFO memories permit interfacing with the RF board, granting the correct synchronism between the DSP external memory interface writing or reading in burst mode, and DAC and or ADC, which are clocked synchronous devices. Particular care has to be dedicated by the microcontroller to avoid FIFO empty or FIFO full events, because these ones lead to data losses, and the whole system should be re-initialised.

4 CONCLUSIONS In this paper we have illustrated the main characteristics of an innovative modem design such as a CDMA modem. The high processing capability available lets the user having a great test environment useful for both academic research and development, and for product manufacturers tests too. In fact nowadays such a powerful development tool is not yet available, and thanks to the ASI-CNIT project it has been possible to reach up to the prototype implementation, which is not usual in a University project. At the end of the debugging and testing phase which is now going on, a full working device will be used by each University working in the mentioned research project, to run and test the algorithms implemented through software and evaluation modules simulations. When both the hardware and the software will work correctly we could establish videoconferencing using a self-made tool. REFERENCES [1] [2] [3] [4] S. Reichart, B. Youmans, R. Dygert, The Software Radio Development System, IEEE Personal Communications, August 1999, Vol. 6 No. 4. Hitachi SuperH RISC engine, SH7709A Hardware Manual, ADE-602-187 Rev. 1.0, 4/14/99, Hitachi, Ltd. TMS320C6202, TMS320C6202B, Fixed Point Digital Processor, SPRS104C October 1999 Revised December 2000, Texas Instruments. J. Hennessy, D. Goldberg, D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, January 1996.