American University of Beirut

Department of Electrical and Computer Engineering EECE 311 Electronic Circuits Homework 1 Solution Problem 1 Refer to Figure 6.4 in the textbook. Using VDD = 2 V and a pair of identical MOSFETs, design the current source in the figure to provide an output current of 30 QA, nominal. The nominal output current is obtained when the V O = VGS. The output voltage is required to operate in the range 0.4 V to V DD = 2 V, and it is also required that the change in the output current over this range be limited to 3% of the nominal value. a) Find the required values of R and all device dimensions (W and L). The technology parameters are: kn = 270 QA/V2, VAn = 15 V/Qm, and Vtn = 0.5V. Do not neglect channel-length modulation in your design. For Q2 to stay in SAT: VGS = VO(min) + Vt = 0.4 + 0.5 = 0.9V Q1 is always in SAT IREF = 30 A    = Spring 2010

W = 4.772 m

b) Using PSpice, verify that the nominal value of IO is obtained at VO = V GS, and that the change in IO is limited to 3% of its nominal value, when VO changes from 0.4 V to VDD. Include the SPICE netlist, and a printout of the plot of the variation of the output current when the output voltage increases from 0 to V DD.

30. 8uA ( 1. 9971, 30. 6 30. 6uA

30. 4uA

30. 2uA ( 9 0 0 . 0 0 0 m, 2 9 . 9 9 8 u )

30. 0uA

29. 8uA

2 9 m, 2 9 . 7 2 7 u )

29. 6uA 0. 4V 0. 5V I D( M2 )

0. 6V

0. 7V

0. 8V

0. 9V

1. 0V

1. 1V

1. 2V V0

1. 3V

1. 4V

1. 5V

1. 6V

1. 7V

1. 8V

1. 9V

2. 0V

As shown in the graph as Vo changes between 0.4 V and 2 V, Io changes between 29.727 QA and 30.6 QA, and as seen also at V O = VGS=0.9V, IO is equal to its nominal value(30uA), and the change is 2.91% of its nominal value.

Problem 2 Refer to Figure 6.18 (a) in the textbook. A common-source CMOS amplifier similar to the one shown in Fig. 6.18 (a) in the textbook uses a supply voltage V DD of 2 Volts, and a bias current IREF of 30 QA. The MOSFET parameters are: W/L = 15 for Q2, W/L = 4 for Q3, kn = 270 QA/V2, kp = 110 QA/V2, V An = 1/Pn = |VAp| = 1/| Pp| = 16 V, Vtn = 0.5 V, and Vtp = 0.55 V. Do not neglect channel-length modulation in the DC analysis.

a) Find the value of VSG of Q2 . VSG for Q2 is equal to VSG for Q3         

c) Find W/L for Q1 if the drain current found in part (b) corresponds to vI = VDD/2 and vO = VDD/2.

d) Find the value of vO and the corresponding value of vI at which Q2 leaves the saturation region.

e) Find the value of vO and the corresponding value of vI at which Q1 leaves the saturation region. Q1 is a the edge of SAT

f) Find the value of the small signal voltage gain vo/vi around the DC bias point (VI = V DD/2, V O = VDD/2)

g) Find the value of the output resistance R o.

b) Fi

drai current of Q1 when vO = VDD/2.

h) Simulate the circuit in PSpice to derive the voltage transfer curve ( vO versus vI ) when vI varies between 0 V and 2 V. This is done as follows: vi input_node 0 DC 0V .DC vi 0V 2 V 0.001V where input_node is the number you assigned to the input node. The .DC statement sweeps vI from 0 V to 2 V in 1 mV steps. Using the Probe trace of V(output_node) , where output_node is the number you assigned to the output node, note that for a range of values of vI , the gain |dvO/dvI | is large and approximately constant. What is this range of values of vI ? What is the corresponding range of values of vO ? How do the values compare with the results of parts (d) and (e)?

2. 0V ( 9 8 0 . 0 0 0 m, 1 . 6 6 2 6 )

1. 5V

1. 0V

( 1 . 0 1 5 0 , 5 0 2 . 7 3 1 m) 0. 5V

0V 0V V( 3 ) Vi 0. 2V 0. 4V 0. 6V 0. 8V 1. 0V 1. 2V 1. 4V 1. 6V 1. 8V 2. 0V

The range of values of vI is 0.98 V to 1.015 V, and that of vO is 0.502731 to 1.6626 V t, which is close to the values obtained.

i) Bias the transistor at ( VI = V DD/2, V O = VDD/2), and apply a sinusoidal input with an amplitude equal to 5 mV. Run a transient analysis using such a sinusoidal source (at a frequency of 1 KHz): vi input_node 0 SIN(DC_bias Amplitude 1KHz) .Tran 5us 8ms 5ms 5us DC_bias is VDD/2 and Amplitude is 5 mV. i.1) Verify, from the Probe plots of vO and vI , that the AC gain is close to the value calculated in part (f).

1. 2V

1. 1V

1. 0V

0. 9V

0. 8V 5 . 0 ms 5 . 2 ms V D( M1 ) V( 4 )

5 . 4 ms

5 . 6 ms

5 . 8 ms

6 . 0 ms

6 . 2 ms

6 . 4 ms T i me

6 . 6 ms

6 . 8 ms

7 . 0 ms

7 . 2 ms

7 . 4 ms

7 . 6 ms

7 . 8 ms

8 . 0 ms

The gain here is (1.6626 0.502731) / (0.98 1.015) = -33.139 V/V, same as the value obtained. i.2) Now change Amplitude to 50mV, and run the transient analysis. How do you explain the shape of the output waveform?

2. 0V

1. 5V

1. 0V

0. 5V

0V 5 . 0 ms 5 . 2 ms V D ( M1 ) V( 4)

5 . 4 ms

5 . 6 ms

5 . 8 ms

6 . 0 ms

6 . 2 ms

6 . 4 ms T i me

6 . 6 ms

6 . 8 ms

7 . 0 ms

7 . 2 ms

7 . 4 ms

7 . 6 ms

7 . 8 ms

8 . 0 ms

The output becomes distorted. With such variations in input, the value of vi becomes outside the allowed range for SAT operation of the amplifying MOSFET. j) Find the output resistance of the amplifier. This is done in SPICE as follows: Set the input source vI to V DD/2 (this is a zero-volt AC input source!), and connect an AC voltage source vx to the output node via a 1 Farad capacitor (this capacitance is needed in order not to disrupt the DC bias, and results in a negligible impedance of 0.16 m; at the AC frequency of 1 KHz): vx test_node 0 AC 1 cx test_node output_node 1 (do not add F after 1) where test_node is the number you assigned to the test node to which vx is connected. Run an AC analysis at 1KHz using: .AC LIN 1 1KHz 1KHz .PRINT AC i(vx) The .PRINT statement will print the value of ix. After running PSpice, click on View -> Output File then scroll down to **** AC ANALYSIS to read the value of ix = I(vx). Calculate the value of the output resistance from this value of ix. Compare with the value calculated in part (g).

Ro = Vx/Ix =

which is close to the value obtained.