PSoC Fundamentals: Sleep Mode

AN47310
Author: Cole Wilson Associated Project: Yes Associated Part Family: All PSoC Devices GET FREE SAMPLES HERE Software Version: PSoC Designer 4.4 or PSoC Express 3.0 Associated Application Notes: None

Application Note Abstract

This application note is part of PSoC Fundamentals series of application notes. This application note describes Sleep Mode operation and other power savings techniques for PSoC.

Introduction
Power Consumption is an important aspect of microcontroller designs. Among the several techniques to reduce the average current used by PSoC, Sleep Mode is most popular. PSoC uses Sleep Mode when it is not required to perform any function, similar to a cell phone backlight dimming after an idle period. This is done to reduce the average current consumed by the device, a necessity of all battery applications. The PSoC enters Sleep Mode by writing a 1 to the SLEEP bit within the CPU_SCR0 register (Bit 3). This is accomplished by calling the M8C_Sleep macro. While in Sleep Mode, the Central Processing Unit (CPU) is stopped, the Internal Main Oscillator (IMO) is disabled, the Bandgap Voltage reference is powered down, and the Flash Memory Model is disabled. The only circuits left in operation, are supply voltage monitor and 32 kHz internal oscillator. Power saving techniques other than Sleep Mode are: Disable PSoC Analog Block References Disable CT and SC Blocks Disable PSoC Analog Output Buffers Set Drive Modes to Analog High Z Sleep Mode has negative effects for a design. If not used carefully, it can cause unpredictable operation. The PSoC must be correctly woken up from sleep when necessary and the user must be aware that sleep is taking place to allow extra processing. This app note also details the process of getting out of Sleep Mode and the issues regarding sleep mode.

Additional Power Saving Techniques

All the power saving techniques with the exception of sleep mode is application based and some of these produces undesirable results. Each technique is discussed in detail below.

Disable PSoC Analog Block References

PSoC Analog Blocks have individual power down settings that are controlled by firmware. Continuous Time blocks remain in operation because they do not require a clock source. However, Switch Capacitor blocks do not operate because there is no clock source for 1 and 2 switches. For devices other than CY8C21x34 and CY8C21x23, the Analog Block References can be disabled by the following register write to the ARF_CR register: ARF_CR &= 0xf8; // A Ref Off

Disable CT and SC Blocks

For any PSoC device, Continuous Time blocks is powered down individually by writing each CR2 register corresponding to the blocks column. Switch Capacitor blocks are controlled by the CR3 register. As an example, the column zero Continuous Time and Switch Capacitor blocks is powered down by the following register writes. ACB00CR2 &= 0xfc; // CT Block ASC10CR3 &= 0xfc; //Type C SC ASD20CR3 &= 0xfc; //Type D SC

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Disable Analog Output Buffers

The analog output buffers which connect analog column outputs to output pins are disabled to save power. This is accomplished by writing to ABF_CR0 register. Some parts do not have analog output buffers or do not contain the maximum of four analog output buffers. In these cases fewer bits are reset in the register. Below is an example of disabling all four analog output buffers. ABF_CR0 &= 0xc3; // Buffer Off

Set Drive Modes to Analog High Z

The state of the PSoC drive modes can affect power consumption. You may change only the drive modes on pins that do not cause adverse affects to the system. The change must occur in a sequence that does not produce line glitches. This sequence depends on the current drive mode of the pin, and the state of port data register. With the PSoC drive mode structure, the pin must temporarily be in either Resistive Pull Up or Resistive Pull Down drive modes when switching between High Z or Strong drive modes. The temporary drive mode is opposite of the previous value on the pin. So, if the pin was driven HIGH then the temporary drive mode must be Resistive Pull Down. This ensures that the drive mode of the pin is not resistive, which eliminates any possible glitch. The drive modes are set manually in software, before going to sleep. There are three registers, PRTxDM0, PRTxDM1, and PRTxDM2, which control the drive modes. One bit per register is assigned to a pin. So, to change the drive mode of a single pin, three register writes are needed. However, this is convenient because an entire port is changed by the same three register writes. The correct pit pattern for Analog High Z is 110b. Below is the code to set port zero to Analog High Z, from Strong, by first going to Resistive Pull Down. PRT0DM0 = 0x00; // low bits PRT0DM1 = 0xff; // med bits PRT0DM2 = 0xff; //high bits

void PSoC_Sleep(void){ M8C_DisableGInt; ARF_CR &= 0xf8; // analog blocks Off ABF_CR0 &= 0xc3; // analog buffer off PRT0DM0 = 0x00; // port 0 drives PRT0DM1 = 0xff; PRT0DM2 = 0xff; PRT1DM0 = 0x00; // port 1 drives PRT1DM1 = 0xff; PRT1DM2 = 0xff; PRT2DM0 = 0x00; // port 2 drives PRT2DM1 = 0xff; PRT2DM2 = 0xff; M8C_EnableGInt; M8C_Sleep; }

Sleep Mode Complications

The PSoC can exit sleep either from a reset or through an interrupt. There are three types of resets within the PSoC: External Reset, Watch Dog Reset, and Power on Reset. Any of these resets takes the PSoC out of sleep mode and once the reset de-asserts, the PSoC begins executing code starting at Boot.asm. Available interrupts to wake the PSoC are: Sleep Timer, Low Voltage Monitor, GPIO, Analog Column, and Asynchronous. Sleep mode complications arise when using interrupts to wake the PSoC or attempting digital communication while asleep. These considerations are discussed in detail below.

Pending Interrupts
If an interrupt is pending, enabled, and scheduled to take after a write to the SLEEP bit in the CPU_SCR0 register, the system will not go into sleep. The instruction still executes, but the PSoC does not set the SLEEP bit. Instead, the interrupt is serviced which effectively causes the PSoC to ignore the sleep instruction. To avoid this, interrupts should be globally disabled while sleep preparation occurs and then re-enabled just before writing the SLEEP bit.

Global Interrupt Enable

The Global Interrupt Enable register (CPU_F) need not to be enabled to wake the PSoC from interrupts. The only requirement to wake up from a Sleep by an interrupt is to use the correct interrupt mask within the INT_MSKx registers, like the example below. If global interrupts are disabled, then the ISR that wakes the PSoC is not executed but the PSoC still exits sleep mode.

Putting it All Together

Below is a sample of a typical sleep preparation sequence for a 28-pin part. In this sequence, interrupts are disabled, the analog circuitry is turned off, all drive modes are set to Analog High Z, and finally interrupts are re-enabled.

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In this case, the user must manually clear the pending interrupt or enable global interrupts to allow the ISR to be serviced. Interrupts are cleared within the INT_CLRx registers. //Set Mask for GPIO Interrupts M8C_EnableIntMask(INT_MSK0, INT_MSK0_GPIO) // Clear Pending GPIO Interrupt INT_CLR0 &= 0x20;

that the PSoC will wake up on any I2C falling edge traffic, which causes more total active time and higher sleep currents. Another solution is to use a 3rd GPIO pin to wake up the PSoC and then send the initial START condition after the appropriate delay time.

Sleep Timer
The PSoC offers a sleep timer and a sleep timer user module. These are used while PSoC is asleep and both perform similar functions. The actual sleep timer runs off of the internal low speed oscillator, which is never turned off. At selectable intervals of 1Hz, 8Hz, 64Hz, and 512Hz, the timer generates an interrupt. It is often useful to periodically wake the PSoC up to do some processing or check for activity. An example of this would be to periodically wake up to scan a sensor. The sleep timer user module uses the sleep timer to generate some additional functionality. This functionality includes a background tick counter to generate periodic interrupts, a delay function for program loops, a settable down counter, and a loop governor to control loop time. A simple block diagram for this functionality is shown below in Figure 1. Figure 1: Sleep Timer User Module Block Diagram

Post Wake up Execution Sequence

If the PSoC is woken up through a reset, then execution starts at the beginning of the boot code. If the PSoC is woken up by an interrupt service routine, the first instruction to execute is the one immediately following the sleep instruction. This is because; the instruction immediately following the sleep instruction is pre-fetched before the PSoC is fully asleep. Therefore, if global interrupts are disabled the instruction execution will continue where it left off before sleep was initiated.

PLL Mode Enabled

If PLL mode is enabled, the CPU frequency must be reduced to minimum 3MHz before going to sleep. This is because the PLL always overshoot as it attempts to relock after the PSoC wakes up and it is re-enabled. Additionally, it is recommended to wait 10ms after wake up before normal CPU operation commences to ensure proper execution. This implies that to utilize Sleep Mode and the PLL, the software must be able to execute at 3MHz. A simple write to the OSC_CR0 register can reduce CPU speed. However, this register just sets a divider of SYSCLK, which means the CPU speed will vary between part families with different SYSCLKs. Typically, SYSCLK is 24MHz. OSC_CR0 &= 0xf8; // CPU = 3 IMO = 24

Sample Project Results

Execution of Global Interrupt Enable
It is undesirable to get an interrupt on the instruction boundary of writing the SLEEP bit. This could cause all firmware preparations for going to sleep to be bypassed, if a sleep command is executed on a return from interrupt (reti) instruction. To prevent this, interrupts are temporarily disabled before sleep preparations and then re-enabled before going to sleep. Due to the timing of the Global Interrupt instruction, it is not possible for an interrupt to occur during the next instruction, which in this case is setting the SLEEP bit. The code within the associated example project has tests for four different modes: normal operation, typical sleep mode, sleep mode with additional no analog circuitry, and sleep mode with all additional power savings techniques. Each method is removed from the project by disabling the appropriate #ifdef value. In the project, all analog blocks are initially turned on to full power and the CPU is set to 24 Mhz. This creates a worse case situation. Different levels of power consumption techniques, as discussed by this application note, were incrementally added in. The results of these tests are shown below in Table 1. A register reference for commonly used sleep mode registers is contained in Appendix 1. Table 1: Power Consumption Test Code Results
Mode Normal Operation Typical Sleep Mode Analog Disabled Full Power Savings Current (mA) 15.6210 6.1900 0.6473 0.0032

I2C Slave with Sleep Mode

There are a few complications being an I2C Slave and using Sleep Mode. Because the IMO and CPU are shut off during sleep, there is no processing within the PSoC. The problem arises with the I2C address. When an I2C START condition is sent to a particular address, the PSoC cannot processes the address and therefore responds with a NAK. A typical work around is to set up falling edge interrupts on either the clock or data lines of the I2C bus. The master can then send a dummy START condition to wake up the PSoC. There is some lag time between waking up and being able to process an I2C address, so the master may need to delay up to 200s before the next transmission or continue to send until an ACK is received. This solution has a second problem in
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Appendix 1: Register Reference

Name Address Description This register is used to control the analog input muxes from port 0, bypass amplifier inputs, and control the analog output buffers. This register is used to configure the various features of the analog references such as: bias level, reference value, and power. This register provides read access to the M8C Flags. This register is used to clear posted interrupts. This register is used to clear posted interrupts. This register is used to clear posted interrupts. This register is used to clear posted interrupts. This register is used to create pending interrupts that can then be posted. This register is used to create pending interrupts that can then be posted. This register is used to create pending interrupts that can then be posted. This register is used to create pending interrupts that can then be posted.

ABF_CR0 ARF_CR CPU_F INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK0 INT_MSK1 INT_MSK2 INT_MSK3

0x62 0xF3 0xF7 0xDA 0xDB 0xDC 0xDD 0xE0 0xE1 0xDF 0xDF

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About the Author

Name: Title: Background: Contact: Cole Wilson Applications Engineer Bachelors of Electrical Engineering from the University of Washington Cypress Semiconductor Lynnwood, WA USA

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Document Title: PSoC Fundamentals: Sleep Mode Document Number: 001-47310
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