You are on page 1of 8

Dead-Time Elimination Method and Current Polarity Detection Circuit for ThreePhase PWM-Controlled Inverter Yong-Kai Lin

Student Member, IEEE Center for Power Electronics Technology, National Taipei University of Technology 1, sec. 3, Chung-Hsiao E. Rd. Taipei, 10608 Taiwan t5319006@ntut.edu.tw
Abstract -- This paper will present a dead-time elimination scheme and the related current polarity detection circuit without separate power sources for three-phase inverters. The presented scheme includes the freewheeling current polarity detection circuit and the PWM control generator without dead time. It will be shown that the presented scheme eliminates the dead time of PWM control for inverter and therefore dramatically improving the output voltage loss and current distortion. Experimental results derived from an FPGA-based PWM-controlled inverter are shown for confirmation. Index Terms-- Pulse-width modulation, dead-time elimination

Yen-Shin Lai
Senior Member, IEEE Center for Power Electronics Technology, National Taipei University of Technology 1, sec. 3, Chung-Hsiao E. Rd. Taipei, 10608 Taiwan yslai@ntut.edu.tw devices are detected only at the instants of rising edge of turn-on for PWM control as shown in [15]. It may result in detection error due to switching noise and current ripple in practice and therefore causing commutation error. Comparison results of previous arts and the proposed one are summarized in Table 1. There are three categories: (1) dead-time compensation [3-11], (2) dead-time elimination [13-15], (3) dead-time minimization [16-19]. For the deadtime minimization method, dead time is required as current is smaller than a certain value. And this current level depends upon the resolution of current sensor. This paper will present a dead-time elimination scheme for three-phase PWMcontrolled inverter. The presented dead-time elimination scheme doesnt require separate power supplies for freewheeling current detection of high-side and low-side power devices. Therefore, only one power source is required for freewheeling current polarity detection of three-phase inverter. Comparison Results of Methods
Method Items Parameters Current Sensor Isolated Power Dead Time [3-12] [13-15] [16-19] Proposed Method TABLE 1

I. INTRODUCTION To avoid short through of high-side and low-side power devices dead time is used in PWM-controlled inverter. The dead time mainly depends upon characteristics of power devices and gate drive circuit. Dead time results in output voltage loss and current distortion [1]. The impact is relevant as switching frequency increases and voltage becomes low. Furthermore, the common-mode voltage is also affected by dead-time of PWM controlled inverter as shown in [2]. Some methods have been presented to cope with this dead time issue. These methods include dead-time compensation [3-12], dead-time elimination [13-15] and dead-time minimization [16-19]. Most of the dead-time compensation methods are developed based upon the knowledge of current polarities. In order to detect the current polarity, accurate current sensor is required. However, the result is highly affected by the harmonics around the zero-crossing points, especially when the current becomes small. Furthermore, some dead-time compensation methods [10-11] highly depend upon the plant parameters. Dead time is still required for dead-time minimization method when the current is in the adjacent of zero-crossing points where the current polarity detection becomes difficult and inaccurate. Therefore, the dead-time effect cant be fully mitigated. Current polarity is determined by detecting the terminal voltages of anti-parallel diode of power device as shown in [13-15] for dead-time elimination. In [13-15], dead-time elimination method is developed based upon the detection method. However, two power sources are required for each inverter leg. For three-phase inverter, four power sources for such detection circuits are required. And the conduction states of anti-parallel diode of power

= Required; = Not Required The freewheeling current polarity detection circuit and the PWM control generator without dead time are presented in this paper. Current polarity is detected regularly with a sampling frequency which is higher than the switching frequency to reduce the detection error. Experimental results derived from an FPGA-based PWM-controlled three-phase inverter are shown to demonstrate the effectiveness. II. EFFECT OF DEAD TIME

Fig. 1 (A) shows the circuit of an inverter leg. For conventional PWM control method, the PWM signals for high-side and low-side power devices are with 180-degree phase shift. Due to the delay of drive circuit and turn-off delay of power devices, these control signals are modified by

978-1-4244-2893-9/09/$25.00 2009 IEEE

83

adding a dead time in ach rising pulse, td, such as PWM A+ and PWM A- in Fig. 1 (B). This additional dead time results in output voltage distortion which is defined as the difference between va, ideal and va, real shown in Fig. 1 (B). As shown in Fig. 1 (B), the real output voltage is greater (smaller) than its command as the current polarity is negative (positive). Fig. 2 shows the phase voltage and current of inverter output. As shown Fig. 2, the output voltage, vo(t), is with distortion as compared to that without dead-time (see waveform A and waveform B). Moreover, waveform A and waveform B cross with each other at points, P1 and P2. The output current, io(t), is also distorted at these two zerocrossing points as shown in Fig. 2.

III. PROPOSED DEAD-TIME ELIMINATION SCHEME A. PWM Generator without dead time Fig. 3 (A) shows the circuit of an inverter leg. As shown in Fig. 3(A), an anti-parallel diode is connected with power device. As the power device is off while the current conduction continues, the anti-parallel diode of its opposite power device provides the current path. Under this situation, it is no need to turn on the opposite power device during this turn-off period. Once no switching occurs to its opposite power device, dead time is not needed anymore. For example, when power device A+ is turned off and the current direction retains, Da- will provide the current path while power device A+ is turned off. Similar facts occur to power device A- and the diode Da+. Therefore, power device A+ and the diode Da- are defined as a P cell which provides conduction path for positive current (current flowing into the load side) as shown in Fig. 3 (B). And power device A- and the diode Da+ are defined as N cell (as shown in Fig. 3 (C)) which conducts negative current.
P A+ Da+

(A). Inverter leg

va
AN
(A). Inverter leg

Da -

(B). Voltage distortion caused by dead time Fig. 1. Voltage distortion caused by dead time

(B). P-cell

Fig. 2. Current distortion caused by dead time

Fig. 3.

(C). N-cell P-cell and N-cell of inverter

84

Fig. 4 shows the PWM control signals without dead time. As shown in Fig. 4 (A), P-cell control is applied to power devices while the current polarity is positive. N-cell control as shown in Fig. 4 (B) is used when current polarity is negative. Therefore, dead time is no more required while guaranteeing no short through between positive and negative DC links. Similarly, the when the current is negative, PWM control signal is applied to N-cell only. Since there is no switching in the power device of P-cell, dead time is no more needed and no short through will occur. Fig. 5 shows the relationship between PWM signals and the control signals of A phase of inverter without dead time. The control signals are therefore can be summarized as (1) and (2). Moreover, PWM control signals of phase B and phase C can be generated according to current polarity of ib and ic, respectively.

Fig. 5.

Signals for PWM generator

PWM A + = PWM a isgn(ia )

(1) (2)

PWM A = PWM a isgn(ia )

As shown in (1) and (2), the required calculation is simple and only slight modifications which can be realized by digital controller to the PWM signal are required. For inverter control, the conventional PWM signal is changed to PWM control signal and the PWM generator can be realized using (1) and (2).

B. Freewheeling current polarity detection circuit without isolated power Fig. 6 shows the polarity detection of freewheeling current [15]. As shown in Fig. 6, the detection circuit requires two separate power sources, Vcc1 and Vcc2. The required number of separate power sources is increased up to 4 for three-phase inverter. These separate power sources increase the difficulty for modularization of the detection circuit. Fig. 7 shows the presented freewheeling current polarity detection circuit of A phase. And the presented circuit requires only one power source for three-phase inverter. This special feature provides the potential of modularization of the detection circuit. In Fig. 7, when ia > 0, the terminal voltage becomes negative during the switching-off period as shown in Fig. 8 (A). During this period, the output signal of comparator, Dan, will latch at high logic level. And Dan will change to low logic level if ia reduce to zero. Similarly, during the switching-off period, the terminal voltage is positive and greater than the DC-link voltage when ia < 0 as shown in Fig. 8 (B). During this period, the output signal of comparator, Dap, will latch at high logic level. And Dap will change to low logic level if ia increase to zero. Therefore, the terminal voltage can be used to reflect the polarity of freewheeling current. Once the polarity of current is determined, the control signals of inverter can be generated by (1) and (2).

(A). P-cell control, ia > 0

Fig. 4.

(B). N-cell control, ia < 0 PWM control based upon P-cell and N-cell

Fig. 6.

Previous detection circuit [15]

85

P A+ VPN A N VPN/k
R3 R4 R1 R2 +15 V 2R R
-

Da + va ia Da -

Chop off and zero crossing point is less greater than 0.5(1D)ts, the average current becomes negative and the current polarity is changed. The polarity change rule is therefore modified as follows. 1 If tm > (1 D)t s , 2 then ia ,avg > 0 and no change of current polarity

Dap

va/k

+15 V 2R R

Dan

N Detection Circuit
Fig. 7. Proposed detection circuit

1 If tm (1 D)ts , 2 then ia ,avg 0 and the current polarity is change where tm = time interval between PWM off and zero-crossing point. m =1, 2, 3 The presented circuit for dead-time elimination circuit and method are indeed effective. More details about the experimental results for confirmation will be shown in Sec. III.

Fig. 9.

Load current with several crossing points around zero current area

(A). ia > 0

ia
PWM A+ PWM Ava
VPN -Vd

ia < 0

ia > 0 t t t
VPN + Vd

Vref,N

Dap sgn(ia)
Fig. 8.

t t

(B). ia < 0 Terminal voltage and PWM control signals without dead time

C. Freewheeling current polarity detection for current with multiple zero-crossing points Under some conditions, e.g. small inductor of load or low switching frequency, the output current polarity changes very quickly in the zero crossing area. There may be a few zero crossing points as shown in Fig. 9. To deal with such ambiguous situation, the concept of average current is used as an assistance index for the judgment of current polarity. Noting no real average value of load current is calculated. Once the time period between

IV. EXPERIMENTAL RESULTS Fig. 10 shows the experimental set up, and the switching frequency is 10 kHz. As shown in Fig. 10, a three-phase induction motor is used as the load. More details of the specifications of induction motor are shown in the Appendix. The proposed PWM generator without dead time is realized by using FPGA. The current polarity is detected by the proposed detection circuit. As shown in Fig. 10, only one power source is required for the proposed detection circuit. Fig. 11 shows the flow chart of the PWM generator without dead time. P cell control signal is generated as the current polarity is positive. Moreover, N cell is switched on and off when current polarity is negative. Fig. 12 shows the details of FPGA implementation of the proposed dead-time elimination method. The polarity of freewheeling current is detected regularly with a sampling frequency which is higher than the switching frequency to reduce the detection error. Fig. 13 shows experimental results of current, PWM control signals and the detected polarity. As shown in Fig. 13, the proposed method can detect the polarity effectively and the PWM control signals dont require any dead time. In order to further confirm the proposed current polarity detection circuit and dead-time elimination PWM technique in the vicinity of zero crossing point of current, Fig. 14 illustrates the experimental results which reflect the scenario

86

shown in Fig. 8. As shown in Fig. 14 (A), the current polarity can be detected accurately as the current go through zero from positive value. Similar results can be derived as the current go through zero from negative value as demonstrated in Fig. 14 (B). These experimental results fully support the effectiveness of the proposed current polarity detection circuit and dead-time elimination PWM technique. Since the dead time for the presented method is eliminated, the current distortion associated with dead time can be removed as demonstrated in Fig. 15, Fig. 16 and Fig. 17 as modulation index = 0.2, 0.5 and 1.0, respectively. Comparing Fig. 15 (A) with Fig. 15 (B) for modulation index = 0.2, the proposed method indeed provides significant improvement to the current distortion caused by dead time. Similar results can be derived as modulation index increases as illustrated in Fig. 16 and Fig. 17.
P
+15 V MOS FET Driver (L6385)

Fig. 12. FPGA implementation of proposed dead-time elimination scheme

A+

Da+

B+
+15 V MOS FET Driver (L6385)

Db+

C+
+15 V MOS FET Driver (L6385)

Dc+

VPN

va
ADa-

vb
BDb-

vc
CDc190 k 10 k

ic

190 k

10 k

PWM A+ PWM A-

PWM B+ PWM B-

PWM C+ PWM C -

ia

ib

IM
vc/k
VPN/k
Comparison Circuit

vb/k VPN/k va/k


N
Comparison Circuit

+15 V

VPN/k

Comparison Circuit

Dbp
+15 V

Dbn

Dcp
PWM A+ PWM A + PWM B PWM B+ PWM C PWM C

Dcn

Dap Dan
CLK

FPGA

Fig. 10. Experimental system

Fig. 13. Experimental results, Ch 1 = ia, Ch 2 = sgn (ia), Ch 3 = PWM A-, Ch 4 = PWM A+

1 tm (1 D )ts ? 2

1 tm (1 D )ts ? 2

Fig. 11. Flow chart of the implementation (A phase)

(A) Ch 1 = ia, Ch 2 = PWM A-, Ch 3 =Dan, Ch 4 = sgn (ia)

87

(B) Ch 1 = ia, Ch 2 = PWM A+, Ch 3 =Dap, Ch 4 = sgn (ia) Fig. 14. Transient state of phase current and related signals

(A). without proposed method, THD = 3.82 %

(A). without proposed method, THD = 8.66 %

(B). with proposed method, THD = 1.29 % Fig. 16. Measured current, modulation index = 0.5

(B). with proposed method, THD = 2.56 % Fig. 15. Measured current, modulation index = 0.2

(A). without proposed method, THD = 1.88 %

88

10 9 8 7 6 5 4 3 2 1 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Modulation index, m

THD (%)

Fig. 19. Measured current THD

(B). with proposed method, THD = 0.7 % Fig. 17. Measured current, modulation index = 1.0

Fig. 18 shows the measured load current with several crossing points around zero current area while reduce switching frequency to 2 kHz. As shown in Fig. 18, there are a few zero crossing points in the zero crossing area since the output current polarity changes very quickly. Based upon the concept of average current, once the time period between PWM off and zero crossing point is less greater than 0.5(1D)ts, the average current becomes negative and the current polarity is changed as demonstrated in Fig. 18. Therefore, the presented circuit for dead-time elimination circuit and method are indeed effective. Fig. 19 shows the measured current THD results of the proposed dead-time elimination PWM method. The related current THD for conventional PWM method with dead time = 3 sec is also included in Fig. 19 for comparison. As shown in Fig. 19, the current THD for the proposed method is indeed significantly reduced and confirming the advantages of the method.

V. CONCLUSION The contributions of this paper include: Propose a current polarity detection circuit which requires one power source only for inverter Present the PWM control method without dead time based upon the proposed current polarity detection circuit Present an average current concept for current polarity detection with large current ripple Confirmation of the effectiveness of the proposed detection circuit and PWM control without dead time The current distortion caused by dead time can be removed by using the proposed method. The proposed detection circuit can be easily incorporated into the inverter hardware. APPENDIX : Specifications of induction motor Three-phase, 60Hz, 4 poles, 220 V, 3.5 A, 1 HP. REFERENCES
[1] [2] T. J. Summers and R. E. Betz, Dead-time issues in predictive current control, IEEE Trans. on Ind. Appl., Vol. 40, No. 3, pp. 835-844, 2004. Y. S. Lai and F. S. Shyu, Optimal common-mode voltage reduction PWM technique for inverter control with consideration of the deadtime effects-part I: basic development, IEEE Trans. on Ind. Appl., Vol. 40, No. 6, pp. 1605-1612, 2004. B. B Lazhar, On the compensation of dead time and zero-current crossing for a PWM-inverter-controlled AC servo drive, IEEE Trans. on Ind. Electron., Vol. 51, No. 5, pp. 1113-1118, 2004. N. Urasaki, T. Senjyu, K. Uezatoand T. Funabashi, Adaptive deadtime compensation strategy for permanent magnet synchronous motor drive, IEEE Trans. on Energy Conversion, Vol. 22, No. 2, pp. 271280, 2007. H. Zhao, Q. M. J. Wu and A. Kawamura, An accurate approach of nonlinearity compensation for VSI inverter output voltage, IEEE Trans. on Power Electron., Vol. 19, No. 4, pp. 1029-1035, 2004. H. S. Kim, H. T. Moon and M. J. Youn, On-line dead-time compensation method using disturbance observer, IEEE Trans. on Power Electron., Vol. 18, No. 6, pp. 1336-1345, 2003. Cichowski and J. Nieznanski, Self-tuning dead-time compensation method for voltage-source inverters, IEEE Power Electronics Letters, Vol. 3, No. 2, pp. 72-75, 2005. J. W. Choi and S. K. Sul, Inverter output voltage synthesis using novel dead time compensation, IEEE Trans. on Power Electron., Vol. 11, No. 2, pp. 221-227, 1996. S. Y. Kim and S. Y. Park, Compensation of dead-time effects based on adaptive harmonic filtering in the vector-controlled AC motor drives, IEEE Trans. on Ind. Electron., Vol. 54, No 3,pp. 1768-1777, 2007.

[3] [4]

[5] [6] [7] [8] [9] Fig. 18. Measured load current with several crossing points around zero current area, Ch1: ia, Ch2: PWMa, Ch3: Dan, Ch4: sgn(ia,avg)

89

[10]

[11] [12]

[13]

[14]

T. Hoshino, J. I. Itoh and T. Kaneko, Dead-time voltage error correction with parallel disturbance observers for high performance V/f control, Conference Record of the IEEE IAS, pp. 2038-2044, 2007. C. Attaianese and G. Tomasso, Predictive compensation of deadtime effects in VSI feeding induction motors, IEEE Trans. on Ind. Appl., Vol. 37, No. 3, pp. 856-863, 2001. S. Bolognani, L. Peretti and M. Zigliotto, Repetitive-control-based self-commissioning procedure for inverter nonidealities compensation, IEEE Trans. on Ind. Appl., Vol. 44, No. 5, pp. 15871596, 2008. B. Zhang, A. Q. Huang, B. Chen and Y. F. Liu, A new generation emitter turn-off (ETO) thyristor to reduce harmonics in the high power PWM voltage source converters, IEEE IPEMC, Vol. 1, pp. 327-331, 2004. B. Zhang, A. Q. Huang and B. Chen, A novel IGBT gate driver to eliminate the dead-time effect, Conference Record of the IAS, Vol. 2, pp. 913-917, 2005.

[15] [16] [17] [18] [19] [20]

L. Chen and F. Z. Peng, Dead-time elimination for voltage source inverters, IEEE Trans. on Power Electron., Vol. 23, No. 2, pp. 574580, 2008. J. S. Choi, J. Y. Yoo, S. W. Lim and Y. S. Kim, A novel dead time minimization algorithm of the PWM inverter, Conference Record of the IEEE IAS, Vol. 4, pp. 2188-2193, 1999. C. Attaianese and G. Tomasso, Low losses modulation of PWMrectifiers, in Proc. of IEEE APEC, Vol. 1, pp. 497-502, 2002. C. Attaianese, V. Nardi and G. Tomasso, A novel SVM strategy for VSI dead-time-effect reduction, IEEE Trans. on Ind. Appl., Vol. 41, No. 6, pp. 1667-1674, 2005. C. Attaianese, V. Nardi and G. Tomasso, THD and Power Losses Optimization by Means of Variable Frequency Space Vector Modulation, in Proc. of IEEE PESC, pp. 962-968, 2005. K. M. Cho, W. S. Oh, Y. T. Kim and H. J. Kim, A new switching strategy for pulse width modulation (PWM) power converters, IEEE Trans. on Ind. Electron., Vol. 54, No 1, pp. 330-337, 2007.

90

You might also like