You are on page 1of 10

2828

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

An Alternative Energy Recovery Clamp Circuit for Full-Bridge PWM Converters With Wide Ranges of Input Voltage
Honnyong Cha, Lihua Chen, Rongjun Ding, Qingsong Tang, and Fang Zheng Peng, Fellow, IEEE
AbstractA full-bridge dcdc converter employing a diode rectier in the output experiences a severe voltage overshoot and oscillation problem across the diode rectier caused by interaction between junction capacitance of the rectier diode and leakage inductance of the transformer. The pronounced reverse-recovery current of high-power diodes signicantly contributes to these issues by increasing power loss and voltage overshoot. Conventional energy recovery clamping circuits suffer from high voltage overshoot if the converter input voltage is wide. In this paper, a novel energy recovery clamp circuit is proposed to overcome this problem. The proposed circuit requires neither active switches nor lossy components. Therefore, the proposed circuit is very promising in high-voltage and high-power applications. Performance of the proposed circuit is veried both theoretically and experimentally with a 70-kW dcdc converter. Index TermsDiode rectier, energy recovery, snubber circuit, voltage oscillation.

I. INTRODUCTION

ULL-BRIDGE pulsewidth-modulated (PWM) dcdc converters have been widely used in high-power and highvoltage dcdc converters because they have several advantages over resonant converters. However, a full-bridge dcdc converter employing a diode rectier in the output experiences severe voltage overshoot and oscillation across the diode rectier because the rectier diode is located between two current sources, i.e., transformer leakage inductance and the output lter inductor [1][3]. Therefore, it increases the diode voltage rating and cost, and causes EMI problems. As the output voltage of the dcdc converter increases, higher voltage diodes are required. However, the use of higher voltage diodes increases power loss and voltage overshoot in the diodes because higher voltage diodes have poor recovery characteristics. In order to reduce voltage spike in rectier diodes, several techniques have previously been proposed. The conventional method is the use of a resistorcapacitordiode (RCD) snubber circuit, as shown in Fig. 1(a) [1]. However, power loss in the

Fig. 1. Conventional snubber circuits used in the PWM dcdc converter. (a) RCD clamped snubber circuit. (b) Active-clamp circuit.

Fig. 2.

DCDC converter using energy recovery clamp circuit.

Manuscript received February 17, 2008; revised May 15, 2008. Current version published December 9, 2008. Recommended for publication by Associate Editor Y.-F. Liu. H. Cha, L. Chen and F. Z. Peng are with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI 48824 USA (e-mail: chahonny@egr.msu.edu; chenlih2@msu.edu; fzpeng@msu.edu). R. Ding and Q. Tang are with Zhuzhou Electric Locomotive Research Institute (ZELRI), Zhuzhou 412001, China (e-mail: dingrj@teg.cn; tangq@ egr.msu.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2008.2003131

snubber resistor Rs is very high as the output power increases. As a result, it degrades system efciency. The active clamp method shown in Fig. 1(b) can solve the efciency degradation problem and the voltage overshoot can be clamped, but it increases system complexity and degrades system reliability because an additional gate drive signal is required to control switch Qs [2]. Therefore, it is not desirable in high-power applications, either. To overcome the aforementioned problems, several energy recovery clamp circuits (ERCCs) have been proposed recently [4][11]. Fig. 2 shows one example of an ERCC employed in

0885-8993/$25.00 2008 IEEE


Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS

2829

Fig. 3.

ERCC modied from the circuit proposed in [6].

a PWM dcdc converter [6]. However, the voltage stress across rectier diodes in Fig. 2 could be very high for PWM converters with wide ranges of input voltage, especially when the duty cycle is less than 0.5. The converter circuit in [12] used a capacitor connected in series with the transformer to eliminate the voltage oscillation problem in the secondary diode rectier and showed good performance. However, this method is also not desirable in high power applications due to the series connection of the bulky capacitor. This paper proposes a novel ERCC that overcomes the drawbacks of the previously proposed circuit. The proposed circuit employs a simple auxiliary circuit in which neither lossy components nor active switches are used. Therefore, the efciency and reliability of the dcdc converter can be improved with this proposed ERCC. In Section II, several previous ERCCs are reviewed and their associated problems are pointed out in detail. In Section III, a novel ERCC is proposed and its principle operation is described in detail. The simulation and experimental results of the proposed ERCC is shown in Section IV. Performance of the proposed ERCC is veried by applying it to a 70-kW PWM dcdc converter.

II. REVIEW OF PREVIOUSLY PROPOSED ERCC Fig. 3(a) shows an ERCC modied from the circuit shown in Fig. 2. To achieve high output voltage, the transformer secondary winding is split into two windings. Two rectier bridges are used and their outputs are connected in series. With this conguration, each bridge needs to sustain only one-half of the output voltage. In this paper, the transformer turns number is set to 6:7:7 (Np :Ns1 :Ns2 ) by considering the duty cycle loss caused by transformer leakage inductance Llk and others. Llk is the transformer leakage inductance reected to the secondary side of the transformer. The operation of this circuit is the same as the one shown in Fig. 2. Fig. 3(b) depicts the peak voltage across the rectier diodes, Vrec pk , without considering diode reverse recovery current and with the assumption that snubber capacitors Cs1 and Cs2 are much bigger than diode junction capacitance Cj . With this assumption, Vrec pk can be expressed [6] Vo Vo = 2Vsec = (2 D)Vsec 2 2 (1) where Vin is the input voltage of the dcdc converter, n is the transformer turns ratio [n = (Ns1 /Np ) = (Ns2 /Np )], Vsec Vrec
pk

= 2 Vsec

Vo 2

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

2830

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 4.

ERCC modied from the circuit proposed in [8] with the insertion of snubber resistors.

is voltage in the transformer secondary winding (=nVin ), Vo is output voltage, and D is the duty cycle of the converter (=(1/2) (Vo /Vsec )). Fig. 3(c) shows the Vrec pk as D changes. In this paper, Vin changes from 333 to 666 V and Vo is regulated to 750 V. With this input voltage range, the minimum duty cycle can be determined as Dm in = Vo /2 750/2 0.483. = Vsec 7/6 666
pk

capacitor. The total power loss in Rs1 and Rs2 is calculated as P = PR s1 + PR s2 = 2 (Vrec
pk

Vo)2

Rs

=2

(Vrec

pk

2DVsec)2 Rs (4)

(2)

From (1) and (2), Vrec Vrec

can be calculated as

7 666 = 1180 V. 6 (3) Considering the reverse recovery current in the rectier diodes, the voltage stress in diodes would be easily higher than 1200 V. Thus, we cannot use standard 1200 V diodes in this case. The use of higher voltage diodes increases power loss and voltage overshoot across diodes because higher voltage diodes have poor recovery characteristics. Therefore, the ERCC shown in Fig. 3(a) is not applicable to the system described in this paper, although it has the advantages of resetting circulating current in the primary side and achieves zero-voltage and zero-current switching (ZVZCS) in switching devices using the phase shift PWM control method [6]. Fig. 4 shows another example of an ERCC modied from the circuit shown in [8]. The circuit in [8] works only when Vsec is less than Vo (i.e., D > 0.5) and the Vrec pk is clamped to Vo . However, when Vsec is higher than Vo (i.e., D < 0.5), this circuit does not work because a huge current will ow through snubber diodes, Ds1 and Ds2 , eventually destroying them. One possible way is to insert additional snubber resistors Rs1 and Rs2 , as shown in the dashed box in Fig. 4. By inserting Rs1 and Rs2 in the discharging path of snubber capacitors Cs1 and Cs2 , a portion of energy stored in Llk is dissipated in Rs1 and Rs2 , and the rest of the energy can be transferred to the output
pk

= (2 D)Vsec = (2 0.483)

where Rs = Rs1 = Rs2 . Compared with conventional RCD snubber circuits, such as the one shown in Fig. 1(a), the power loss in Rs1 and Rs2 of Fig. 4 can be reduced signicantly because the voltage across Rs1 and Rs2 can be reduced a lot. The power losses in Rs1 and Rs2 , however, are not negligible when D varies in a wide range. Therefore, the ERCC shown in Fig. 4 also suffers from the efciency degradation problem and is not applicable in the system discussed in this paper. III. PRINCIPLE OPERATION OF THE PROPOSED ERCC The two snubber circuits discussed in Figs. 3 and 4 have some limitations and are not desirable for systems with wide ranges of input voltage, especially when D < 0.5. Fig. 5 shows the ERCC proposed in this paper. The transformer secondary current IL l k (t) and diode voltage Vrec (t) waveforms are sketched in Fig. 6. The output lter inductor Lo is assumed big enough, and thus Io can be modeled as constant. To control the output voltage, either duty cycle control or phase shift PWM control can be used. In this paper, the duty cycle control method is used. The operational modes of the proposed ERCC are explained as follows and are shown in Fig. 7. For the sake of simplicity, only the diode rectier located at the bottom is considered and analyzed because the top and bottom rectiers operate in the same manner. Mode 1 (to ): S1 S4 turned off and rectier diodes are in freewheeling period. Vsec remains zero. D1 D4 are ON and each diode carries Io /2. Mode 2 (to t1 ): S1 and S4 turn on. Vsec changes from zero to nVin and transformer secondary current builds up linearly with the slope of nVin /Llk until it reaches Io . The current

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS

2831

Fig. 5.

Conguration of the proposed ERCC.

Mode 5 (t3 t4 ): When Vrec reaches Vo at t3 , Ds1 starts conducting and there is another resonance between Cs1 and Llk . Because Cs1 is much bigger than Cj , the current owing through Cj can be ignored in this mode analysis. Cs11 is added to minimize circuit stray inductance in the snubber path Cs1 Ds1 Cs11 , and can be assumed large enough because it is connected in parallel with the output capacitor. During this mode, Vrec and IL l k are expressed as (7) and (8) with the initial conditions Vrec (0) = Vo , IL l k (0) = Ip . Ip is the current at t = t3 and can be calculated from (5) and (6) Vrec (t) = Vo + (nVin Vo ) [1 cos(wd t)] +
Fig. 6. Key waveforms of the proposed ERCC.

Zd Zc

(IR Zc )2 + 2nVin Vo Vo2 sin(wd t) nVin Vo sin(wd t) Zd

(7)

IL l k (t) = Io + in D1 and D4 increases, while the current in D2 and D3 decreases in this mode. Mode 3 (t1 t2 ): Reverse recovery period of D2 and D3 . The current in D1 and D4 builds up with the same slope of nVin /Llk until D2 and D3 turn off at t2 . At t = t2 , the current in Llk becomes Io + 2Irr , where Irr is the reverse recovery current of the rectier diode. Until this mode, Vrec remains zero because D2 and D3 are still ON (conducting). Mode 4 (t2 t3 ): D2 and D3 snap off at t2 and its junction capacitors Cj start resonance with Llk . During this mode, Vrec and IL l k are expressed as follows with the initial conditions Vrec (0) = 0, IL l k (0) = Io + 2Irr : Vrec (t) =nVin [1 cos(wo t)] + (IR Zc ) sin(wo t) IL l k (t) =Io + where Zc = nVin sin(wo t) + IR cos(wo t) Zc Llk 2Cj , IR = 2Irr (5) (6) +

(IR Zc )2 + 2nVin Vo Vo2 cos(wd t) Zc

(8)

where Zc = Llk /2Cj , Zd = Llk /Cs1 , and wd = 1/ Llk Cs1 . At t = t4 , Vrec (t) reaches its peak value Vrec pk because IL l k (t) becomes equal to Io at this point. From (7) and (8), Vrec pk can be derived as Vrec
pk

= nVin + (nVin Vo )2 + Llk 2 2Cj I + (2nVin Vo Vo2 ). Cs1 R Cs1 (9)

Vo can be expressed as Vo = 2 D nVin . (10)

Llk /2Cj , wo = 1/

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

2832

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 7.

Operational mode analysis of the proposed ERCC.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS

2833

Thus, there is a 50% reduction in Vrec pk by using the proposed ERCC, which enables the use of low-voltage diodes and leads to higher efciency of the dcdc converter. Although the proposed ERCC has higher voltage spike when D > (2/3), it does not degrade the performance of the proposed ERCC because the diode voltage rating is determined with maximum input voltage or minimum duty cycle of the converter. In other words, the increased voltage spike when D > (2/3) is still within the range of the diode voltage rating. IV. SIMULATION AND EXPERIMENTAL RESULTS
Fig. 8. Comparison of V re c
pk

as a function of D.

Substituting (10) into (9) yields Vrec +


pk

= nVin Llk 2 2Cj IR + (nVin )2 4D(1 D). Cs1 Cs1 (11)

[nVin (1 2D)]2 +

Mode 6 (t4 t5 ): When IL l k is equal to Io at t4 , Ds1 stops conducting and there is a resonance between Llk and Cj . This resonance is similar to that of mode 4. During this mode, Vrec and IL l k starts decaying with oscillation, and nally, converges to nVin and Io , respectively. The voltage in Cs1 is kept constant to VC S 1 during this mode. Mode 7 (t5 t6 ): S1 and S4 turn off at t5 . IL l k and Vrec start decreasing. Mode 8 (t6 t7 ): Vrec is equal to VC S 1 at t6 and Dh1 starts conducting at this point. Cs1 can be discharged through Dh1 and supplies a portion of the load current Io . VC S 1 is fully discharged at t7 and D1 D4 turn on and start freewheeling after t7 . The operational mode analysis shown before is applied to the condition D < 0.5 (i.e., Vsec > Vo ). For D > 0.5, Vrec pk (=VC s 1 + Vo ) is almost equal to Vo because the current in the transformer leakage inductance is not sufcient to charge Cs1 . From the results mentioned earlier, Vrec pk can be expressed as (12) and (13) for D < 0.5 and D > 0.5, respectively. It should be pointed out that reverse recovery current of the rectier diode is not included in (12) and (13) for the sake of simplicity Vrec Vrec
pk pk

= 2(Vsec Vo ) + Vo = 2(1 D)Vsec (D < 0.5) (12) Vo = 2

Vo = 2DVsec (D > 0.5). (13) 2 Using (12) and (13), Vrec pk of the proposed ERCC is plotted in Fig. 8 as a function of D with Vsec and Vo . Vrec pk in Fig. 3(a) is plotted again for comparison with the proposed ERCC. As shown in Fig. 8, Vrec pk is clearly reduced by using the proposed ERCC within the duty cycle range of 0 < D < (2/3). When D = 0.5, for example, Vrec pk of the proposed ERCC is Vsec (or Vo ) while Vrec pk of Fig. 3(a) is 1.5 Vsec (or 1.5 Vo ).

A 70-kW prototype dcdc converter employing the proposed ERCC has been built and tested to verify the principle of operation and is compared with simulation results. Table I shows operational conditions and circuit parameters of the dcdc converter developed in this paper. In this paper, the two output inductors, Lo , are coupled together to minimize inductor size. The interleaved winding method is used in the transformer winding to minimize leakage inductance and copper loss. Fig. 9 shows the simulation results of the dcdc converter when D = 0.483 and 0.8, respectively. The simulation waveforms shown in Fig. 9 are consistent with theoretical ones shown in Fig. 6. When D > 0.5, Vrec pk is almost clamped to Vo as expected because the current in Llk is not sufcient to charge snubber capacitors Cs1 and Cs2 . Fig. 10(a) shows Vrec measured without snubber circuits under the test conditions of Vin = 328 V, Vo = 374 V, and Po = 14 kW. Without the snubber circuits, Vrec pk was increased to 1100 V when transformer secondary voltage Vsec was 328 (7/6) 383 V. Vrec pk was almost 2.9 times that of Vsec because the reverse recovery currents of the rectier diodes contribute signicantly to this voltage overshoot. Fig. 10(b) shows Vrec measured with the proposed ERCC under the same test conditions mentioned before. As shown in Fig. 10(b), Vrec pk was well clamped to almost 1.3 times that of Vsec with the proposed ERCC. Fig. 11(a) shows the experimental waveforms of the transformer primary current and Vrec using the proposed ERCC under the worst case conditions of Vin = 666 V, Vo = 750 V, D = 0.483, and Po = 70 kW. Due to the physical layout of the secondary busbar, the transformer primary current is measured instead of the secondary. Fig. 11(b) shows the expanded waveforms of Fig. 11(a). Vrec pk is effectively clamped to almost 1000 V. The current and voltage waveforms in Fig. 11(b) are compatible to those of theoretical waveforms shown in Fig. 6 and simulation waveforms shown in Fig. 9(a). Fig. 12 shows the experimental waveforms of the transformer primary current and Vrec using the proposed ERCC under the test conditions of Vin = 400 V, Vo = 750 V, D = 0.8, and Po = 70 kW. Vrec pk is almost clamped to Vo as expected and is close to the simulation results shown in Fig. 9(b). Fig. 13 shows the zoom in waveforms of transformer primary current and Vrec when Vin = 600 V, Vo = 670 V, D = 0.48, and Po = 50 kW to compare the performance of the proposed ERCC with the ERCC in Fig. 3(a). As shown in Fig. 13, Vrec pk was decreased from 1060 to 850 V with the proposed ERCC, which

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

2834

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

TABLE I OPERATIONAL CONDITIONS AND CIRCUIT PARAMETERS OF DCDC CONVERTER

Fig. 9.

Simulation waveforms of dcdc converter with the proposed ERCC. (a) D = 0.483. (b) D = 0.8.

Fig. 10.

Experimental waveforms measured with and without snubber circuit. (a) Without snubber circuit. (b) With proposed ERCC.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS

2835

Fig. 11. Experimental waveforms using proposed ERCC when D = 0.483. Transformer primary current (top) and V re c (bottom). (a) Waveforms with proposed ERCC. (b) Zoom-in waveforms of (a).

Fig. 12. Experimental waveforms using the proposed ERCC when D = 0.8. Transformer primary current (top) and V re c (bottom). (a) Waveforms with the proposed ERCC. (b) Zoom-in waveforms of (a).

Fig. 13.

Comparison of the proposed ERCC with Fig. 3(a). (a) ERCC in Fig. 3(a). (b) Proposed ERCC.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

2836

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

was almost the same as in Fig. 3(a) when Vin is low and slightly improved as Vin moves toward maximum value as expected. In the test, a digital power meter (YOKOGAWA, WT1600) was used to measure the input and output power, and the output power was 50 kW. V. CONCLUSION This paper introduced a novel ERCC for PWM dcdc converters with wide ranges of input voltage. The limitations and drawbacks of previously proposed ERCCs have been pointed out. Detailed analysis has been presented, and performance of the proposed ERCC was compared with previously proposed ERCCs. A 70-kW prototype dcdc converter employing the proposed ERCC has been built and tested to verify the principle of operation. The proposed ERCC consists of two small capacitors and two diodes in each bridge. Neither lossy components nor additional active switches are used to clamp diode voltage. Therefore, the efciency and reliability of the dcdc converter can be improved by using the proposed ERCC. The proposed ERCC is very promising for high-voltage and high-power dcdc converters with wide ranges of input voltage. REFERENCES
[1] L. H. Mweene, C. A. Wright, and M. F. Schlecht, A 1 kW 500 kHz front-end converter for a distributed power supply system, IEEE Trans. Power Electron., vol. 6, no. 3, pp. 398407, Jul. 1991. [2] J. A. Sabate, V. Vlatkovic, R. B. Ridley, and F. C. Lee, High-voltage, highpower, ZVS, full-bridge PWM converter employing an active snubber, in Proc. IEEE APEC, 1991, pp. 158163. [3] S. Lin and C. Chen, Analysis and design for RCD clamped snubber used in output rectier of phase-shift full bridge-bridge ZVS converters, IEEE Trans. Ind. Electron., vol. 45, no. 2, pp. 358359, Apr. 1998. [4] E. S. Kim, K. Y. Joe, M. H. Kye, Y. H. Kim, and B. D. Yoon, An improved soft switching PWM FB dc/dc converter for reducing conduction losses, IEEE Trans. Power Electron., vol. 14, no. 2, pp. 258264, Mar. 1999. [5] J. G. Cho, J. W. Baek, D. W. Yoo, H. S. Lee, and G. H. Rim, Novel zero-voltage and zero-current-switching (ZVZCS) full bridge PWM converter using transformer auxiliary winding, IEEE Trans. Power Electron., vol. 15, pp. 250257, Mar. 2000. [6] J. G. Cho, J. W. Baek, C. Y. Jeong, and G. H. Rim, Novel zero-voltage and zero-current-switching (ZVZCS) full bridge PWM converter using a simple auxiliary circuit, IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 1520, Jan./Feb. 1999. [7] E. S. Kim and Y. H. Kim, A ZVZCS PWM FB dc/dc converter using a modied energy-recovery snubber, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 11201127, Oct. 2002. [8] A. Bendre, S. Norris, D. Divan, I. Wallace, and R. W. Gascoigne, New high power dcdc converter with loss limited switching and lossless secondary clamp, IEEE Trans. Power Electron., vol. 18, no. 4, pp. 1020 1027, Jul. 2003. [9] T. T. Song, N. Huang, and A. Ioinovici, A family of zero-voltage and zerocurrent-switching (ZVZCS) three-level dcdc converters with secondaryassisted regenerative passive snubber, IEEE Trans. Circuits Syst., vol. 52, no. 11, pp. 24732481, Nov. 2005. [10] M. Ilic and D. Maksimovic, Phase-shifted full bridge dcdc converter with energy recovery clamp and reduced circulating current, in Proc. IEEE Appl. Power Electron. Conf. Exp., 2007, Feb. 2007, pp. 969 975. [11] X. Wu, X. Xie, C. Zhao, Z. Qian, and R. Zhao, Low voltage and current stress ZVZCS full bridge dcdc converter using center tapped rectier reset, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 14701477, Mar. 2008. [12] K. B. Park, C. E. Kim, G. W. Moon, and M. J. Yoon, Voltage oscillation reduction techniques for phase-shift full-bridge converter, IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 27792790, Oct. 2007.

Fig. 14.

Measured and theoretical results of V re c

pk

versus C s 1 .

Fig. 15.

Comparison of efciency.

is almost a 30% reduction in Vrec pk . In addition to voltage reduction in Vrec pk , the peak current in the transformer primary (secondary) winding was increased with the ERCC in Fig. 3(a) because snubber capacitors Cs1 and Cs2 start charging when Vrec reaches Vo /2 instead of Vo . Therefore, it will increase conduction loss in the transformer and insulated gate bipolar transistor (IGBT) that results in the decrease of system efciency (see Fig. 15). Fig. 14 shows the measured Vrec pk as Cs1 (or Cs2 ) changes from 10 to 600 nF under the test conditions of Vin = 450 V, Vo = 510 V, and Io = 55 A. The measured Vrec pk is compared with the theoretical results plotted using (11). The measured Vrec pk is very close to the theoretical value. Vrec pk is inversely proportional to snubber capacitance Cs1 . In this paper, a 100-nF capacitor is selected for Cs1 and Cs2 because a larger than necessary capacitor will increase current in the transformer and IGBT. Therefore, converter efciency will be decreased. Fig. 15 shows the measured efciency of dcdc converter using the proposed ERCC and is compared with the efciency measured in Fig. 3(a). The efciency of the proposed converter

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.

CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS

2837

Honnyong Cha received the B.S. and M.S. degrees in electrical engineering from Kyungpook National University, Taegu, Korea, in 1999 and 2001, respectively. He is currently working toward the Ph.D. degree at Michigan State University, East Lansing. From 2001 to 2003, he was a Research Engineer with Power System Technology (PSTEK) Company, An-san, Korea, where he was involved with the development of power electronics application systems. His current research interests include dcdc converters, dcac inverters, and hybrid vehicles.

Qingsong Tang was born in HuBei Province, China, in 1974. He received the B.S. and M.S. degrees in electrical engineering from Beijing Jiaotong University, Beijing, China, in 1997 and 2007, respectively. He is currently a Research Engineer with Zhuzhou Electric Locomotive Research Institute (ZELRI), Zhuzhou, China. Since January 2006, he has been a Visiting Scholar at Michigan State University, East Lansing. His current research interests include power converter circuits, especially in soft-switching technology, motor drives, and DSP-based power electronics control systems.

Lihua Chen received the B.S. and M.S. degrees in electrical engineering from Changchun University of Science and Technology, Changchun, China, in 1993 and 1996, respectively. He is currently working toward the Ph.D. degree at the Department of Electrical and Computer Engineering, Michigan State University, East Lansing. From 1996 to 1999, he was an Assistant Professor with Changchun University of Science and Technology. From 1999 to 2002, he was with Argonne National Laboratory, Argonne, IL, as a Visiting Scientist. His current research interests include high-power converters and inverters, intelligent gate drives, and high-temperature superconductors and their applications.

Rongjun Ding was born in Jiangsu Province, China, in 1961. He received the B.S. degree in electrical engineering from Southwest Jiaotong University, Sichuan, China, in 1984, and the M.S. degree in electrical engineering from the Central South University, Changsha, China, in 1998. He is currently a Professor with Zhuzhou Electric Locomotive Research Institute (ZELRI), Zhuzhou, China. Since 1988, he has been engaged in the research of ac dive systems for electric locomotives, especially in control technology and converter design.

Fang Zheng Peng (M92SM96F05) received the B.S. degree in electrical engineering from Wuhan University, Wuhan, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from Nagaoka University of Technology, Nagaoka, Japan, in 1987 and 1990, respectively. From 1990 to 1992, he was a Research Scientist with Toyo Electric Manufacturing Company, Ltd., where he was engaged in research and development of active power lters, exible ac transmission systems (FACTS) applications, and motor drives. From 1992 to 1994, he was with Tokyo Institute of Technology, Tokyo, Japan, as a Research Assistant Professor, where he initiated a multilevel inverter program for FACTS applications and a speed-sensorless vector control project. From 1994 to 2000, he was with Oak Ridge National Laboratory (ORNL), from 1994 to 1997, he was a Research Assistant Professor at the University of Tennessee, Knoxville, where he was also a staff member, and from 1997 to 2000, he was the Lead (principal) Scientist of the Power Electronics and Electric Machinery Research Center, ORNL. In 2000, he joined Michigan State University, East Lansing, as an Associate Professor, and he is currently a Professor in the Department of Electrical and Computer Engineering. He is the holder of more than ten patents. Dr. Peng was the recipient of the 1996 First Prize Paper Award and the 1995 Second Prize Paper Award of the Industrial Power Converter Committee in the IEEE/Industrial Application Society (IAS) Annual Meeting, the 1996 Advanced Technology Award of the Inventors Clubs of America, Inc., the International Hall of Fame, the 1991 First Prize Paper Award in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, and the 1990 Best Paper Award in the Transactions of the Institute of Electrical Engineers of Japan (the Promotion Award of Electrical Academy). He was an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS from 1997 to 2001, and again since 2005. He was the Chair of the Technical Committee for Rectiers and Inverters of the IEEE Power Electronics Society from 2001 to 2005.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE SAO JOAO DEL REI. Downloaded on March 2, 2009 at 10:00 from IEEE Xplore. Restrictions apply.