TEST PAPERS VLSI Spring Session 2011 Test#1 <Date: 23rd Feb, 2011> Q.

1 (8 Marks) In Original Code below, assume the module definition and declaration part is error free in all respects and so skipped. Also assume that there are no syntax mistakes in the code. a) Re-write the Verilog code in second column after applying some necessary code level optimization techniques. b) Highlight the Optimization errors or rules violated in the third column. c) On backside of the page, write the effects/ drawbacks that the original code may come across iff optimization is not performed. NOTE: Line numbers are given just for your easy reference Original Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 always@ (*) begin A< = 1b1; C< = 1b1; D< = 1b0; B< = C + D; if (~A) Y< = B + C + D; else Y< = E + C + D; case ({ B, C }) 2b 00: Y< = {D, E}; 2b 01: Y< = 2b11; 2b 11: Y< = C + D; endcase end//always 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Optimized Code Optimization Errors (Rules Violated)

Q.2 For the Verilog code given below, show the execution time and values assignment in the table. Assume all registers are of single bit each. NOTE: Line numbers at the left are given just for your easy reference. (6 Marks) 1 assign result = c ? a : b ; T a b c d e result 2 always @ ( * ) begin 3 a = 1; 4 b = a; 5 #2 c = #2 a + b; 6 d = #1 a ^ b; 7 #2 e = #1 b + c; 8 #1 b = a & b; 9 end Q.3 What is wrong with the code given below? (Just point out errors only by referring to the line numbers) (4 Marks) Note: There is no any typo error module Sum_Sub(X, Q, P, reg_Z); (Write your answer here) 2 output reg X; 3 output reg_Z; 4 input Q, P; 5 assign X = P + Q; 6 always@ (*) begin 7 assign reg_Z = Q + ~P +1; 8 end//always 9 endmodule

Test#1 <Date: 23rd Feb, 2011> Q.1 (8 Marks) In Original Code below, assume the module definition and declaration part is error free in all respects and so skipped. Also assume that there are no syntax mistakes in the code. a) Re-write the Verilog code in second column after applying some necessary code level optimization techniques. b) Highlight the Optimization errors or rules violated in the third column. c) On backside of the page, write the effects/ drawbacks that the original code may come across iff optimization is not performed. NOTE: Line numbers are given just for your easy reference 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Original Code always@ (*) begin A< = 1b1; C< = 1b1; D< = 1b0; B< = C + D; if (~A) Y< = B + C + D; else Y< = E + C + D; case ({ B, C }) 2b 00: Y< = {D, E}; 2b 01: Y< = 2b11; 2b 11: Y< = C + D; endcase end//always Optimized Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Optimization Errors (Rules Violated)

Q.2 For the Verilog code given below, show the execution time and values assignment in the table. Assume all registers are of single bit each. NOTE: Line numbers at the left are given just for your easy reference. (6 Marks) 1 assign result = c ? a : b ; T a b c d e result 2 always @ ( * ) begin 3 a = 1; 4 b = a; 5 #2 c = #2 a + b; 6 d = #1 a ^ b; 7 #2 e = #1 b + c; 8 #1 b = a & b; 9 end Q.3 What is wrong with the code given below? (Just point out errors only by referring to the line numbers) (4 Marks) Note: There is no any typo error. 1 module Sum_Sub(X, Q, P, reg_Z); (Write your answer here) 2 output reg X; 3 output reg_Z; 4 input Q, P; 5 assign X = P + Q; 6 always@ (*) begin 7 assign reg_Z = Q + ~P +1; 8 end//always 9 endmodule

Test#2 <Date: 24th Mar, 2011> Q.1 Define in 2 to 3 Lines each of the following: 1. CPLDs (with its key benefit over SPLDs) 2. Row styled FPGAs 3. Intellectual Property 4. Compiled Cells Q.2 Give at least two major differences between the following: A. Channeled gate arrays VS Channelless gate arrays B. Field Programmable Gate Arrays VS Mask Programmable Gate Arrays Q.3 What advantage(s) does it add when we Partition the Large array into identical k-macrocells? Test#2 <Date: 24th Mar, 2011> Q.1 Define in 2 to 3 Lines each of the following: 1. LUTs 2. Anti-fuse 3. The term Mask Programmable 4. SOG Q.2 Give at least two major differences between the following: A. Hard Macro VS Soft Macro B. Pre-diffused Arrays VS Pre-wired Arrays Q.3 To get rid of fixed cell-based topologies, compiled cell technique allows far more flexibility in design and portability. (Justify this statement) Test#2 <Date: 24th Mar, 2011> Q.1 Define in 2 to 3 Lines each of the following: 1. Fuse Based FPGAs 2. Reconfigurable logic 3. Mask-Level Designs 4. Mega-cells Q.2 Give at least two major differences between the following: A. Volatile FPGAs VS Non-volatile FPGAs B. Standard Cells VS Compiled Cells Q.3 Give two main drawbacks of array based programmable logic (PLAs, PALs and PROM). Also briefly suggest the possible solution for each. Test#2 <Date: 24th Mar, 2011> Q.1 Define in 2 to 3 Lines each of the following: 1. The term Mask-Programmable 2. Feed-through cells 3. IP Cores 4. Embedded Gate arrays Q.2 Give at least two major differences between the following: A. Cell Based Designs VS Array Based Designs B. Island-styled FPGAs VS Row-styled FPGAs Q.3 SOG approach has increased design density. (Reason)

Test#3 <Date: 2nd April, 2011> Q.1 What advantages does a carry Look ahead adder give over carry by-pass adder? And how? Describe with example. Q.2 Discuss carry Select adder by considering its data path given below:

Q.3 Does Polynomial Expression (1 + x2 + x3 + x5) represents a 5-bit maximal LFSR or not? Justify Q.4 How Carry Save Addition minimizes the addition time as compared to carry Propagate addition? Q.5 Implement Equality comparator at Gate level of abstraction using Verilog HDL. Test#3 <Date: 2nd April, 2011> Q.1 What advantages does a carry skip adder give over carry ripple adder? And how? Describe with example. Q.2 Discuss carry look Ahead adder by considering its data path given below:

Q.3 Does Polynomial Expression (1 + x2 + x3 + x4) represents a 5-bit maximal LFSR or not? Justify Q.4 How Carry Save Addition minimizes the addition time as compared to carry Propagate addition? Q.5 Implement Equality comparator at behavioral level of abstraction using Verilog HDL. Test#3 <Date: 2nd April, 2011> Q.1 If for each of the 4-bit groups of 32-bit addition of two numbers A and B, P =1, which adder will be the best

among Carry skip and Carry Look ahead and why? Q.2 Draw figure with brief functionality description of combined Adder/ Subtractor logic. Q.3 Assume a 4-bit magnitude Comparator that compares A & B by maintaining Carry (C) and Zero (Z) flags. Write Verilog HDL code at Behavioral Level of Abstraction to compare whether A<B, A>B or A=B. Q.4 Define Seed value, Majority function and Carry Select Adder. Q.5 What is the importance of using PG logic in various adders? Derive formula for Group PG Logic.