World of 100 Gbps The Lower Layers

100 Gigabit Ethernet

MAC
802.3 MAC Frame Structure
7 bytes
Preamble

OTU4
4 bytes 2 bytes 46 to 1500 bytes
MAC Payload

1 byte
SFD

6 bytes
Destination MAC address

6 bytes
Source MAC address

4 bytes

4 bytes
FCS

Signal Structure
IEEE Model with CAUI
(to interconnect chip devices)
Higher Layers (e.g., IP) LLC or other MAC Client MAC Reconciliation CGMII

VLAN VLAN Type/ (optional) (optional) Length

IEEE Layer Model

Higher Layers (e.g., IP) LLC or other MAC Client MAC Reconciliation CGMII 100GBase-R PCS

Signal Structure
OPU4 OH

Client (e.g.,100GE)

ODU Multiplexing
ODU OH

ODU Payload

ODU ODTU4.ts

OPU4 Payload

OPU4
OTU4 TC L1

ODU4 Multiplexing
ODU4 TCMOH
ODTU4.ts JOH

ODTU4.ts JOH

ODU (0, 1, 2, 2e, 3, 4, ex)

User Priority

C F I

VID: VLAN ID

Type/ Values > 1535 are Ethernet Types Length Values 1500 are for Length of the MAC frame with preamble/SFP and typically used with LLC/SNAP in the MAC Payload

Information Containers
ODU4 TCMOH

ODU4 PMOH

OPU4

ODU4 Path

ODTU4.ts JOH

ODU

ODU

ODTUG4
(PT=0x21)

PCS
Input Data

100GBase-R PCS

ODU4 Tandem Connection

OTU4 TC L6

ODU4 TCMOH
OTU4 Section

ODTUG4 (PT=0x21)
OPU4 OH ODU4 OH

64B/66B PCS Block Format

S Block Payload Y N C Bit Position 0 1 2 Data Block Format D0 D0D1D2D3/D4D5D6D7 01 Block Type Control Block Formats Field 10 0x1E C 0C 1C 2C 3/C4C 5C 6C 7 S 0D1D2D3/D4D5D6D7 10 0x78 10 0x4B O0D1D2D3/Z4Z 5Z 6Z 7 10 0x87 T 0C 1C 2C 3/C4C 5C 6C 7 10 0x99 D0T 1C 2C 3/C4C 5C 6C 7 10 0xAA D0D1T 2C 3/C4C 5C 6C 7 10 0xB4 D0D1D2T 3/C4C 5C 6C 7 10 0xCC D0D1D2D3/T4C 5C 6C 7 10 0xD2 D0D1D2D3/D4T 5C 6C 7 10 0xE 1 D0D1D2D3/D4D5T 6C 7 10 0xFF D0D1D2D3/D4D5D6T 7

PMA CAUI PMA PMD PMD MDI Optical Medium PMA

OTU4 OH

OPU4 Payload ODU4 Payload

OPU4 ODU4

OTU4 FEC

65 D1 C0 D1 D1 D0 D0 D0 D0 D0 D0 D0 C1 C1 D2 C2 C2 C2 D3 C3 C3 C3 C3 O0 D4 C4 C4 C4 C4 C4 D4 D4 D4 D5 C5 D6 C6 D7 C7 D7 C7 C7 C7 C7 C7 C7 C7 D6

MDI Optical Medium

OTL4.n #0

OTL4.n #1

OPSM

OTL4.n #n-1

OT Lanes

n: number of physical lanes

Tributary Slots (1.25G) for Multiplexing

Column (bytes) 1 3815 3816 3817 3824 3825 Row 1 FA OTU4 OH
39 40 41 42 79 80 1 2 39 40 1 2

39 40 41 42

OTU4 111.809974 Gbps 20 ppm PCS Lanes 0 1 2 ... 18 ... 19 0 1 2 ... 18 ... 19 PCS Lanes

OTL Type OTL4.10

OTL Nominal Bit Rate 255/227 x 9.953280 Gb/s = 11.180997 Gbps 255/227 x 24.883200 Gb/s = 27.952493 Gbps

39 40 41 42

TxD <0> CGMII Output of encoder function Sync header D0 D1

TxD <63> CGMII Input to decoder function

RxD<0>

RxD<63>

PMA 20:10

2:1

2:1

2:1

2:1

2:1

2:1

PMA 20:10 Physical Lanes CAUI SP6 10.3125 Gbps PMA 10:4 PMD Service Interface 0 1 2

OTL4.4

PSI OMFI 41 42

PCS Transmit

PCS Receive

Potential Evolution
PCS ... 18 19 PCS Lanes PMA 20:4 Physical Lanes

39 40 41 42

2:1

2:1

2:1

Output of scrambler function Transmit block

S0

S1

S2

S3

S4

S5

S6

S7

Input to descrambler function

S0

S1

S2

S3

S4

S5

S6

S7

SP2 PMD

SP5

25.78125Gbps

PSI OMFI 41 42

79 80 1 2

39 40 41 42

PMA 10:4

5:1

...

5:1

5:1

...

5:1

OTL4.4 Physical Lanes

PMD
L8 L9 L 0 L 1 L 2 L 3 SP3

PMD

5 Logical lanes:1

S0 TxB <0>

S1

S2

S3

S4

S5

S6

S7 TxB <65>

Receive block

S0 RxB<0>

S1

S2

S3

S4

S5

S6

S7 RxB<65>

L0 L1 L2

...

SP4 L 0 L 1 L 2 L 3

0 1 2 3 OTM-0.4v4

0 1 2 3 OTM-0.4v4

PSI for Multiplexing

27.952Gbps

PSI [0] [1] TS1 [2] TS2 [3]

TSO TSO

PT=0x21 RES Trib Port# Trib Port# 1 TS Occupied 0 Unallocated 1 Allocated 2 3 4 5 6 7 8 (Bits) Tributary Port# The Tributary Port# indicates the ODUj (j=0, 1, 2, 2e, 3, ex) transported in this TS; Multiple 1.25G TS can be grouped

Block Distribution and Alignment Marker Insertion

Lane Block Sync & Deskew & Alignment Marker Removal

10 Fibers
TxB <65> S7 S7 TxB <131> S7 TxB <1319> RxB<0> S0 S0 S0 RxB<65> S0 S0 RxB<1254>

100GBase-SR10
850 nm MMF 100 m in OM3 125 m in OM4

100GBase-LR4

1310 nm SMF 4*25.78 Gbps 10 km

100GBase-ER4

1310 nm SMF 4*25.78 Gbps 30 km or 40 km (engineered links)

Optics for OTU4 inter-Domain Interface similar to 100GBase-LR4 and ER4 applicable to OTU4

TS80 [81]

TSO

Trib Port#

S6

S6

S6

Additional optical implementations such as 10*10G can be considered

[255]

S5

S5

S5

S4 S4 20 PCS lanes in total S4

20 PCS lanes in total

PMA service interface

TxB <0> PCS Lane 0 PCS Lane 1

TxB <66> PCS Lane 19

TxB <1254>

PMA service interface

RxB<65>

RxB<131>

RxB<1319> PCS Lane 19

CAUI CGMII CFI CPPI FCS LLC LWDM MAC MDI PCS

100 Gbps attachment unit interface 100 Gigabit media independent interface canonical format indicator 100 Gbps parallel physical interface frame check sequence logical link control LAN wave division multiplexing media access control media dependent interface physical coding sublayer

PMA PMD RS SFD SP VLAN

physical media attachment physical media dependent reconciliation sublayer start frame delimiter skew point virtual local area network

S3

S3

S3

Frame Structure
Column (bytes) 3816 3817 3824 3825 4080 Row 1 2 3 4 ODU4 OH 14 15 16 17 1 7 8 FA OTU4 OH OPU4 OH OPU4 Payload Fixed Stu OTU4 FEC

GMP provides a generic mapping method for the justi cation of CBR client signals into OPU
Floor Minimum Nominal Nominal Ceiling 15050 15050.518 15052.325 15054.131 15055

S2

S2

S2

C8 for 100GBase-R client

JC1 JC2 JC3 C1 C9 C2 C10 C3 C11 C4 C5 C12 C13 CRC-8 D1 D6 D2 D7 C6 C14 C7 II C8 DI

S1

S1

S1

S0

S0

S0

SM, PM, and TCMi (i = 1...6)

1 TTI 2 BIP-8 3 (bytes)
MFAS Bits 678 APS/PCC Channel ODU4 Path ODU4 TCM1 ODU4 TCM2 ODU4 TCM3 ODU4 TCM4 ODU4 TCM5 ODU4 TCM6 ODU4 server layer trail Protection Scheme using the APS/PCC Channel ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/S, ODU4 SNC/N ODU4 SNC/I

PCS Lane 0 PCS Lane 1

1 2 3 4 2 3 FAS RES TCM3 GCC1 GCC2 TCM ACT TCM2 APS/PCC TCM6 TCM1 4 5 6 7 MFAS 8 9 SM TCM5 PM RES 10 11 12 13 RES FTFL EXP OPU4 OH 14 15 16 0 1 GCC0 TCM4

15 JC4 JC5 JC6 PSI PT

16 JC1 JC2 JC3 OMFI

Justi cation via GMP

JC4 JC5 JC6

RES RES RES

D3 D4 D8 D9 CRC-5

D5 D10

TSOH

10

M0

M1

M2

BIP

M4

M5

M6

BIP

Alignment markers are inserted after every 16383 66-bit blocks on each PCS lane
PCS Lane Encoding
0xC1, 0x68, 0x21, BIP3, 0x3E, 0x97, 0xDE, BIP7 0x9D, 0x71, 0x8E, BIP3, 0x62, 0x8E, 0x71, BIP7 0x59, 0x4B, 0xE8, BIP3, 0xA6, 0xB4, 0x17, BIP7 0x4D, 0x95, 0x7B, BIP3, 0xB2, 0x6A, 0x84, BIP7 0xF5, 0x07, 0x09, BIP3, 0x0A, 0xF8, 0xF6, BIP7 0xDD, 0x14, 0xC2, BIP3, 0x22, 0xEB, 0x3D, BIP7 0x9A, 0x4A, 0x26, BIP3, 0x65, 0xB5, 0xD9, BIP7 0x7B, 0x45, 0x66, BIP3, 0x84, 0xBA, 0x99, BIP7 0xA0, 0x24, 0x76, BIP3, 0x5F, 0xDB, 0x89, BIP7 0x68, 0xC9, 0xFB, BIP3, 0x97, 0x36, 0x04, BIP7

Skew Tolerance
Skew Point
SP1 SP2 SP3 SP4 SP5 SP6 At PCS Rx

2 3 4

PCS Lane
10 11 12 13 14 15 16 17 18 19

SM

Encoding
0xFD, 0x6C, 0x99, BIP3, 0x02, 0x93, 0x66, BIP7 0xB9, 0x91, 0x55, BIP3, 0x46, 0x6E, 0xAA, BIP7 0x5C, 0xB9, 0xB2, BIP3, 0xA3, 0x46, 0x4D, BIP7 0x1A, 0xF8, 0xBD, BIP3, 0xE5, 0x07, 0x42, BIP7 0x83, 0xC7, 0xCA, BIP3, 0x7C, 0x38, 0x35, BIP7 0x35, 0x36, 0xCD, BIP3, 0xCA, 0xC9, 0x32, BIP7 0xC4, 0x31, 0x4C, BIP3, 0x3B, 0xCE, 0xB3, BIP7 0xAD, 0xD6, 0xB7, BIP3, 0x52, 0x29, 0x48, BIP7 0x5F, 0x66, 0x2A, BIP3, 0xA0, 0x99, 0xD5, BIP7 0xC0, 0xF0, 0xE5, BIP3, 0x3F, 0x0F, 0x1A, BIP7

Maximum Skew
29 ns (~150 UI) 43 ns (~222 UI) 54 ns (~278 UI) 134 ns (~691 UI) 145 ns (~748 UI) 160 ns (~824 UI) 180 ns (~928 UI)

Maximum Skew Variation (10.3 GBd)

0.2 ns (~2 UI) 0.4 ns (~2 UI) 0.6 ns (~4 UI) 3.4 ns (~35 UI) 3.6 ns (~37 UI) 3.8 ns (~39 UI) 4 ns (~41 bits)

255

BEI/BIAE

BDI IAE

Mapping & Concat. Speci c

1.25G TS 1 2 3 4 5 79 80 1 2

1 0 0 0 0 0 0 0 0 0

2 0 0 0 0 0 1 1 0 0

3 0 0 0 0 0 0 0 0 0

4 0 0 0 0 0 0 0 0 0

OMFI Bits 6 5 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0

7 0 0 1 1 0 1 1 0 0

8 0 1 0 1 0 0 1 0 1

Decimal 0 1 2 3 4 78 79 0 1

31 32 Operator Speci c 63

BEI/BIAE

BDI

DAPI

TCMi

Alignment Markers

Ci II DI Di

Relative change indication Increment Indicator Decrement Indicator Ci-derived cumulative value

PM

15 16

SAPI

BEI

BDI

1 2 3 4 5 6 7 8 (bits) STAT

000 001 010 011 100 101 110 111

1 2 3 4 5 6 7 8 (bits) RES

1 2 3 4 5 6 7 8 (bits) RES

PCS Block Distribution

66b Block 2 66b Block 1

0
Round Robin 66b Block 20 66b Block 21 66b Block 0 66b Block 39 66b Block 19 PCS Lane 19 66b Block 0 66b Block 1 PCS Lane 0 PCS Lane 1

1 2 3 4 5 6 7 8 9

PT of 0x07 for 100GBase-R client

Logical Lanes
Logical Lane Markers
Used for logical lane identi cation and skew FAS Byte Values
OA1 OA1 F6 OA1 F6 OA2 28 OA2 28 OA2 LLM F6

SP Points shown in Multilane Model

LL 0 1 2 3 19 1 18 19 0 1

1 0 0 0 0 0 0 1 1 0 0

2 0 0 0 0 0 0 1 1 0 0

3 0 0 0 0 0 0 1 1 0 0

4 0 0 0 0 1 1

OA2 LLM Bits OA2 LLM Bits 5 6 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0

7 0 0 1 1 1 0 1 1 0 0

8 0 1 0 1 1 0 0 1 0 1

Decimal Decimal 0 1 2 3 19 20 238 239 0 1

Byte Distribution from OTU4 to the 20 Logical Lanes

Rotate Rotate Rotate
16305:16320 16001:16016 16289:16304
Multiple Rotations

Rotate
16017:16032 1:16 (FAS) 16033:16048 16001:16016 17:32 305:320

LL 0 LL 1 LL 19

1:16 (FAS) 17:32 305:320

321:336 337:352 625:640

16001:16016 ... 16305:16320

305:320 289:304

17:32 33:48 1:16 (FAS)

16017:16032 1:16 (FAS)

Optical

Average Optical Power

100GBase- 100GBase- 100GBaseSR10 LR4 ER4
2.4 dBm 8 dBm 2.4 dBm 9.9 dBm 4.5 dBm 4.3 dBm 4.5 dBm 10.6 dBm 2.9 dBm 2.9 dBm 4.5 dBm 20.9 dBm

100GBase-LR4 and ER4 LWDM Lane Assignments

Lane
L0 L1 L2 L3

LWDM Wavelength Range

APS BDI BEI BIAE BIP-8 DAPI EXP FAS FEC FTFL automatic protection switching backward defect indication backward error indication backward incoming alignment error bit interleaved parity-8 destination access point identi er experimental frame alignment signal forward error correction fault type and fault location GCC GMP IAE JC JOH LLM MFAS ODTU ODTUG ODU

0 0 0 0

Bytes from the OTN frame are sequentially ordered in groups of 16 bytes row by row and rotated by OTL

LLM is processed at the OTL layer

Parameter
Max Launch Power/lane Min Launch Power/lane Max Avg Rx Power/lane Min Avg Rx Power/lane

Center
1295.56 nm 1300.05 nm 1304.58 nm 1309.14 nm

Range
1294.53 to 1296.59 nm 1299.02 to 1301.09 nm 1303.54 to 1305.63 nm 1308.09 to 1310.19 nm

1295

1300

1305

1310 (nm)

General Communication Channel generic mapping procedure incoming alignment error justi cation control justi cation overhead logical lane marker multi-frame alignment signal optical channel data tributary unit optical channel data tributary unit group optical channel data unit

OH OMFI OPSM OPU OTL OTLCG OTN OTU PCC PM

overhead OPU multi-frame identi er optical physical section multilane optical channel payload unit optical channel transport lane optical transport lane carrier group optical transport network optical channel transport unit protection communication channel path monitoring

PMA PMOH PSI PT RES SAPI SM SNC SNC/I SNC/N

physical media attachment performance monitoring overhead payload structure identi er payload type reserved source access point identi er section monitoring subnetwork connection SNC protection with inherent monitoring SNC protection with non-intrusive monitoring

SNC/S STAT TC TCM TCM ACT TCMOH TS TTI

SNC protection with sublayer monitoring status tandem connection tandem connection monitoring TCM activation tandem connection monitoring overhead tributary slot trail trace identi er

To learn more, www.jdsu.com/test

Product speci cations and descriptions in this document subject to change without notice. 2011 JDS Uniphase Corporation February 2011 30162982 001 0211 100GBPS.PO.LAB.TM.AE

References: 100GE IEEE 802.3ba, and 802.1Q OTU4 ITU-T G.709, G.872, G.695, and G.959.1 Line I/F OIF IA# OIF-SFI-S and IA# OIF2008.388.00

79 80

Sync header (2-bit wide) 01: data block 10: control block

5:1

...

5:1

5:1

...

5:1

Scrambler

Descrambler

39 40 41 42

0 1 2 3

0 1 2 3

79 80 1 2

39 40

1 2

5 PCS lanes:1

Physical Lanes 0 1 2 ... 8 9 11.181Gbps

0 1 2

... 18

19

Logical Lanes

OMFI = 79 (TSOH TS80)

2 3 ODU4 OH

TSOH TS80

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

SP1

OTL4.10

...

OTU4

41 42

79 80 1 2

39 40 41 42

79 80 1 2

79 80

39 40

1 2

Sync header

Physical Lanes 0 1 2 ... 8 9 CPPI

10.3125 Gbps

Multilane Model Logical

Lanes

OTU4 0 1 2 ... 18 19

79 80 1 2

39 40 41 42

79 80 1 2

0 1 2 ... 8 9

Potential Evolution
1 FA

OTU4 OH

79 80

39 40

1 2

OMFI = 1 (TSOH TS2)

2 3 ODU4 OH

TSOH TS2

D1 D1 D1 D1 D1 D1

D2 D2 D2 D2 D2

4 1 FA OTU4 OH

PSI OMFI 41 42

D3 D3 D3 D3

Multilane Model
PCS PCS

OTM 0.4v4 (4 optical lanes)

79 80 1 2

39 40 41 42

79 80 1 2

39 40 41 42

41 42

79 80 1 2

39 40 41 42

79 80 1 2

79 80

39 40

1 2

79 80

39 40

1 2

OMFI = 0 (TSOH TS1)

2 3 ODU4 OH

TSOH TS1

D2 D2

D3 D3

41 42

79 80 1 2

39 40 41 42

79 80

D4

D5

D6 0x000_0000 C5 C6 C5 C6 C5 C6 C5 C6 C5 C6 C6 D5 D5

100 Gigabit Ethernet 103.125 Gbps 100 ppm

OTLCp

OTLCp

OTLCp

OTLCG

...

...

...

Fixed Stu

OTU4 FEC

...

...

...

Fixed Stu

OTU4 FEC

...

...

...

Fixed Stu

OTU4 FEC

4080

14 15 16 17 18

55 56 57 58

95 96 97 98

7 8

S1 S2 S3 S4 S5 S6 S7

S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7

S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7