Lecture 19 Two-stage op-amp design part 1

In this lecture:
19.1 The basic two-stage op-amp 19.2 Frequency compensation -- in theory Example Pole shifting 19.3 Frequency compensation -- in practice Simple compensation Miller compensation Reminder: the Miller effect

19.1. The basic two-stage op-amp

VDD

RD

RD vO1 Q1 NMOS Q2 NMOS vIN-

vIN+

Q3 PMOS vO2

IBIAS1

IBIAS2

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The basic two-stage op-amp structure above consists of 1. A differential amplifier stage operating in one-sided mode -- lowfrequency gain is AV1 = gmRD . where gm is set by IBIAS and VGS-VT, and RD is usually the output resistance of an active load (see section 12.2). 2. A common-source amplifier stage -- low frequency gain is AV2 = -gm2(rds3||rds BIAS) This configuration eases the gain requirements of each stage.

19.2. Frequency Compensation in theory

The basic two-stage circuit above includes unavoidable parasitic capacitances, due to charge storage effects in the MOSFETs. These parasitic capacitances add poles to the open-loop gain A(s) of the two-stage amp to rolls off at high frequencies possibly in a third-order way. This can be undesirable if the amplifier is designed to be used with feedback, giving a closed-loop gain of 1/. If this happens, then it is quite possible for the amplifier with feedback to be unstable for the given 1/ -- clearly an undesirable situation! Frequency compensation avoids this by moving or adding a pole to the open-loop gain A(s), usually by adding a capacitor to the amplifier circuit. It is placed in such a way that the amplifier with feedback () is stable. The simplest method consists of adding a new pole at a sufficiently low frequency fD. A good rule of thumb is to place fD such that the modified loop gain, A(s), crosses the 0 dB line at a slope of 20 dB/decade. This method is called dominant pole compensation.
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Example
|A()| (dB) 100 80 60 40 20 0

Solution
|A()| (dB) 100

|A()| (dB) 100

100 80 60 40 20

|A()| (dB)

80 60 40 20

80 60 40

(rad/s)
10 A()
4

10

10

10

10

(rad/s)
10 A()
4

20 101

10

10

10

10

(rad/s) 0 2 10 103 104 105 106 107 108

A() 0

(rad/s) 0 101 102 103 104 105 106 107 108

-20 A() 0 -90 -180 -270 104 105 106 107 108 (rad/s)

0 -90 -180 -270 10

4

0 -90 -180 -270

10
5

-90 -180
104 105 106 107 108 (rad/s)

10

10

(rad/s)

10

-270 101 102 103 104 105 106 107 108 (rad/s)

The above amplifier with poles as shown is unstable in a feedback arrangement with =10-2. How to add a compensation pole to stabilize?
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Pole shifting
Apply the rule of thumb: add an extra (dominant) pole to the open-loop amplifier such that |A| crosses the 0 dB line at a slope of 20 dB/decade. To do this: 1. Find the first pole frequency p1 (here 105 rad/s) 2. Draw a line back from p1 at a slope of 20 dB/decade until it hits the low-frequency line (here 60 dB at 102 rad/s). This is where we should put the new dominant pole, D. The Bode plots for the modified open-loop gain, A(), are shown on the previous page. Also shown are the Bode plots for the modified loop-gain, A(). It is clear that this method achieves stability a phase margin of +45, and a gain margin of about 20 dB. A serious problem with dominant pole compensation is that at most frequencies the open-loop gain is greatly reduced, impairing the performance of the amplifier with feedback. This can be solved by shifting an existing pole, instead of adding a new one.
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If, instead of adding a new pole at D, we were able to shift the lowest pole p1 to a new location D, this would result in the loop gain A() shown right. The amplifier with feedback is just as stable (check the margins!), but maximum gain persists right up to 103 rad/s ten times higher than the previous example. How to do this in practice?

|A()| (dB) 60 40 20 10
1

(rad/s) 0 2 3 4 5 6 7 10 10 10 10 10 10 108

-20 A() 0 -90 -180 -270 101 102 103 104 105 106 107 108 (rad/s)
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19.3. Frequency compensation in practice

Identify the poles p1, p2, p3 etc. manually or from computer simulation, and which stage introduces which pole Assume p1 is introduced at the interface between the two stages (right). We can represent the interface between the two stages by an equivalent circuit (below).

The value of the pole is then

p1 =

1 RO1C p1

To move the pole, now connect a compensating capacitor between vO1 and earth in parallel with Cp1. This will result in the modified equivalent circuit (below):
vO1 IO1 RO1 Cp1 CC A2 vO2

The pole will no longer be at p1; rather, the pole can be at any desired lower frequency D: The pole p1, caused by parasitic capacitances, can be represented by an equivalent RC network at the input of A2 (below), where RO1 is the output impedance of the diff amp and Cp1 models the parasitic capacitance.
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D ' =

RO1 C p1 + CC

)
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So by choosing an appropriate value for CC we can shift the pole frequency from p1 to any desired D.

Note, however: 1. Adding the capacitor CC will usually move some or all of the other poles of the amplifier, p2 and p3. Therefore we may need to calculate the new locations of p2 and p3 and iterate a few times to arrive at the right value for CC. 2. A disadvantage of this method is that CC is usually required to be quite large, especially if the amplifier is an IC op-amp the maximum practical size of a monolithic capacitor is about 100 pF. An elegant solution is to connect a capacitor in the feedback path of one of the amplifier stages: due to the Miller effect its capacitance will appear to be multiplied by the stage gain.
Cf

Reminder: the Miller effect

Consider a circuit element of admittance Y connected between two nodes 1 and 2 (right). In addition, nodes 1 and 2 may be connected by other components (e.g. amplifiers etc.), with the effect that v2 = Kv1 Millers theorem says that Y can be replaced by Y1 and Y2 as shown right, where
v1 Y1 Y2 v2=Kv1

Y1 = Y (1 K )

Y2 = Y (1 1 K )
In our case Y = jCf and K = A2, large and negative (typically between -50 and -100 V/V). So the Miller admittances look like

vO1 IO1 RO1 Cp1

A2

vO2

Y1 = jC f (1 A2 ) j A2C f Y2 = jC f (1 1 A2 ) jC f

and so the effect of Cf is multiplied by the gain of the second stage! END OF LECTURE
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