ECSE2210,MicroelectronicsTechnology,Prof.E.F.

Schubert
Chapter32page1
MOS capacitor Ideal


Introduction

- The Ideal MOS Capacitor
- MOS capacitor consists of a

M Metal Metal has work function u
M

O Oxide: SiO
2
SiO
2
has a large bandgap E
g
> 5eV
SiO
2
is transparent for all visible wavelengths
SiO
2
is a great insulator
S Semiconductor: Si Semiconductor has work function u
Semiconductor
. (We
will use a p-type semiconductor throughout this
Chapter)

- We assume u
M
= u
Semiconductor




Some helpful rules when considering semiconductors

- Applying a negative potential to an electrode is equivalent to putting negative charge on
that electrode.

o Example: When applying a negative voltage to the gate of a MOSFET, a
negative charge is put on the gate.


- Applying a negative potential to a material moves the Fermi level upward.

o Example: Applying a negative potential to the gate of a MOSFET, moves the
Fermi level upward in the gate.



ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page2
Basic bias conditions of MOS capacitor


(1) Equilibrium V
G
= 0 (E
F
= constant throughout structure)





Source: Above page
Drain: Below page

Gate = Metal Gate




ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page3
(2) Negative bias V
G
< 0 (Accumulation)
- When gate bias is negative (V
G
< 0), then E
F
goes up in the metal
M and S have much higer conductivity than O.
Voltage drops mostly across oxide.
Electronic field is generated in oxide.
- Boundary condition of OS interface:
D
ox
= D
semi
or
c
ox
E
ox
= c
semi
E
semi

- Band diagram of MOS capacitor for negative bias conditions:



Fermi levels are different in M and S.
Fermi levels are constant within M and within S

kT E E
e n x p
/ ) (
i
F i
) (

= (1)
Majority-carrier concentration p(x) increases near surface Accumulation

Surface potential = u
s




Surface potential = eu
s
=
Difference between bulk value of
E
i
and surface value of E
i
.
ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page4
When bands bend upward:

0
s
surface
i
bulk
i
< u = e E E (2)

When bands bend downward:

0
s
surface
i
bulk
i
> u = e E E (3)

When bands bend not at all Flatband:

u
s
= 0 (4)




Introducing dependence on x:
) (
i
bulk
i
s
x E E e = u (5)
) 0 ( ) ( = u = u x x (6)

Using Eqns. (1) and (5), one obtains:


kT E E
n x p
/ ) (
i
F i
e ) (

=

kT E x e E
n
/ ) ) ( (
i
F
bulk
i
e
u
=

kT x e kT E E
n
/ ) ( / ) (
i
e e
F
bulk
i
u
=

kT x e
p x p
/ ) (
0
e ) (
u
= (7)

Since u(x) < 0, p(x) increases close to the surface.
Accumulation
Eqn. (7) is consistent with band diagram

Under Flatband conditions, u
s
= 0.
ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page5
(3) Positive bias V
G
> 0 (Depletion)
- When gate bias is positive (V
G
> 0), then E
F
goes down in the metal
- Band diagram:




- Semiconductor is depleted near surface
- Depletion layer thickness follows from Poissons equation:


2

s
A
D
u
c
=
N e
W (8)

E
F
is near E
i
at the surface
Semiconductor is practically intrinsic at the surface
Recall Eqn. (7):

kT x e
p x p
/ ) (
0
e ) (
u
=
We see that for u(x) > 0 p < p
0
(depletion).


ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page6
(4) Positive bias V
G
>> 0 (Onset of Strong Inversion)
- When gate bias is more positive (V
G
> 0), then E
F
goes further down in the metal






- Semiconductor is depleted of holes near surface.
E
F
is close to E
C
at the surface
Semiconductor is n-type near surface
Conductivity of semiconductor is inverted.


- Criterion for the Onset of Strong Inversion:


F s
2 u = u e e (Onset of Strong Inversion) (9)

where

bulk
F
bulk
i F
E E e = u
.
(10)





Onset of Strong Inversion means
that the semiconductor is as
strongly n-type at the surface as it
is p-type in the bulk.
ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page7

Using Boltzmann statistics


kT E E
n p
/ ) (
i
F i
e

= (11)

and Eqns. (9) and (10), one obtains


i
A
F s
ln 2 2
n
N
T k e e = u = u (Onset of Strong Inversion) (12)

At the onset of strong inversion, an n-channel is forward at the Si surface.


- Depletion layer thickness at the onset of strong inversion:


i
A
A
F
A
max D,
ln 2
2
2
2
n
N
e
kT
N e N e
W
c
= u
c
=


i
A
A
2
max D,
ln 2
n
N
N e
kT
W
c
= (13)

W
D, max
is the maximum depletion layer thickness.

A further increase in V
G
will result in more inversion rather than in more depletion.



ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page8
(5) Positive bias V
G
>>> 0 (Strong Inversion)

- Lets go beyond the onset of strong inversion Strong Inversion





Beyond the onset of strong inversion, electrons are induced into the electron channel.
The depletion layer thickness does not increase further, i.e. W
D
= W
D, max
.




Example: Find W
D,max
for ideal MOS capacitors with N
A
= 10
16
cm
3
and
N
A
= 10
18
cm
3
. Assume the following values: n
i
= 10
10
cm
3
,
c
r
= 9.

We use the formula:


i
A
A
2
max D,
ln 2
n
N
N e
kT
W
c
=

For N
A
= 10
16
cm
3
W
D, max
= 0.27 um = 270 nm
For N
A
= 10
18
cm
3

W
D, max
= 0.03 um = 30 nm


ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page9
Illustration of band diagram, charge, field, and potential of ideal MOS capacitor







We use the Depletion Approximation for the acceptor charge in the semiconductor

=
A
3
D
N e Q
D
for
D
0 W x s s (14)

0
3
D
=
D
Q for
D
W x > (15)
ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page10
Threshold voltage of Ideal MOS Capacitor

- Charge neutrality of the MOS structure requires:

) (
charge
electron
D 2
n
charge
depletion
D 2
D
tor semiconduc
D 2
s
metal
D 2
m

Q Q Q Q + = = (16)

where =
D 2
Q Charge per unit area (17)
and
D A
D 2
W N e Q = (18)

- Voltage across MOS capacitor


s ox
u + = V V (19)

where
ox ox
d V E = (20)

D 2
ox
D 2
s ox ox
D 2
s
/ ) / ( C Q d Q = =


ox ox
D 2
s
D 2
ox
D 2
s
ox
/ d
Q
C
Q
V
c
= = (21)

Note that (22)
=
ox
C Capacitance
=
D 2
ox
C Capacitance per unit area

- Threshold voltage




Recall: At the onset of strong inversion:
0
D 2
n
~ Q (23)
D 2
D max D, A
D 2
s
Q W N e Q = = (24)
F s
2u = u (25)
At threshold, an electron channel
is induced at the
oxide-semiconductor interface.
This happens at the
Onset of Strong Inversion.
ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page11
Insertion of Eqns. (23) (25) into Eqns. (19) and (21) yields


F
D 2
ox
max D, A
F
D 2
ox
D 2
D
th
2 2 u + = u + =
C
W N e
C
Q
V (26)

Thus the threshold voltage is the sum of a voltage drop in the oxide and in the
semiconductor at the onset of strong inversion. Eqn. (26) applies to the ideal MOS
structure.

















Capacitance of Ideal MOS Capacitor

- Capacitance of oxide capacitor:

ox
ox 2D
ox
d
C
c
= (27)

- Capacitance of depletion layer:


D
s D 2
D
W
C
c
= (28)
- Two capacitors in series:

1
D 2
D
D 2
ox
D 2
MOS
1 1

|
|
.
|

\
|
+ =
C C
C (29)


1
s
D
ox
ox D 2
MOS

|
|
.
|

\
|
c
+
c
=
W d
C (30)

ECSE2210,MicroelectronicsTechnology,Prof.E.F.Schubert
Chapter32page12
- Illustration:
D 2
MOS
C - versus - V
G
curve (Note: W
D
depends on V
G
)




1
s
max D,
ox
ox D 2
min MOS,

|
|
.
|

\
|
c
+
c
=
W
d
C (31)

- Discussion of
D
C
2
MOS
- versus - V curve (shown above):

V
G
> 0 Accumulation: Holes accumulate at the oxide-
semiconductor interface.

ox
ox D 2
MOS
d
C
c
=

V
G
< 0 Depletion: Depletion layer thickness increases
with V
G
.

1
s
D
ox
ox D 2
MOS

|
|
.
|

\
|
c
+
c
=
W d
C

V = V
th
Onset of strong inversion: W
D
= W
D, max


1
s
max D,
ox
ox D 2
min MOS,

|
|
.
|

\
|
c
+
c
=
W
d
C

V > V
th
Strong inversion
(A) Low Frequency: An inversion channel is formed at
oxide-semiconductor interface.

ox ox
D 2
MOS
/ d C c =


(B) High Frequency: Electron-hole pairs are generated too
slowly to follow ac signal of
measurement.
D 2
min MOS,
D 2
MOS
C C =

(Note: Deep depletion will not be discussed here and is left for advanced courses)