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S.C. Roy1,H.T. Naglez,M.G. McNamel3, W.T. Krakow' 'MCNC - Center for Microelectronics * North Carolina State University, Raleigh, NC
Introduction
The current leader in fatal diseases in the U.S. is heart disease. Over 975,000 people die of a heart attack (cardiac arrest) each year [ll. Greater than 50%die within two hours after the attack. Initially, the attack may s t a r t as angina pectoris (chest pain), myocardial infarction (cardiac muscle death), congestive failure (failure to pump blood), or sudden death. Heart disease currently kills more men than women with men in the 40 50 year old category being most susceptible.
atedcircuit(A&C)chi environmentwithBuilt-InSelfTest &ST). Our use of BI& for Testibilit (DFT) results in a % y reliable r ! z c i M : ? % u, g t in whici physical defects in e device (resulting from manufacturing problems or wearout) can be detected anytime during the device's life cycle. With its implementation as a sin le integrated circuit, the system size can be minimized, a n f the complete instrument is realized with only a few discrete devices. The use of highly integrated medical instrumentation is a hotly debated issue. Most researchers agree it is important that with technology advancing at its current pace,
Figure 1 (a) Cardiac Electrical Pathways (b)Electrocardiogram Summation (Adapted from W.F. Ganong, Review of Medical Physiology, Appleton and Lange, 14th ed, pg 459,1989.)
~ x o ~ o ~ - e / e o ~ o o o o - ~ ~ ~ - ~ ~ ~ ~ ( o ) ~ l ~ e 0 oI E E E C e o
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the contraction of the ventricular muscles, which in turn causes blood to flow into the pulmonary and aortic arteries. The T wave originatm from electrid activity in the ventricular muscles when they repolarize and repare for the next contraction. his laet phase ofthe E & q p a l has tlo mechanical counterpart, and simp1 representa an electrical event. B d e t e c t q the QRS of the ECG aignal, m m y tienta that are auUcardiac agnonalitaes experienced b acterized b an absence of normal C@%mplexett can be detected and &us allowinterventional meamrestobe instituted to avoid the possible death of cardiac tissue and of the patient.
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There are several approaches +at can be used to solve d e constraintson the reliability problem: (1)impoae de designers, 80 untwtable blocks wiU n o x used [4J;(2) implement the des otl a vehide speai6cally de ed for its testability a u P w ths CDC e~ gate m y [5l;Xan&or use built-in wif teat 18") Esattltes. For the design of the QRS chip, points 1 a n 3 we= chOaen[61.
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DFT for ASICs is aseuming rnever increa role. In the past, a PCB designer could implement a r e l i ! system without incorporatiy DFT feature8 in the degign. Designs were highly observa le and wntmllable Bince most of the important signals were accessible by lo@ probes or becisfnmls testers. With an entire PCB Ainctlon now in rn ASIC, probing is not possible and must be rephd with DFT.
Every manuhcturer is interested in producin quality designere of new ASIC componente generally try to save area and improve performance, the manuf&tuers now ask them t o i n c l u d e t e s t a b i l i t y f ~ t ~ ~ Traditionally, chip speed and performance have alwa wonhelp out over testabiht in contests for silicon area. offeredby CAD tooG is still in e*perimental s s Further. more, many of the innovative circuits used% designers, t 'ng to save silicon area, produce deisigns which are untesx l e . These factors are just some of those which often limit ASIC chip reliability.
parts within their limited economic mwurc%s3 .&le 11
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(1)Synchronous clocking (2) No floating levels (3)No wired logic (4) 2 Phase non-overlapping clock (5) No gated clock signals
The Circular Self Test Path (CSTP) method [81[91 involves the reco of some of the sequential elements ofthecireuitintoi%?Yi ~ ~ u ~ q ~ ~ , ce s (Figure2). In a typical design, the YO buffers and aome of the intenul scannable latches are replaced by CSTP cells. The CSTP cells have 3 modes of operation ( n o d and two test modes). The first is a normal 2-phase master-slave D flip-flop. The second mode ie a serial scan mode. Normal serial scan terti mxdures can be used in this mode. The third mode is the%fST mode. During this test mode, all the CSTP cells are tied to ether to form a k-bit Multiple Input Si turn Register (MISh whch both a lies p a t t e r n to the S t and compresses them. The seRtest 1 mode uses all the CSTP aequential elements to form a MISR whose alias' probability is 2-L (where k is the number of CSTP cells i % chain). In addition, a serial input signature n e register (SISR) is used to further compress the data at the output. The SISRs aliasing robability is 2", where m is the number of fip-flops in the S~SR.
Stroud proposed the moving of the SISR to the feedback path to increase thc randomness of the feedback [71. This compressed response from the SISR will be used as the comparison si ature. The 17-bit SISR used to compress the test responseanas an aliasing error probability of 2 7 Our 1. implementation is highlighted in Figure 3.
Table 1 DFTRules .
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summary
Combinational Logic
Why use BIST for the QRS detector ASIC? There is really one answer - to improve device reliability. We require a very high level of fault coverage for our QRS detector since it is to be used in critical care situations. The circular self-test ath (CSTP)BIST, which was used, has been shown to give a gh level of fault coverage [71[81[91.
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The total integrated circuit design time from architectural definition to la out was approximatel 6 months, and the total silicon area &r the design is relativefy modest for the performance achieved. The design statistics, Table 2, show the increase in transistor count for design with BIST. The design size with the BIST circuitry, scannable and CSTF' flip-flops, is 45,544 transistors. The scan path overhead required by the OASISR) system is a proximately 5,000 transistors or 11%. The additional BISf transistor overhead is a proximately 6,400, or 14%. The t t l transistor penalty is t i u s an increase of 25%. oa The inclusion of testing circuitry also required four dedicated pins for control: 1)self-test mode; 2) scan mode; 3)scan in; and 4) scan out. The inclusion of both scan and CSTP in the design enables the QRS chip to be used as a vehicle for comparing device yield and defect levels to test coverage parameters. The lo 'c testing of the chi s will use three test sets: functional, O&XP scan, and CZTP. The resultant test data will be correlated with fault simulation data to evaluate current yield and defect prediction models used in industry. There are many uses for the QRS device as both a stand alone unit and in conjunction with a cardio-tachometer. As a stand alone unit, the monitor can be used for the detection of sudden infant death syndrome and for exercise monitoring. The unit in conjunction with a cardio-tachometercan be used for the monitoring of atients with known conditions such as skipped beats or doubre beats, and also as a secondarymonitor for the operatingroom and other critical care procedures. The implemented real-time QRS detection algorithm was designed and verified in a structured design environment. This project has used an integrated circuit implementation to reduce the size of a large, prototype system, making it a reliable system that could be used in many portable and personal applications. Ideally such a device could be beneficial for some of the 975,000 persons who die each year from heart attacks.
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Several different chip architectures were considered during this hase based on several driving factors. The highest priorit Factors were that device testability should be high (greater J a n 90%) and the system should be highly integrated, so that only a minimal number of extra parts are needed. The architecture was defined in a loose fashion based upon this decision. Once an architecture was defined it was coded into Logic-ZZlllO], MCNC's hardware description lanY g e and tested. The final architecture was synthesized and ayed out using the MCNC OASIS(R) system. The oasis program is a supervisor shell that is used to run all tools necessary for a complete IC design from a finite state machine or netlist description. A target goal can be assigned when oasis is called, the supervisor will then run all the necessary programs to complete the assigned goal. The Logic-ZZZ silicon compiler is the OASISR)s stem front-end. Logic-ZZZallows the specification ofhighlevermodules such as finite state machines. In addition, gate level modules and interconnections between modules can be specified allowng the definition of a complete system in a single file. Logic-ZZI produces a two-level combinationallogicdescription inBerkeley PLA format file. decaf [11] takes PLA format input and transforms this description into an optimized netlist of standard cells. The cell netlist is o timized for area, timing, or a combination based on the cell ibrary desired. The ldvsim 1121 logic simulator was used during the ASIC design. Zdvsim is an event-driven mixed-mode simulator for MOS circuits. The Ldvsim system allows the m i ~ n of g 'C'level, gate level, and transistor descriptions in an open simulation environment. This feature allows verification of the QRS chip at the behavioral, gate level pre-layout, and transistor level post-layout stages in a unified environment. The upnr [13] (vanilla Placement aNd Routing) tool wasused togenerate the physicallayoutofthe QRSchip. vpnr is a standard cell placement and routing program using a quadrisection algorithm. The output of this program is a hierarchical layout in magic E141 format.
Technology Area Transistor Count Scan Overhead BIST Overhead Test Pin Overhead Maximum Clock Rate Fault Coverage Test Vectors
14% 4 pins
20 MHz
998
522,000
Table 2 Design Statistics
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Acknowledgements
We would like to acknowledge Sandia National Labs and MCNC for their hancial support during this project.
References
Heart-DiseaseDeaths Fall 24% in Decade, Philadelphia Enquirer, Jan 16,1989, pg. A7.
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S.C. Roy, A Testable CMOS QRS Detector and Arrhythmia Monitor, Master's Thesis, University of North Carolina, Chapel Hill, NC, 1990. C. E. Stroud, Automated BZSTfir Sequential Logic Synthesis, IEEE Design & Test of Computers, Vol. 5, No. 6, Dec. 1988, pp. 22-32. B. Berg,An Implementation of BZST for Gate Arrays, 1985 BIST Workshop, Kiawah Island, South Carolina, 1985. A. Krasniewski et. al, Circular Self-TestPath: A Low-Cost BIST Technique, h c . of the 16th ACM/IEEE Design Automation Conference, 1987, pp. 407-415. M. Wong, G. Kedem, F. Brglez, A Guide to Logic-ZZZ, D& User Guide, August 1989.
R. Lisanke et al, Decaf:Decomposition and factorization, MCNC Technical Report TR87-15, 1987.
J.V. Briner, Jr., LDVSZM:A Mired Level System Simulator, Duke University, Computer Science North Carolina, Technical Report 89-29, Durham, 1989.
P. R.Suaris and G. Kedem, A Quadrisection based Combined Place and Route Scheme for Standard Cells, IEEE Trans. CAD, Vol6, Num. 3, pp. 234-244, March 1989.
G. Hamachi et al,Magic - A VLSZLayout Editor, 1986 VLSI Tools: Still More Works by the Original Artists, 1986.
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