Microcomputer Interface II-IV Interrupts and Pushbuttons

Lecture 17

Microcomputers

EE 383

Learning Objectives
What is interrupt? What is the mechanism of interrupt? How to program an interrupt for pushbuttons?

Interrupts
An interrupt is a signal which causes the CPU to stop its normal flow of instructions and begin processing code intended to address the situation causing the interrupt signal. An interrupt is generally caused by a change of state on an external CPU pin. The active-low IRQ and XIRQ pins are dedicated to this function. Many port pins may be configured as interrupts. XIRQ and IRQ are the same as Port E pins 0-1. An interrupt signal causes the CPU to immediately perform a subroutine branch to a routine located at a specific address. On the Dragon12plus, XIRQ* is dedicated to the ABORT button used to stop execution of a program running under D-BUG12 without causing a full reset.

IRQ/XIRQ on Dragon12

Port H on Dragon12
For pushbuttons to have an effect the rightmost four DIP switches must be in the UP ( ) position

What does an interrupt do?

When an interrupt occurs (e.g. IRQ* or XIRQ* goes low):
1. 2. 3. 4. 5. 6. 7. 8. 9.

Currently executing instruction completes Turn off interrupt system Transfer control to interrupt service routine Clear interrupt source Store key registers to stack Perform interrupt specific actions Restore key registers from stack Turn on interrupt system Return control to prior running process

What interrupts are available on Dragon12+?

On the Dragon12plus, the XIRQ pin (Port E, pin 0) is dedicated to the ABORT switch. IRQ (Port E, pin 1) is available. For the MC9S12DP256B, the pins of Port H, Port J, and Port P may be made to trigger interrupts. On the Dragon12+, Port H, pins 0-3 are connected to momentary pushbutton switches making them ideal for triggering interrupts.

Interrupt Vectors
An interrupt vector points to the address of the start of the interrupt service routine. The vectors for all interrupt types have all been gathered into a single table. By default this table is located in the range $FF00-$FFFF which is in non-volatile EEPROM. When operating under D-BUG12, the interrupt vectors are all set to point to addresses in RAM where they may be easily updated to point to user-defined routines. The hardware vector for IRQ is located at $FFF2. The DBUG12 vector for IRQ is at $3E72. The hardware vector for XIRQ is located at $FFF4. The DBUG12 vector for XIRQ is at $3E74. D-BUG12 uses XIRQ for the ABORT button.

Enabling Interrupts
Some interrupts such as XIRQ are always processed when they occur. These are known as non-maskable interrupts. Others, such as IRQ, may be ignored. These are the maskable interrupts. To enable processing of any maskable interrupts, the I bit of the CCR must be cleared to 0. This may be accomplished with CLI. The various interrupts are activated through various bits in the control registers. To enable IRQ specifically, the IRQEN (IRQ enable) bit (bit 6) of the Interrupt Control Register (INTCR) (address $001E) must be set to 1.

Interrupt Service Routines

To write a routine which is to be used as an Interrupt Service Routine (ISR), write it as if it were a standard subroutine except replace the RTS at the end of the routine with RTI. To activate the ISR, place the 16-bit address of the first instruction of the ISR into the Interrupt Vector Table. For instance, if you write an ISR starting at address $3000 and you wish to have it activated for XIRQ while running D-BUG12, you could do the following: ORG $2000 MOVW #$3000, $3E74 CLI BRA * RTS Now, when abort pushbutton is pressed, the routine at $3000 will be started.

Example ISR
ORG $3000 SEI LDD #SALUTE JSR PUTS_SCI0 CLI RTI SALUTE DC.B HELLO FROM XIRQ,CR,LF,NULL #include serialio_Dragon12plus.inc End If address $3000 is loaded into the XIRQ vector then whenever the XIRQ is pulsed low, the message HELLO FROM XIRQ should be sent to the host over the serial port.

Dragon12 Pushbutton and DIP switch configuration

Each pushbutton switch (PH0-PH3) is paired with an SPST switch: Vcc

Normally-open momentary

Switch output SPST

When the momentary switch is open (OFF) the output value is high and when the switch is closed (ON) the output value is low.

Port H Control Registers

From DP256reg.asm: PORTH: EQU REGBS+$260 ;portH data register PTIH: EQU REGBS+$261 ;portH input register DDRH: EQU REGBS+$262 ;portH direction register RDRH: EQU REGBS+$263 ;portH reduced drive register PERH: EQU REGBS+$264 ;portH pull device enable PPSH: EQU REGBS+$265 ;portH pull polarity select PIEH: EQU REGBS+$266 ;portH interrupt enable register PIFH: EQU REGBS+$267 ;portH interrupt flag register These controls are described as part of the Port Integration Module are are located beginning at an offset of $20 from the beginning of the PIM block. The PIM block begins at $0240 by default on the MC9S12DP256B.

PORTH

DDRH

PPSH

PIEH

PIFH

Port Interrupt
If any bits of PIEH are set, then an edge transition on the corresponding pin of port H will cause a port H interrupt. The port H interrupt vector is located at $3E4C under D-BUG12 If multiple bits are set in PIEH, then a transition on any one of the selected bits will cause the port H interrupt. The bit of PIFH corresponding to the port pin causing the interrupt will be set. After processing the interrupt and before executing the RTI instruction, the set bit of PIFH needs to be cleared by writing a 1 to the bit. This is counter-intuitive but is the common pattern adopted for all interrupt flags on the HC12 series. The sample code displays how this may be used.

Interrupt Initialization
Initialize interrupts Port H pin 0~3
ORG $2000 MOVW BCLR BCLR BSET BSET CLI BRA RTS * #ISR, DDRH, PPSH, PIFH, PIEH, $3E4C #$FF #$0F #$0F #$0F ; ; ; ; ; ; ; ; ; interrupt vector set Port H as input set Port H for falling edge clear previous interrupts enable interrupts Port H pins 0~3 enable all maskable interrupts eternal loop

Pushbutton ISR
Press pushbutton0 to generate a message
SALUTE0 DC.B HELLO FROM PUSHBUTTON0,CR,LF,NULL ORG $3000 ISR: SEI ;DISABLE ALL MASKABLE INTERRUPTS BRSET PIFH, #%00000001, PUSHBTN0 BRA ISR_DONE PUSHBTN0: LDD #SALUTE0 ;CONFIRM THE INTTERUPT JSR PUTS_SCI0 ;DISPLAY THE MESSAGE ISR_DONE: BSET PIFH, #$0F ;CLEAR PREVIOUS INTERRUPTS CLI ;ENABLE ALL MASKABLE INTERRUPTS RTI #include serialio_Dragon12plus.inc