3 The TTL NAND Gate

3.1 TTL NAND Gate Circuit Structure The circuit structure is identical to the previous TTL inverter circuit except for the multiple emitter input transistor. This is used to implement the diode structure above in active transistor form using parallel diffusions for several emitters.

Figure 3.1 Multiple Input Emitter Structure of TTL If any input is low, the corresponding base-emitter junction becomes forward-biased and the transistor conducts. The other characteristics of the circuit and its transfer characteristic are identical to those of the inverter circuit.

3.2 Logical Operation A table of conduction states can be drawn up showing the state of each transistor in the circuit for all possible input conditions as before to verify the logic function performed. The direction of conduction of T1 can be in the forward or reverse mode so this should also be noted in the table. It can be seen from the table that the output goes LO only when both inputs are HI which verifies the NAND function. IN1 LO LO HI HI IN2 LO HI LO HI T1 ONfor ONfor ONfor ONrev T2 OFF OFF OFF ON T3 OFF OFF OFF ON T4 ON ON ON OFF D ON ON ON OFF OUPUT HI HI HI LO

VCC

R3 R1 RB 4 k 1.6 k 130

N3 N1 N2

N5
T4

N6
T2

Input 1 Input 2

T1

N7 N4 T3

Output (no load)

R2 1k

Fig. 3.2 Circuit Diagram of a Standard 2-input TTL NAND Gate

3.3. Circuit Analysis It is of interest to examine the conditions for the different logic states of the NAND Gate circuit, particularly with regard to estimating the power consumption in each state. This can be done by first establishing the voltages at each of the nodes N1 N7 in the circuit and then finding the total current drawn from the power supply.

(a) At Least One Input LO Output HI To aid in the analysis, the NAND Gate circuit can be redrawn with the transistors which are OFF removed from the circuit as shown in Fig. 3.3. Then the potentials, relative to ground, can be found for each of the nodes in turn. Consequently under this condition, T1 is ON in forward mode, T2 is OFF, T3 is OFF, while T4 is ON at the point of cut-in and therefore T2 and T3 have been removed from the circuit.

VCC IB I1
R1 RB 4 k 1 .6 k

I3
R3 130

N3 N1 N2

N5
T4

Input 1 Input 2

0.1 V

N6 N7 N4
R2

T1

Output (no load)

1k

Fig. 3.3

NAND Gate Circuit Redrawn with at least One Input LO

(i)

T1 ON in forward mode and is operating in saturation as there is only a leakage current from T2 available as collector current, i.e. T1 operates with a large base current and negligible collector current where IC MAX = 0. Then:

Node N1 : VN1 = Vi + VBE1 sat = 0.1 + 0.8 = 0.9V

(ii) With T1 operating in saturation, its collector-emitter voltage is VCE sat = 0.1V so that:

Node N2 : VN2 = Vi + VCE1 sat = 0.1 + 0.1 = 0.2V

(iii) With T4 operating at the point of cut-in its base current and hence its collector current can be taken as zero. This means that there is no voltage drop across either resistor R1 or R3 and so the potential at both sides of these resistors is equal to the supply voltage VCC giving:

Nodes N3 and N5 : VN3 = VN5 = VCC = 5V

(iv) Node N4 is pulled low by the resistor R2 which has no current flowing through it so that:

Node N4 :
(v)

VN4 = 0V

Finally, with T4 operating at the point of cut-in:

Node N6 : VN6 = VN3 VBE4 cut in = 5 0.6 = 4.4V

and with the diode at cut-in also:

Output Node N7 : VN7 = VN6 VD cut in = 4.4 0.4 = 4.0V

4

The current drawn from the supply can then be obtained as:

IB =

VCC VN1 5 0.9V = = 1.025mA RB 4k

with I1 and I3 = 0 as negligible current flows into the base or collector of T4. The power consumption of the gate with the output in the logic Hi state can then be obtained as:

POH = VCC x I B = 5V x 1.025mA = 5.125mW

(b) Both Inputs HI Output LO Under this condition T1 is ON in the reverse mode, T2 is ON, T3 is ON and T4 is OFF. Fig. 3.4 shows the NAND gate circuit redrawn with T4 removed. Potentials must be determined in a different order this time. VCC

I1 IB
R1 RB 4 k 1 .6 k

I3

R3 130

N5 N3

N1 Input 1 Input 2 5V 5V N2

N6
T2

T1

N7 N4 T3

Output (no load)

R2 1k

Fig. 3.4

NAND Gate Circuit Redrawn with Both Inputs HI 5

(i) With T3 ON and in saturation:

Node N4 : VN4 = VBE3 sat = 0.8V

(ii) With T2 also on and in saturation:

Node N2 :

VN2 = VN4 + VBE2 sat = 0.8 + 0.8 = 1.6V

(iii) Since T1 is ON in the reverse mode, the base-collector voltage in this mode can be taken as the same as the base-emitter voltage of a transistor operating in the forward active mode so that:

Node N1 : Node N3 :
(v)

VN1 = VN2 + VBC1 on rev = 1.6 + 0.7 = 2.3V VN3 = VN4 + VCE2 sat = 0.8 + 0.1 = 0.9V

(iv) With T2 operating in saturation, its collector emitter voltage will be VCE sat = 0.1V so that:

With T4 OFF no current will flow through resistor R3 and consequently Node N5 will be pulled up to the supply rail:

Node N5 :

VN5 = VCC = 5V

(vi) With T3 ON and in saturation, its collector-base voltage will be at a saturation value so that the output voltage at Node N7 is simply:

Node N7 :
(vii)

VN7 = VCE3 sat = 0.1V

With T4 and the diode non-conducting, the potential at Node N6 is somewhat ill-defined

and depends on the resistances of the non-conducting junctions of these devices but will lie somewhere between that of Nodes N3 and N7, i.e. between 0.1 and 0.9V. However, this voltage is not significant.

The current drawn from the supply this time is given by the sum of IB and I1 as again I3 = 0. Then:

IB =
and

VCC VN1 5 2.3V = = 0.675mA RB 4k

I1 =

VCC VN3 5 0.9V = = 2.56mA R1 1.6k

The power consumption when the output is LO is then given as:

POL = VCC x ( I B + I1 ) = 5 x ( 0.675 + 2.56) = 16.175mW

If the NAND gate is assumed to spend half of its time in each logic state then the average power consumption is obtained as:

PAVE =

POH + POL 5.125 + 16.175 = = 10.56mW 2 2