EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

I. Silicon wafer fabrication

Silicon (Si) is one of the most abundant elements on Earth as it constitutes nearly 28% of Earths crust. It also happens to be a semiconductor, it is relatively easy to process and it can form an excellent quality oxide, which makes it ideal for microelectronic applications. Most circuits in today microelectronics are made on silicon substrates, therefore, this course will concentrate on silicon-based devices. Nonetheless, there are various semiconductor applications which use other materials such as gallium arsenide (GaAs, the second most popular material in microelectronics) and selected examples will also be discussed throughout the course.

1.1 Silicon crystal structure

Silicon has the same structure as diamond. It consists of two interpenetrating face-centred cubic lattices, displaced along the body diagonal of the cubic cell by one quarter the length of the diagonal. The figure shows a representation of the basic diamond unit cell. The periodic arrangement of identical copies of the same basic cubic cell forms the crystal lattice, also shown in the figure. For silicon, the size of one unit cell or lattice constant a is 0.54306 nm. Germanium, another semiconductor material used in microelectronics, has the exact same atomic structure as silicon but with a slightly larger lattice constant.

(a) Unit cell of silicon; (b) silicon lattice section The crystal orientation defines its electrical properties, therefore, devices fabricated on wafers with different orientations will exhibit different behaviour, even if the material of both wafers is the same! The Miller indices is a notation commonly used to refer to crystal planes. The three most common crystal orientations used in silicon are shown in the following figure.

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

Schematic of the (100), (110) and (111) planes and a silicon lattice section viewed from each direction

1.2 Czochralski growth

Silicon purification Silicon is extracted from silica sand (SiO2). The first stage to fabricate pure silicon wafers is to separate it from the initial SiO2 at high temperature (around 1900C) where carbon is used to reduce the SiO2 to Si according to the following main reactions: SiO2 (s) + 2C (s) Si + 2CO (g) SiO2 (s) + C (s) Si + CO2 (g) This process results in 98% pure Si known as metallurgical-grade silicon (MGS). The remaining impurities are are mainly Fe, B and P atoms, which are removed in a gaseous stage. The MGS is pulverised and converted to gaseous trichlorosilane (SiHCl3): Si + 3HCl SiHCl3 + H2

Impurities also react with HCl to form gaseous compounds which have different boiling points compared with SiHCl3, therefore, SiHCl3 can be separated by distillation and subsequently converted back to solid electronic-grade Si (EGS). 2SiHCl3 + 2H2 2Si (s) + 6HCl (g)

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

Czochralski crystal growth Once pure Si has been obtained, an ingot of crystalline Si is produced using the Czochralski growth technique. The process is carried out in a furnace. The polycrystalline EGS is placed in a silica crucible and heated above the melting point of Si (1421C). A single crystalline seed with the desired crystal orientation suspended over the crucible and dipped into the silicon melt. The crystalline seed is attached to a crystal puller which gradually withdraws the seed from the crucible. Both crystal and crucible rotate in opposite directions. The silicon in contact with the crystal seed solidifies as it is being pulled away from the melt, and it acquires the same crystal orientation as the seed. The pulling rate is initially fast in order to form a thin neck to suppress defects; then the pulling slows down to increase the ingot diameter. The diameter is ultimately controlled by the pull rate, for example, the typical pulling rate for a 100 mm ingot is 1.4 mm/min, while a 200 mm ingot is pulled at 0.8 mm/min. Magnetic fields are often applied during pulling to reduce temperature fluctuations and convection currents in the melt, which improves quality uniformity in the ingot. Dopants can be incorporated during the Czochralski process by adding the doping species into the melt. Doping atoms will also solidify into the ingot and find a site in the crystal. The final doping concentration in the ingot is usually lower than in the melt. This concentration difference depends on the segregation coefficient of the doping species, which is different for each material.

Czochralski crystal pulling

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

When the ingot is completed, the seed is removed and the diameter is defined by grinding the ingot surface. The ingot is then marked using either flats or notches for easy identification of the wafer crystal orientation and doping type. The wafers are then sliced from the ingot and polished to produce a smooth surface.

1.3 Crystal defects

Defects in the crystal can impact its electrical, mechanical and optical properties. During wafer fabrication, some defects can originate during the crystal pulling and wafer preparation stages. However, defect formation is not limited to the wafer fabrication since it can also occur at various stages of device fabrication due to deposition of other films or layers, etching steps, implantation, thermal treatment, etc. Defects are often classified as: i) point defects: vacancies, self-interstitials, foreign interstitials, substitutionals; ii) line defects: some types of linear dislocations; iii) area defects: stacking faults, dislocation loops, twinning; iv) volume defects: precipitates.

Various defect types in a crystal lattice

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

1.4 Wafer engineering

Czochralski growth delivers good quality material, however, it can still be improved by using wafer engineering techniques in order to meet the quality requirements for different applications. Two popular wafer engineering techniques used in semiconductor device fabrication are epitaxial wafers and silicon-on-insulator (SOI). Epitaxial wafers Czochralski wafers may exhibit buried particles or defects originated during the wafer production (often carbon and oxygen impurities), which may be affect the operation of the devices fabricated on that wafer. One way to minimise their impact is to deposit additional Si layers on top of the Czochralski Si crystal in order to bury the particles far below the active regions of the devices, as shown in the figure.

Epitaxial Si over a Czochralski Si wafer The epitaxial material can also be different than the substrate, which expands the design space for some devices, for example, SiGe layers can be used as the base for heterojunction bipolar transistors (HBT) or as MOSFET channels. Epitaxial deposition of crystalline films will be covered in detail in chapter 2. Silicon on insulator Silicon on insulator (SOI) wafers are used to encase the devices in an insulating material to reduce parasitic capacitances and power consumption. SOI technology is also frequently used to manufacture MEMS devices. An SOI structure comprises an insulating layer between the substrate and the top Si layer where devices are to be fabricated. Silicon dioxide (SiO 2) is commonly used as the insulator, often referred to as buried oxide.

Silicon on insulator

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

Three common methods to fabricate SOI wafers are: i) wafer bonding, ii) Smart-cut, and iii) SIMOX. Wafer bonding In this method, the SOI is prepared by bonding together two different wafers followed by the thinning of the backside of one of them by polishing and etching (removal of material using chemicals). The surface of at least one of the two wafers must be oxidised to form the buried oxide. The process starts with the growth of a highly doped epitaxial Si layer on the surface of one of the wafers, followed by a second, lightly doped Si layer which is the device layer. (The large difference in doping levels will make the highly doped layer act as an etch-stop when the backside of the wafer is removed by etching.) Depending on the thickness required in the buried oxide, oxide is then grown on the surface of one or both wafers. Both wafers must have smooth surfaces for a successful bonding. The bonding is carried out at high temperature (around 1000C) to promote the formation of Si-O-Si bonds. Water is released in the process since hydrogen is often present at the surface. The downside of this method is that it consumes two wafers to produce one SOI wafer.

Wafer bonding process

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

Smart-cut The Smart-cut method also utilises two wafers, however, one of them can be used to prepare several SOI wafers. The donor wafer is oxidised and implanted with hydrogen to create gas bubbles beneath the oxide layer, which weakens the wafer in that region. Polishing is necessary after the hydrogen implant to ensure the surface is smooth. Wafer bonding is then performed at room temperature, followed by the sectioning of the donor wafer along the mechanically weak region by annealing at 400 600C. After splitting, further annealing a 1100C is carried out to strengthen the SOI structure.

Smart-cut process

EEE8103/EEE8019 Semiconductor device fabrication Silicon wafer fabrication

SIMOX Separation by implantation of oxygen (SIMOX) only requires one wafer. Oxygen is implanted into the Si wafer, followed by annealing at 550 650C. The high temperature promotes the formation of the buried oxide. The thickness of the Si cap can be controlled by the oxygen implantation energy: high implantation energy will penetrate deeper into the Si, thus leaving a thicker Si layer above the buried oxide. Nonetheless, SIMOX can only produce thin silicon and buried oxide layers (100 nm thick). Although this method is more economical in terms of material requirements, the resulting silicon cap exhibits a high defect density due to the damage induced by the oxygen implantation. Therefore, applications requiring low defect density layers must use SOI materials produced by other methods.

SIMOX process