Code No: RR321301 Set No.

1
III B.Tech Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Electronics & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Explain about IAS memory formats.

(b) List various registers in a computer along with their purpose [8+8]

2. (a) Find the output of the following binary expressions using 2’s complement
representation.
i. 111.01 + 10.111
ii. 110.11 - 111.01
(b) Explain the steps involved in the subtraction of a number from a given number
using 1’s complement notation [10+6]

3. Explain common addressing modes with suitable flow diagrams. Also explain the
merits and demerits of each, in detail. [16]

4. Elaborate on different types of registers in a register organization [16]

5. (a) Discuss about principles of cache memory.

(b) Elaborate on elements of cache memory.
(c) Explain the purpose of replacement algorithms [6+5+5]

6. (a) Explain about magnetic disk layout

(b) Elaborate on Winchester disk track format. [8+8]

7. Discuss about horizontal and vertical instruction formats. Also differentiate be-
tween horizontal and vertical instruction formats. [16]

8. (a) Differentiate between short and long pipeline. Which is more advantageous?
(b) Elaborate on depending constraints of pipelining. Give an example for pipeline
stalled by data dependency.
(c) Give an example for idle cycle caused by a branch instruction. [5+6+5]

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Code No: RR321301 Set No. 2
III B.Tech Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Electronics & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Define PCI. Explain the applications of PCI

(b) Describe any ten mandatory PCI signals. [8+8]

2. Write an algorithm to substract binary numbers represented in normalized floating

point mode with base 2 for exponent [16]

3. Discuss various key design issues of an instruction format. [16]

4. (a) Differentiate between large register file versus cache.

(b) Discuss how compiler based register optimization is done.
(c) Explain various characteristics of reduced instruction set architectures.
[6+6+4]

5. (a) Explain the functioning of ROM cell

(b) Draw and describe the working of CMOS memory cell.
(c) Draw and explain about a single-transistor of dynamic memorycell.
[4+6+6]

6. (a) What is ‘data striping’ ?

(b) Discuss about the recent disk system developments.
(c) Explain the control command operations enabled by magnetic tape drive con-
troller. Also explain about cartridge tape system. [4+4+8]

7. (a) List sequencing and branching control fields of IBM 3033 microinstruction.
(b) Discuss the functioning of micro sequencer with example [8+8]

8. (a) What is branch folding technique in pipelining

(b) . Discuss how operand forwording is done in a pipelined processor.
(c) What do you mean by speculative execution [6+6+4]

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Code No: RR321301 Set No. 3
III B.Tech Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Electronics & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) How optional signal lines for PCI are functionally grouped .
(b) Explain typical server system using PCI configuration. [8+8]

2. (a) How subtraction is done on the binary numbers represented in one’s comple-
ment notation give an examples.
(b) What do you mean by r’s complement. [8+8]

3. List integer arithmetic, logical and shift operations of power PC with description
[16]

4. (a) List and describe all arithmetic instructions of MIPS R-Series processors
(b) Discuss how R3000 pipeline can be modified to improve performance
[8+8]

5. Discuss about power PC cache Organization in detail [16]

6. Discuss three possible techniques for I/O operations with merits and demerits of
each. [16]

7. (a) Differentiate between impact and non-impact printers.

(b) Elaborate on mechanical printers.
(c) Discuss about joysticks which use potentiometers as position transducers.
[5+5+6]

8. (a) Why special handling is required for branch instruction in a pipelined proces-
sor. Explain with examples.
(b) How would you determine the number of pipeline stages in a pipelined proces-
sor [10+6]

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Code No: RR321301 Set No. 4
III B.Tech Supplimentary Examinations, Aug/Sep 2008
COMPUTER ORGANIZATION
(Electronics & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) How mandatory signal lines for PCI are functionally grouped
(b) Explain typical desktop system using PCI configuration. [8+8]

2. (a) Find the output binary number after performing the arithmatic operation
using 1’s complement representation.
i. 111.01 + 10.111
ii. 110.11 - 111.01
(b) Explain steps involved in the addition of numbers using 2’s complement no-
tation. [10+6]

3. Discuss various key design issues of an instruction format. [16]

4. (a) Differentiate between large register file versus cache.

(b) Discuss how compiler based register optimization is done.
(c) Explain various characteristics of reduced instruction set architectures.
[6+6+4]

5. (a) Discuss about address translation in paging.

(b) How does page size effects storage utilization and effective memory data-
transfer rate [8+8]

6. (a) Explain about CD-ROM block format.

(b) What is WORM? Also explain its uses.
(c) Differentiate between disk layout using constant angular velocity and constant
linear velocity [5+5+6]

7. Discuss about current applications of micro programming in detail. [16]

8. (a) Differentiate between high-level and low-level parallelism

(b) Discuss about Flynn’s classification of parallel processor systems.
(c) Explain different MIMD interconnection topologies. [5+6+5]

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