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Selim nl
Photodetectors and Nanophotonics

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TA B L E O F C O N T E N T S
Selim nl
ASSOCIATE DEAN FOR RESEARCH, BOSTON UNIVERSITY
Interview with Selim nl, an expert in the area of photodetectors and nanophotonics.

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TABLE OF CONTENTS

FPGAs Satisfying Demand for Higher Bandwidth

BY RISHI CHUGN WITH ALTERA
Current service providers are continuously looking for technology advancements to keep up with network bandwidth demand, and seeking ways to optimize their network infrastructure.

The Ground Myth in Printed Circuit Boards

BY BRUCE ARCHAMBEAULT WITH IBM
The term ground is probably the most misused and misunderstood term in EMC engineering, and in fact, in all of circuit design. This article provides insight into how you should think about ground.

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INTERVIEW

Selim nl
How did you originally get into electrical engineering? Ive always said that what you do in life is defined mostly by coincidence. In elementary school, I always wanted to be either an electrical engineer or an aviation engineer, despite not even knowing what those professions entailed. Growing up in Turkey, I went to a specialized high school that trained people to become scientists. About a third of my classmates became electrical engineers, more than a third became medical doctors, and about a fifth took other engineering jobs. I chose electrical engineering because I enjoyed the subject material. For two years, as a junior and senior, I had a job at a factory building electronic circuits for

Nanophotonics Expert
handheld radios, transmitters, and receivers. It was very satisfying to build things that could actually be put to use. When I finished my undergraduate degree, I applied to graduate programs, and was admitted to the Masters and PhD programs at the University of Illinois at UrbanaChampaign. At the time, my background was in high-frequency devices including electronic circuits, electromagnetics, and microwaves. Based on my experience with microwave devices, my MS and PhD advisor recruited me to work on semiconductor devices. Although this was a completely new field of study for me, I accepted the offer and worked in his lab for six years.

I worked on a variety of semiconductor devices from bipolar transistors to diodes. After my MS and a couple of years into my PhD, I started to work on optoelectronic devicesmostly photodetectors, which I became interested in enhancing with an interference filter. One of the most significant coincidences that shaped my career was having Katsumi Kishinoa professor from Tokyovisit our lab while on sabbatical. Working with Kishino, we developed resonant cavity enhanced (RCE) photodetectors. The RCE concept was an interesting innovation and applied to both detectors and light emitting devices. Consequently, RCE attracted significant interest from researchers worldwide and became a very large research field over the next decade. Today, there is even a Wikipedia listing. What are your major research areas now? I work in a variety of application areas at Boston Universitys College of Engineering, which offers a very collaborative, highly interdisciplinary, and stimulating work environment. Based at the B.U. Photonics Center, my laboratory interfaces with many research groups in engineering and the sciences, and has very strong ties to the B.U. Medical School. One of my major areas of focus is high-resolution optical microscopy with an emphasis on semiconductor circuit imaging and fault isolation. Most recently, I branched into doing conformational measurements of

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Selim nl - Optical Characterization and Nanophotonics

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INTERVIEW
biomolecules, biosensing, and neural stimulation. Our groups name, Optical Characterization and Nanophotonics (www.bu.edu/ OCN), falls short of adequately describing the breadth of our multi-disciplinary research. Can you give a background on each one of those applications? Let me start with our recent work on high resolution imaging of semiconductor circuits and devices using a solid immersion lens. The trend in the semiconductor industry is to reduce the dimensions and increase the number of transistors in a chip, while increasing speed and reducing power. When you are making these finer structures, you have to use a very short wavelength of ultraviolet light in photolithography. Once the fabrication is completed, the top surface of the chip has many layers of metallic, opaque structures, so you can no longer look through the top surface to examine the semiconductor layer and see what devices are functioning as designed, or what is not working well. If there is a fault, you cannot identify it by looking from the top surface. Instead, most of the technologies for isolating faults in semiconductor chips are through backside imaging, that is, through the silicon substrate. For inspection, you can no longer use the very short wavelengths in the UV range that are utilized during the manufacturing process. Instead, you have to use infrared wavelengths because silicon is not transparent in the visible. Basically, you have to use a five-timeslonger wavelength to measure the things you have written with short wavelengths. Thus, your imaging resolution is no longer compatible with the nanoscale structures on the electronic circuit. We have developed a very simple technique using a high-index silicon microlens that transforms the back side of the substrate, which is normally flat, into a curved surface, which allows tight focusing of light. That way we can achieve resolutions that are compatible with the feature sizes that engineers are trying to image. We pioneered this technology for circuit and device design about ten years ago, and have been working on improving it ever since. Recently we received substantial funding from the Intelligence Advanced Research Projects Activity (IARPA) totaling $5.3 million as an interdisciplinary research team from Boston University along with an industrial partner, DCG Systems, Inc. of California. Our team will spend the next four years applying novel imaging approaches to pinpoint and resolve defects on next-generation ICs. These tools, which enable rapid and accurate fault identification, are very important because the semiconductor industry is very large and extremely timesensitive; in the development cycle of new electronics chips, minutes are measured in many thousands of dollars. Are you building a prototype? We will work indirectly with semiconductor manufacturers and state-of-the-art chips. Manufacturers will not reveal the specific structure of the metal layers, materials in the chips, and other components, and chip layouts are also closely guarded secrets, but many chip manufacturers are DCG Systems customers. We rely on our industrial partners expertise and connections to ensure the relevance of our technology development. What size of structures are you able to resolve with the technology youve been developing? In our current research program, the first milestone is to resolve fault isolation at 150 nanometers. The semiconductor technology does not arbitrarily reduce the size of the devices continuously, but rather follows a roadmap with discrete improvements termed nodes. When we started to work on solid immersion lens technology, standard semiconductor IC technology nodes were transitioning from 0.13 microns to 90 nanometers. Subsequent technology nodes were 65 nm, 45 nm, and 32 nm. The nextgeneration technology thats going into production is 22 nm. In the next four years, we hope to achieve 22-nm as well as 11-nm nodes. Our resolution requirements are 150 nm for the first phase and 80 nm for the next generation. It will be very challenging to isolate faults with that precision on the chip, but our strong team and innovative technology give us confidence.

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INTERVIEW
What do you use as the image sensor? There are different modalities of imaging semiconductor chips. Obviously, you want to monitor how well the electronic circuit is functioning. One of the specific analysis techniques our industry partner has developed is so-called laser voltage probing (LVP), or laser voltage imaging (LVI). In this modality, you have the chip working as it would normally operate (with a clock driving the chip at a certain frequency), and data flowing through the chip at a different repetition rate. Thus, the transistors are switching at these frequencies. If they are functioning properly, you know that some of them have to be switching at the data frequency and some of them should be switching at the clock frequency. And then you shine a tiny spot of light on the circuit and scan that light across the chip. So, at a given time, light is reflecting from a small area, and the resolution is determined by how tightly you can focus that light. When the transistors switch, there is a slight change in the optical properties due to variations in the carrier concentration. Observing the reflected light, you can look at the changes at those particular frequencies, either clock or data, and if you see a signal modulated at the clock frequency, or data frequency, for example, you can see the transistor switching at that speed. Most of the signal is not modulated at that frequency; its a very small change (less than one part in 1,000). Extracting that information is a detection problem, but we do use somewhat ordinary photodetectors for this. The innovations are mostly in the optical systems. By scanning the focused light across the chip, we can form an image. Alternatively, by focusing on a single point we can obtain the switching characteristics as a function of time. These are used to diagnose the circuits so you know that these transistors should be switching at this frequency, and if they arent switching as expected, you know that there is a fault. transistor parameters change, the amount of light emitted and the wavelength of the light is also varying. Its a moving target, thus a very challenging project. When we started working on this project, we were the first people who actually applied solid immersion techniques to semiconductor circuit imaging. Now, all of the equipment manufacturers are using similar technology. Almost invariably, everybody has to use this solid immersion lens technology to image chips. Its quite satisfying to see that our hard work is making an impact. Can you tell us about your other project on Disease Diagnostics? The current industry techniques for diagnostics are based on a sandwich assay. Most of the detection techniques rely on fluorescent labels for transduction. A common way of detecting the presence of a disease is to look for the protein biomarkers. Every pathogen has specific antigens and the immune system will develop antibodies against the infection. Typical assays use antibodies as capture agents to detect the presence of corresponding antigen proteins in a sample such as blood, urine, or saliva. Capturing these proteins does not provide a sufficient signal. A secondary antibody that recognizes the same antigen is used in a so-called sandwich assay, where the secondary antibody has either an enzyme or some fluorescent molecules linked to it. Consequently, either

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We pioneered this technology for circuit and device design about ten years ago, and have been working on this ever since.
Another method is called photo emission microscopy. When transistors switch, they emit a tiny bit of light. You can collect that light, and from determining the timing of the emission and its location, intensity of the light and timing of the signal, you can diagnose the circuit. Of course, that light is in very small amounts, so you need to build very sensitive detectors, very high collection-efficiency optics, and high-resolution optics to operate the transistor properly. You also have to work very closely with the manufacturers because, as the

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INTERVIEW
the solution color changes, or it fluoresces when excited by another light source. Thats a transduction mechanism to make the presence of small amounts of target proteins captured visible. This kind of technology is typically called enzyme-linked immunosorbent assay (ELISA). Its a very common technology, but it does require a secondary antibody, and you have to refrigerate those, have a trained technician, etc. The problem is, you cannot perform those types of tests in a doctors office. Today, you go to the doctor for an examination, the doctor takes your blood, and you have to come back three days later for the results. We want to build systems where people can, around the world, be tested right on the spotat the point of care. Are you at the point where you will start working on prototypes? Label-free sensing is a recent trend in disease diagnostics. We all want to get rid of the secondary antibodies, the additional reagents, and the labels. But its a challenging project, because you have to do the detection, not only sensitively, but also specifically. There are a lot of steps that need to be taken to prove these things. Using our knowledge of optics and layered surfaces, based on our expertise in semiconductors, we have recently been able to build the technology for a very inexpensive and compact system. We can detect individual bioparticlessomething that people werent able to do prior to our work. Now, on a very simple surface, we can detect the presence of individual nanoparticles and viruses. We would like to apply this to diagnostics, which would allow multiple diagnoses on a single chip, with much more timely results.

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FPGAs Satisfying the Demand for

Higher Bandwidth
By Rishi Chugh, Altera Corporation

Current service providers are continuously

looking for technology advancements to keep up with network bandwidth demand, and seeking ways to optimize their network infrastructure. These service providers must continue to make a profit by reducing the cost per bit while simultaneously extending their service offerings. High-speed Ethernet, especially 100G Ethernet (100GE), offers the key solution. As the demand for more bandwidth becomes increasingly prevalent, service providers are looking at emerging 40-GE/100-GE standards for their next generation line cards (Figure 1). A few key adopters like Data-Centers, cloud computing vendors, government/financial institutions and large research labs are also driving todays quest for ever-increasing high speed connection and aggregation speeds. Companies like Google, Facebook, Yahoo, EBay and others have been forced to use multiple 10GE links in parallel to meet their

bandwidth needs, however this creates problems with port density, traffic management and power consumption. Currently they are desperately evaluating solutions and looking at both 40GE and 100GE architectures. This would eventually drive 100GE into the transport eco-system and this would be an integral play in the edge router architecture. Todays FPGA devices offer solutions to the bandwidth problem by providing integrated 10-Gbps transceivers with integrated Physical Coding Sublayer (PCS) functions on the 28-nm process node. Highest System Integration for Increased Functionality in a Smaller Line Card A key challenge in designing a 100-GbE line card is determining the level of integration that can be achieved on a small form factor line card without exceeding the cost and power-consumption budget.

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TECHNICAL ARTICLE
TECHNICAL ARTICLE

Nx100GbE 100GbE 10GbE & 40GbE

Figure 1: 40G/100G Eco-System Deployment

Designing with these FPGAs allows developers to reach an unprecedented level of system integration on one FPGA while maintaining low cost and power consumption. These FPGAs offer a fully-integrated PCS per transceiver supporting 8b/10b, 64b/66b as well as 64b/67b encoding decoding schemes. In addition, some FPGA vendors offer integrated functions equivalent to 14.3 million ASIC gates or 1.19 million logic elements (LEs) within their device. This feature allows designers to harden standard or logic-intensive applications within the FPGA. Using these integrated hardened functions built within the next generation FPGA devices, designers can implement the full 100-GbE system within a single device, saving hundreds of LEs for implementing the remaining design functions. In this way, designers can fit 100GbE logic functions, including elements of

traffic management and packet processing, in as few as two FPGAs, as shown in Figure 2. FPGAs are customized using these integrated builtin functions to deliver devices with PCI Express Gen1/Gen2/Gen3 hard IP or hardened 100-GbE PCS. For 100-GbE line card designs, developers can start with the FPGA, which hardens the 100GbE PCS, and use the remaining EHBs to harden other functions related to their application. Today FPGA venders offer devices to designers with the required resources such as targeted reference designs, fully tested IP development kits , and expert technical support, which will shorten design cycles and time-to-market. These complex FPGA product offerings are supported by the industry-leading design software that features productivity-boosting tools such as power and

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TECHNICAL ARTICLE
TECHNICAL ARTICLE

1 100G Chip to Backplane

2 100G Chip-to-Chip Interlaken 20-24 x 6.375 Gbps

3 100G Chip-to-Module CAUI (10 lanes x 10 Gbps)

100G Traffic Manager Switch fabric/10G backplane 1 Stratix V FPGA 2

TCAM
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100G MAC Packet Processing Stratix V FPGA 3

TCAM

Egress Traffic Manager

Line/Optical Module

Packet Buffer

LUT

Statistics

QDR II/III RLDRAM II

QDR II/III

DDR3

Figure 2: 100G Line Card using next generation FPGA devices

performance-drive compiles, Advance Blockset, and easy-to-use partial reconfiguration. 100G system designs are gaining popularity as bandwidth requirements continue to grow exponentially. An ideal FPGA solution for 40-GbE/100-GbE systems that delivers integrated 10 Gbps transceivers and hardened industrystandards is an IP that supports the emerging 100-GbE standards and proprietary serial protocols with line rate up to 28Gbps. It will perfectly fit the design requirements of next generation 100GbE system designs. Offering system designers an accelerated time-to-market advantage with reduced risk compared to ASSP or ASIC solutions is indeed the right path to follow.

About the Author As senior product marketing manager, Rishi Chugh is responsible for product marketing in Alteras wireline business group, as well as leading its specific product planning activities. Mr. Chugh joined Altera in March 2008, and has over 15 years of industry experience with LSI and Artisan Components (acquired by ARM).

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By Bruce Archambeault Distinguished Engineer

Ground
Myth in Printed Circuit Boards
The term ground is probably the
most misused and misunderstood term in EMC engineering, and in fact, in all of circuit design. Ground is considered to be a zero potential region with zero resistance and zero impedance at all frequencies. This is just not the case in practical high-speed designs. The one thing that should be remembered whenever the term ground is used, is that Ground is a place where potatoes and carrots thrive! By keeping this firmly in mind, many of the causes of EMC problems would be eliminated. The term ground is a fine concept at DC voltages, but it just does not exist at the frequencies running on todays typical boards. All metal has some amount of resistance, and even if that resistance was near zero ohms, the current flowing through a conductor in a loop creates inductance. Current through that inductance results in a voltage drop. This means that the metal ground plane/wire/bar/etc. has a voltage drop across it, which is in direct contradiction with the intention and definition of ground The important point is that for EMI/EMC we need to consider the current, not the voltage, in our signal paths. Since current must always flow in a loop back to its source, the return current path must be considered as well as the intended signal path along a PCB trace. Any interruptions to the return current path can

The

Signal Path

Connector

GND PWR Signal Layers

Figure 1: Initial two board configuration

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TECHNICAL ARTICLE
have serious negative effects to the EMI/EMC performance of a PCB. A very slight deviation in return current path can result in enough inductance to dramatically increase emissions. The return current path is also very important when considering mother/daughter board configurations. Figure 1 shows a simple four-layer board example of a mother/daughter board configuration and a signal path from the mother board to the daughter card through a connector. If we consider how the return current will flow from this configuration, we should expect that the return current will spread out to include displacement current through the dielectric between GND and PWR, as well as local decoupling capacitors (depending on their distance and the plane separation). Figure 2 shows the return current for this configuration. The added return current path length results in additional inductance in the total path, resulting in a noise voltage between the two GND planes (across the connector). This noise voltage will drive the wide, thin, monopole-like antenna, resulting in increased emissions. However, if we had simply considered the return current path and routed the signal trace so that it was referenced to the same plane (PWR or GND), the return currents are able to stay close to the signal trace (Figure 3), and emissions are greatly reduced. When we consider the return current path, more ground is
Signal Path Connector

TECHNICAL ARTICLE

GND PWR Return Current Signal Layers

Figure 2: Return current paths for initial configuration

not always the right answer! For example, on a recent design, there was a 144 pin connector with many high speed signals traveling from one board to the other. It was determined that 30 pins could be used for power and ground combined. At least five pins must be power so there would not be an excessive DC voltage drop across the connector. How many of the remaining 25 pins should be ground? In this particular design, it turned out that about 2/3 of the total signal pins were referenced to the power plane, and only 1/3 referenced against the ground plane. This meant that of the total 30 possible power/ground pins, 2/3 should be power and only 1/3 should be ground! More ground pins was NOT the best design for this case. Of course, once we consider both the power and the ground pins to be return current paths, it is obvious we should distribute them throughout the signal pins to keep the return current deviation as small as possible (compared

to putting all the ground pins at the ends of the connector, etc.). When we consider the most important concerns for good EMI/ EMC design, the schematic is not as important as the physical layout of the signal path and the return current. Since todays high speed PCBs have many layers and are very complex, it is difficult for an engineer to examine each critical signal path for a good return current path. Automated EMC rule checking tools can examine each net in turn, regardless of the PCB complexity. The key to selecting an automated rule checking tool is to make sure it can interface well with your existing design process, it is easy to use, and it can display rule violations in a graphical and easy to understand manner. The most important EMC design rules for high speed PCBs concern the return current path. Since the return current will always find a path that minimizes the inductance of that path, the return current will always flow on the nearest plane,

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is whether it will be a path that is beneficial to you, or if it will cause problems. So, Do you feel lucky today? It is always best to design on purpose rather than by luck.

TECHNICAL ARTICLE

Displacement Current Connector Signal Path

Decoupling Capacitors

About the Author

Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC and co-founder of Applied EM Technology. He received his BSEE degree from the University of New Hampshire in 1977 and his MSEE degree from Northeastern University in 1981. He received his PhD from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems.

GND PWR Signal Layers

Figure 3: Improved return current design

whether it is called ground or power or carrots. When traces across a split in the return plane (for example if a trace is routed next to a power layer with multiple power islands), the return currents path is interrupted. Changing

layers within the PCB so that the return current must also change planes will also interrupt the return current path. Remember, the return current must always get back to its source. It will get back to its source. The only question

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