Abstracts - VLSI Projects 2010 - NCCT, Final Year Projects IEEE Projects

NC CT
Promise for the Best Projects
IEEE PROJECTS 2010-11
VLSI & FPGA
ALGORITHM OF BINARY IMAGE LABELING AND PARAMETER EXTRACTING BASED ON FPGA

ABSTRACT
For the real-time detection and identification requirements of the rail profile image, A quickly algorithm using connectivity labeling of binary image and parameter extracting to remove the speckle disturbing was presented in this paper, based on FPGA, it can use the limited hardware resources of the system to realize high-speed and accurate binary image labeling and feature extraction, obtain the bright band image and region. This method overcomes the shortcoming of previous methods which must scan pixel repeated and require a large memory to record the relationship of the connected components, and a large computation to merge the labeling. Also, it is rapid, simple, rules, and extensibility, the processing speed will be increased by providing a quick effective way to identify and record the complex relationship between regions, and by completing the label merge or parameter extraction during the line or field blanking realizing of FPGA can accurately and effectively identify the complex connectivity between images, produce the correct label results and extract the characteristic parameters of each connected component which can limit the subsequent processing in a rectangle and save the time and resource greatly, provide guarantee for subsequent identification. The algorithm is used and we have a good effect on the scene testing of rail measurement, it is enough to meet the requirement of real-time image recognition system.
Tools used Language FPGA
: Xilinx Platform Studio :C : SPARTAN 3 XC3S200
Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS
NC CT
MICROCONTROLLERS * VLSI * DSP * MATLAB

, 28235816, 93801 02891, 98411 93224 , www.ieeeprojects.net , ncctchennai@gmail.com
www.ncct.in
NC CT
VLSI & FPGA
IMAGE EDGE DETECTION BASED ON FPGA

ABSTRACT Field Programmable Gate Array (FPGA) is an effective device to realize real-time parallel processing of vast amounts of video data because of the fine-grain reconfigurable structures. This paper presents a kind of parallel processing construction of Sobel edge detection enhancement algorithm, which can quickly get the result of one pixel in only one clock periods. The algorithm is designed with a FPGA chip called XC3S200- 5ft256, and it can process 102410248 Gray Scale Image successfully. The design can locate the edge of the gray image quickly and efficiently. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT
EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS
NC CT

www.ncct.in
NC CT
VLSI & FPGA
FPGA BASED REAL-TIME ADAPTIVE FUZZY LOGIC CONTROLLER

ABSTRACT
Fuzzy logic based control systems provide a simple and efficient method to control highly complex and imprecise systems. However, the lack of a simple hardware design that is capable of modifying the fuzzy controller's parameters to adapt for any changes in the operation environment, or behavior of the plant system limits the applicability of fuzzy based control systems in the automotive and industrial environments. The design and implementation of an FPGA based fuzzy logic controller, that allows real-time modification of its membership functions and rule base is introduced in this paper. The development of the controller's architecture is carried out on a National Instruments Intelligent DAQ board (PCI-7833R) with a reconfigurable Xilinx Virtex-II FPGA. The proposed design combines the performance advantages of existing static FPGA based fuzzy control architectures, with the flexibility and ease of implementation of conventional micro-controllers and general purpose processors. To test the efficiency of the controller and its ability to stabilize a highly dynamic system, a semi-active suspension system was developed. Simulation results for the proposed FPGA controller showed a 56% characteristic enhancement over the standard passive suspension system.
Tools used Language FPGA
: Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

www.ncct.in
NC CT
VLSI & FPGA
RECOGNITION FPGA SYSTEM FOR DETECTION OF ANOMALIES IN MAMMOGRAMS

ABSTRACT The recognizing of cancer in mammograms implemented on the FPGA platform is pretty much similar to PC result evaluation. With less than 0.6% error, this program can be used in other image processing applications that require the neural networks employment with good results in characteristic recognizing of the images. The FPGA is used as a platform to implement the rank filter and the neural network hardware employing a scheme off-line training (by software). Last facilitates the implementation due to the ability of reprogramming the FPGA. In this case, the program could be implemented successfully in the Stratix EP1S80B956C6 FPGA using less than 15% of its resources. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

www.ncct.in
NC CT
VLSI & FPGA
SORT OPTIMIZATION ALGORITHM OF MEDIAN FILTERING BASED ON FPGA

ABSTRACT The traditional sorting algorithm of median filtering is optimized according to the hardware structure features of FPGA. FPGA is used to acquire the data parallelly for comparing the data of the same column in the median filtering window. Comparing results shared by adjacent filter window are saved temporarily to match the new round of median filtering by using FPGA internal resources. This method can reduce the comparing times from current 21 down to 13, and improve the algorithm efficiency nearly 40%.The experimental results prove that the optimized algorithm can filter a 1K1K gray-level image in about 20ms, which ensure the proposed algorithm can be applied in the real-time image median filtering system. Tools used Language FPGA KIT : Xilinx Platform Studio :C : SPARTAN 3 XC3S200 : SPARTAN 3 EDK KIT
Compiler code : Verilog/VHDL
NC CT

www.ncct.in
NC CT
VLSI & FPGA
AN FPGA-BASED ARCHITECTURE FOR LINEAR AND MORPHOLOGICAL IMAGE FILTERING

ABSTRACT Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of real time algorithms suited to video image processing applications. The unique architecture of the FPGA has allowed the technology to be used in many applications encompassing all aspects of video image processing. Among those algorithms, linear filtering based on a 2D convolution, and non-linear 2D morphological filters, represent a basic set of image operations for a number of applications. In this work, an implementation of linear and morphological image filtering using a FPGA NexysII, Xilinx, Spartan 3E, with educational purposes, is presented. The system is connected to a USB port of a personal computer, which in that way form a powerful and low-cost design station. The FPGA-based system is accessed through a Matlab graphical user interface, which handles the communication setup. A comparison between results obtained from MATLAB simulations and the described FPGA-based implementation is presented. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

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NC CT
VLSI & FPGA
PERFORMANCE EFFICIENT FPGA IMPLEMENTATION OF PARALLEL 2-D MRI IMAGE FILTERING ALGORITHMS USING XILINX SYSTEM GENERATOR
ABSTRACT Currently, Field Programmable Gate Array (FPGA) goes beyond the lowlevel line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image filtering algorithms using the Xilinx system generator. The implementation method consists of five simple steps that provide fast FPGA prototyping for high performance computation to obtain excellent quality of results. The results are obtained for nine 2-D image filtering algorithms. Behaviourally, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are targeted to achieve; lower power consumption of (1.57 W) and down to (0.97 W) respectively at maximum sampling frequency of up to (230 MHZ). Then, one of the nine MRI image filtering algorithms, has empirically improved to generate an enhanced MRI image filtering with moderate lower power consumption at higher maximum frequency. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

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NC CT
VLSI & FPGA
DESIGN OF SHA-1 ALGORITHM BASED ON FPGA

ABSTRACT SHA (Secure Hash Algorithm) is a famous message compress standard used in computer cryptography, it can compress a long message to become a short message abstract. The algorithm can be used in many protocols or Secure Algorithm, especially for DSS. In this paper, the improved version SHA-1 is analysised, then improved and implemented in HDL (Hardware Description Language) and FPGA. QuartusII is used to compile and generate the function modules, RTL level description circuit and simulated waveform. RTL level description is the circuit connection in FPGA chip. It shows the connection of the modules. Simulated waveform shows us the timing and the function of the SHA-1 module. The algorithm is implied easily. And the SHA-1 module that design in this paper used less memory units and logic elements. It can be used in DSA or any protocols or secure algorithm. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

www.ncct.in
NC CT
VLSI & FPGA
HARDWARE REALIZATION OF SHADOW DETECTION ALGORITHM IN FPGA

ABSTRACT The paper describes the problem of shadow detection in video sequences. Based on the methods known from the literature, a novel shadow detection algorithm has been developed, working in real-time and intended for hardware implementation in FPGA. The algorithm has been tested and compared to the existing ones in the MATLAB environment. The shadow detection system has been implemented in Virtex-4 FPGA using VHDL language. This system has been tested with respect to efficiency, utilized hardware resources and power consumption. The results from the running system, the conclusions and the possibilities of further improvement of the designed system are presented. Tools used Language FPGA : Xilinx Platform Studio :C : SPARTAN 3 XC3S200
NC CT

www.ncct.in
NC CT
VLSI & FPGA
RFID-BASED HOSPITAL REAL-TIME PATIENT MANAGEMENT SYSTEM

ABSTRACT In a health care context, the use RFID (radio frequency identification) technology can be employed for not only bringing down health care costs but also facilitate automating and streamlining patient identification processes in hospitals and use of mobile devices like PDA, smart phones, for design a health care management systems. In this paper, we outline a RFID model for designing a system in the health care. An application of the architecture is described in the area of RFID-based real-time hospital patient management system (HPMS). Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

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NC CT
VLSI & FPGA
DEVELOPMENT OF A NEW BREATH ALCOHOL DETECTOR WITHOUT MOUTHPIECE TO PREVENT ALCOHOL-IMPAIRED DRIVING
ABSTRACT A new breath alcohol detector for a driver has been developed. A mouthpiece is not required for the detection because driverpsilas breath sample is captured by an electric suction fan of the detector. The influence of an arbitrary dilution of driverpsilas expiration is extremely reduced by the calibration of alcohol concentration, using an oxygen level of driverpsilas expired breath that is measured simultaneously with the alcohol content. The detector is able to measure breath alcohol concentration rapidly and easily, compared with the current breath alcohol detectors, which require a blowing through a mouthpiece. Good accuracy has been demonstrated in an experiment with the drunk subjects. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
THE REALIZATION OF PRECISION AGRICULTURE MONITORING SYSTEM BASED ON WIRELESS SENSOR NETWORK
ABSTRACT Based on the analysis of the development of agricultural mechanization, the trend of agricultural service system reform, agricultural environment protection and the development of information technology, it is possible to realize the precision agriculture. This paper designs the agricultural environmental monitoring system based on the wireless sensor network (WSN). The system can real-timely monitor agriculture environmental information, such as the temperature, humidity, and light intensity. This paper introduces the theory of the monitoring system, and discusses the aspect of hardware and software design of the composed modules, network topology, network communication protocol and the present challenges. Experiments show that the node can achieve agricultural environmental information collection and transmission. The system has the feature of compact in frame, light in weight, steady in performance and facilitated in operation. It greatly improves the agricultural production efficiency and automatic level drastically. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
FPGA IMPLEMENTATION FOR HUMIDITY AND TEMPERATURE REMOTE SENSING SYSTEM

ABSTRACT This paper presents the hardware design and implementation of a remote sensing system for humidity and temperature in real time. The design based on using FPGA (Field Programmable Gate Array) for the hardware implementation of the controller circuit and GSM (Global System for Mobile) for remote monitoring. The controller circuit has been described using VHDL (VHSIC Hardware Description Language). The design has been simulated using ModelSim from Model Technology and implemented using Xilinx ISE 6.2i software tools. FPGA Spartan 3E starter kit from Digilent has been used for the hardware implementation of the controller circuit. The system offers low cost and user friendly way of 24 hours real-time remote monitoring for temperature and humidity using SMS (Short Messaging Service) messages. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
MOBILE VIDEO MONITORING SYSTEM BASED ON FPGA AND GPRS

ABSTRACT In order to improve efficiency of video monitoring system and meet the needs of mobile video system, MPEG-4 video compression encoder was designed, which use the "cross" motion estimation algorithm and DCT if whose coefficients all is zero, it can prejudged, processor structure based on the Nios was created, and video transmission based on GPRS module was built. The system is real-time mobile video monitoring intelligent system with implementing the integration of monitoring, security and control. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
IEEE1451-BASED MULTI-INTERFACE MODULE (I2M) FOR INDUSTRIAL PROCESSES AUTOMATION

ABSTRACT This paper describes the implementation of a multi-interface module (I2M) for automation of industrial processes, based on the IEEE1451 standard. Process automation with I2M can communicate through either wires or using wireless communication, without any hardware or software changes. We used FPGA resources to implement the I2M functions FPGA, with a NIOS II processor and ZigBee communication system (IEEE802.15), as well as RS232 serial standard. Part of the project was done in the SOPC Builder environment, which gave the designer flexibility and speed to implement the NIOS II-based microprocessor system. To test the I2M implementation, a didactic Industrial Hydraulic Module (MHI-01) was used to simulate two industrial processes to be controlled by the system proposed. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
SOLID WASTE MONITORING AND MANAGEMENT USING RFID, GIS AND GSM
ABSTRACT This paper deals with the solid waste monitoring and management system using radio frequency identification (RFID) associate with intelligent systems. The system consists of RFID system, mobile communication like GSM and geographical information system (GIS) for tracking vehicle position. The proposed system would be able to monitor the solid waste collection process and management the overall collection process. It would provide in time solid waste collection, tracking the vehicle position through the GIS database and also overcome the disadvantages such as usage of minimum route, low fuel cost, clean environment and available vehicle. The technologies that would be used in the proposed system are good enough to ensure the practical and perfect for solid waste collection process monitoring and management for green environment. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in
NC CT
VLSI & FPGA
INNOVATIVE APPLICATION OF RFID SYSTEMS TO SPECIAL EDUCATION SCHOOLS

ABSTRACT Innovation is a new way of doing something. It may be incremental, radical, or revolutionary changes in thinking, products, processes, or organizations. Different from invention, which is an idea made manifest, innovation is ideas applied successfully. In this work, we strive to apply innovative Radio Frequency Identification (RFID) systems to special education school campus because in this modern age of science and technology, there still exists a wide digital gap in special education schools such that they have not yet benefited from technology advancements such as RFID. Supported by the ministry of education in Taiwan, we successfully designed and deployed RFID technology to the campus of a special education school at Chiayi in Taiwan. Though the technology was applied to eight different use case scenarios, we will focus on five of the more innovative ones in this work, including student temperature monitoring (STM), body weight monitoring (BWM), garbage disposal monitoring (GDM), mopping course recording (MCR), and campus visitor monitoring (CVM). Both active and passive tags and readers were employed to implement these five systems within the same campus. The benefits obtained from these systems by the students, teachers, and administrators were threefolds. First, student health monitoring through STM and BWM systems allowed the teachers and administration real-time control over changing health conditions that significantly affects such students. Second, course monitoring and recording through GDM and MCR allowed teachers to easily grasp and tune the learning curve of each student and also to implement a more guided training based on past learning efforts. EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS
NC CT

www.ncct.in
NC CT
VLSI & FPGA
Last but not least, campus safety monitoring through CVM allowed the administration to monitor the location of visitors in the campus and thus safeguard the students and teachers from dangerous or troublesome visitors. Novel techniques and creative methods were employed in the five systems, including temperature correction algorithm in STM, BMI-based weight tuning strategy in BWM, multiple route-tracking in GDM, learning improvement through history analysis in MCR, and face detection in CVM. The project was successfully deployed and is currently in use by the Chiayi School of Special Education which has more than 300 students and 150 administration staff and faculty. Tools used : Xilinx ISE Language FPGA : VHDL : SPARTAN 3AN (XC3S50AN)
SPARTAN 3AN KIT
NC CT

www.ncct.in

Abstracts - VLSI Projects 2010 - NCCT, Final Year Projects IEEE Projects

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Abstracts - VLSI Projects 2010 - NCCT, Final Year Projects IEEE Projects

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NC CT

Promise for the Best Projects

IEEE PROJECTS 2010-11

VLSI & FPGA

ALGORITHM OF BINARY IMAGE LABELING AND PARAMETER EXTRACTING BASED ON FPGA

Tools used Language FPGA

: Xilinx Platform Studio :C : SPARTAN 3 XC3S200

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

IMAGE EDGE DETECTION BASED ON FPGA

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

FPGA BASED REAL-TIME ADAPTIVE FUZZY LOGIC CONTROLLER

Tools used Language FPGA

: Xilinx Platform Studio :C : SPARTAN 3 XC3S200

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

RECOGNITION FPGA SYSTEM FOR DETECTION OF ANOMALIES IN MAMMOGRAMS

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

SORT OPTIMIZATION ALGORITHM OF MEDIAN FILTERING BASED ON FPGA

Compiler code : Verilog/VHDL

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

AN FPGA-BASED ARCHITECTURE FOR LINEAR AND MORPHOLOGICAL IMAGE FILTERING

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

DESIGN OF SHA-1 ALGORITHM BASED ON FPGA

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

HARDWARE REALIZATION OF SHADOW DETECTION ALGORITHM IN FPGA

Compiler code : Verilog/VHDL SPARTAN 3 EDK KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

RFID-BASED HOSPITAL REAL-TIME PATIENT MANAGEMENT SYSTEM

SPARTAN 3AN KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS

MICROCONTROLLERS * VLSI * DSP * MATLAB

IEEE PROJECTS 2010-11

VLSI & FPGA

SPARTAN 3AN KIT

EMBEDDED SYSTEMS PROJECTS / IEEE PROJECTS