LD Lab Manual 2011 Final

Logic Design Lab
2011-12
a. AND GATE (7408)
b. OR GATE(7432)
c. NOT GATE( 7404)
Dept. of ECE, CIT, Gubbi
Logic Design Lab
2011-12
Experiment No. 1: Verification of Logic Gates

Aim: To study and verify the truth table of logic gates. Apparatus required: IC Trainer Kit, patch chords, IC 7408, IC 7432, IC 7400,
IC 7402, IC 7404.
Procedure:
1. 2. 3. 4. 5. Place the IC on IC Trainer Kit. Connect VCC and ground to respective pins of IC Trainer Kit. Connect the inputs to the input switches provided in the IC Trainer Kit. Connect the outputs to the switches of O/P LEDs. Apply various combinations of inputs according to the truth table and observe condition of LEDs.
Theory:
1. BASIC GATES; a) AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is in low level when any one of the inputs is low. Symbol:
b) OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low. Symbol:
c) NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high. Symbol: A Y= A Y
Logic Design Lab
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d) NAND GATE (7400)
e) NOR GATE (7402)
f) EX-OR GATE (7486)
Logic Design Lab
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2. UNIVERSAL GATES: g) NAND GATE: The NAND gate is a compliment of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high. Symbol:
h) NOR GATE: The NOR gate is a compliment of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high. Symbol:
i) X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high. Symbol: A B Y
Result:
Logic Design Lab
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1) Y1= (A+BC)(B+A C ) Simplification: Y1= (A+BC)(B+A C ) = AB+ A C +BC = AB+ AC+ BC = AB . BC . AC Y1= ( A+BC)(B+ A C ) = (A+B)(A+C)(B+A)(A+ C ) = ( A C )( A B )( B C ) = ( A C ) + ( A B) + ( B C ) Using Basic Gates A B C A 0 0 0 0 1 1 1 1 Truth table B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y1 0 0 0 1 1 0 1 1 (Using only NOR gates) (Using NAND Gates) ( Given Expression) (Using basic gates)
Y1
Using only NAND gates A B C
Using only NOR gates A B C
Y
Y
Logic Design Lab
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Experiment No. 2: Simplification and Realization of Boolean Expression

Aim: Simplify and realize the given Boolean expressions using logic gates/universal
gates.
Apparatus required: IC Trainer Kit, patch chords, IC 7408, IC 7432, IC 7400,

IC 7402, IC 7404.
Procedure:
1. Fix the IC on the base board. 2. Connections are made as shown in the circuit Diagram. 3. Verify the truth Table for each expression.
Logic Design Lab
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2) Y=(A,B,C,D)= (5,7,9,11,13,15) Simplification: Y= ABCD+ABCD+ABCD+ABCD+ABCD+ABCD =ABD(C+C)+ABD(C+C)+ABD(C+C) =ABD+ABD+ABD =BD(A+A)+ABD =BD+ABD =D(B+AB) =D(A+B) =AD+BD Using Basic Gates
Using NAND gates
Using NOR gates
Truth table
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Simplification: 3) Q = AB + BC(B + C)
Using Basic gates:
Truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Q 0 0 0 1 0 0 1 1
Logic Design Lab
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Half Adder:
a) Half Adder using Basic gates A B
S= A B
C= AB
b) Half Adder using NAND Gates A
S=A B
B C=AB
Truth table A 0 0 1 1 B 0 1 0 1 SUM (S) 0 1 1 0 CARRY (C) 0 0 0 1
Logic Design Lab
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Experiment No 3: Half Adder & Full Adder

Aim: Realization of Half & Full adder using logic gates. Apparatus Required :
Sl no 1 2 Particulars IC 7400 7404,7486,7408 Quantity 3 1
Procedure:
1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on VCC and apply various combinations of input according to the truth table. 4. Note down the output readings for half & full adder (sum and carry bits) for different combinations of inputs.
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FULL ADDER:
a) Full Adder using Basic Gates
b) Full Adder using NAND Gates only
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Theory:
A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits. The drawback of this circuit is that in case of a multi bit addition, it cannot include a carry. A full adder is a logical circuit that performs an addition operation on three binary digits. The full adder produces a sum and carry value, which are both binary digits. It can be combined with other full adders or work on its own. K-Map Simplification 1) SUM
AB
C
00 0 1
01 1 0
11 0 1
10 1 0
0 1
SUM= S= A B C 2) CARRY
AB
C
00 0 0
01 0 1
11 1 1
10 0 1
0 1
C= AB+C(A B)
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Half Subtractor:
a) Half Subtractor using Basic gates A B
D= A B
B AB
b) Half Subtractor using NAND Gates A
D=A B
Bo = A B
Truth Table: A 0 0 1 1 B 0 1 0 1 Diff(D) 0 1 1 0 Borrow ( Bo ) 0 1 0 0
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Experiment No 4: Half Subtractor & Full Subtractor

Aim: Realization of Half & Full subtractor using logic gates. Apparatus Required :
Sl no 1 2 Particulars IC 7400 7432,7404,7486,7408 Quantity 3 1
Procedure:
a) Verify the gates. b) Make the connections as per the circuit diagram. c) Switch on VCC and apply various combinations of input according to the truth table. d) Note down the output readings for half & full subtractor (difference and borrow bits) for different combinations of inputs.
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Full Subtractor:
1. Full Subtractor using Basic Gates A B C
D= A B C
Bo=
A B+C(A B)
2. Full Subtractor using NAND Gates only A D= A B C B C Bo= A B+C(A B)
Truth Table: A 0 0 0 0 1 1 1 1 B C 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Diff 0 1 1 0 1 0 0 1 Borrow 0 1 1 1 0 0 0 1 B0= A B+C(A B)
Diff= A B C
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Theory:
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference) and B (borrow).
K-Map Simplification a) DIFFERENCE:

AB
C
00 0
0 0 0
Diff= A B C
b) BORROW:
AB
C
00 0
01
11 0
10 0 0
0 1
B0= A B+C (A B)
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PARALLEL ADDER/SUBTRACTOR Circuit

B3 B2 B1 B0
A3
A2
A1
A0
Ctrl =0 to add =1 to subtract
1 VCC 5 GND 12
10
16
11 13
IC 7483
14 15 2 6 9
Cin
Cout
S3
S2
S1
S0
Truth Table: Addition: Decimal Binary Equivalent no No. 1 A B A3 A2 A1 A0 9 5 1 0 0 1 12 8 1 1 0 0 Binary Equivalent No. 2 B3 B2 B1 B0 0 1 0 1 1 0 0 0 Output Sum Co 0 1 S3 1 0 S2 1 1 S1 1 0 S0 0 0
Subtraction: Decimal Binary Equivalent no No. 1 A B A3 A2 A1 A0 8 14 1 0 0 0 8 2 1 0 0 0 Binary Equivalent No. 2 B3 B2 B1 B0 1 1 1 0 0 0 1 0 Output Difference Co 0 1 S3 1 0 S2 0 1 S1 1 1 S0 0 0
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Experiment No. 5: Parallel Adder/ Subtractor

Aim: To Realize Parallel Adder / subtractor using IC7483 Apparatus Required:
Sl no 1 2 Particulars IC 7483 IC 7404 Quantity 1 1
Procedure:
1. Make the connections as shown in the fig. 2. For Addition make Cin=0 and apply 4 bits of i/p for A and apply another set of 4 bits to B. Observe the O/P at S3 S2 S1 S0 and Carry generated at Cout. Repeat the steps for different inputs and tabulate the results. 3. For Subtraction, Cin=1(A-B) By XOR-ing the i/p bits of B by1,1s complement of B is obtained. 4. Verify the difference at S0,S1,S2,S3 and Cout. If Cout is 1, difference is -ve and difference is in 2s complement. If Cout is 0, difference is +ve. e) Repeat the above steps and tabulate the result.
Block Diagram
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Circuit diagram for BCD to Excess-3 Code Conversion

B3 B2 B1 B0
E0 E1
E2
E3
Truth Table:
BCD to Excess-3
B3 0 0 0 0 0 0 0 0 1 1 BCD i/p B2 B1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 B0 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 Excess o/p E2 E1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0
Excess-3 to BCD
Excess i/p E3 E2 E1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 BCD o/p E0 B3 B2 B1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 B0 0 1 0 1 0 1 0 1 0 1
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Logic Design Lab
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Experiment No. 6: BCD TO EXCESS 3 AND EXCESS 3 TO BCD

Aim: To verify BCD to excess 3 code conversion using NAND gates. To study and verify the truth table of excess-3 to BCD code converter. Apparatus Required:
Sl no 1 2 Particulars IC 7486.7408,7404 IC 7432,7483 Quantity 1 1
Procedure:
1. Make the connections as shown in the fig. 2. Pin [14] of all ICS are connected to +5V and pin [7] to the ground. 3. The inputs are applied at E3, E2, E1, and E0 and the corresponding outputs at B3, B2, B1, and B0 are taken for excess 3 to BCD. 4. B3, B2, B1, and B0 are the inputs and the corresponding outputs are E3, E2, E1 and E0 for BCD to excess 3. 5. Repeat the same procedure for other combinations of inputs.
Theory:
In computing and electronic systems, binary-coded decimal (BCD) (sometimes called natural binary-coded decimal, NBCD) is an encoding for decimal numbers in which each digit is represented by its own binary sequence. Its main virtue is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations. Its drawbacks are the increased complexity of circuits needed to implement mathematical operations and a relatively inefficient encodingit occupies more space than a pure binary representation. To BCD-encode a decimal number using the common encoding, each decimal digit is stored in a four-bit nibble.
Decimal: BCD: 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001
Thus, the BCD encoding for the number 127 would be: 0001 0010 0111 Excess-3 is a non weighted code used to express decimal numbers. In XS-3, numbers are represented as decimal digits, and each digit is represented by four bits as the BCD value plus 3 (the "excess" amount). The primary advantage of XS-3 coding over BCD coding is that a decimal number can be nines' complemented (for subtraction) as easily as a binary number can be ones' complemented; just invert all bits.
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Circuit diagram for Excess-3 to BCD Code Conversion

E3 E2 E1 E0
B0 B1
B2
B3
K-map Simplification: a) BCD to Excess-3 Conversion

E3: B3+B2(B0+B1)
B1B0 B3B2
E2= B 2 (B0+B1)+B2 B1 B0
B1B0
00 00 01 11 10 0 0 X 1
01 0 1 X 1
11 0 1 X X
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B3B2
00 00 01 11 10 0 1 X 0
01 1 0 X 1
11 1 0 X X
10 1 0 X X 21
0 1 X X
Logic Design Lab
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E1= B 0 B1
B1B0 B3B2
E0= B0
B1B0
00 00 01 11 10 1 1 X 1
01 0 0 X 0
11 1 1 X X
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B3B2
00 00 01 11 X 10 1 1 1
01 0 0 X 0
11 0 0 X X
10 1 1 X X
0 0 X X
b) Excess-3 to BCD Conversion: B3= E2E3+E3E1E0

E1E0 E1E0 E3E2
B2=E2E1E0+ E 2 ( E1 + E 0 ) 11 0 0 X 1 10
E3E2
00 00 01 11 10 X 0 1 0
01 X 0 X 0
00 00 01 11 10 X 0 0 1 B0= E 0
01 X 0 X 1
11 0 1 X 0
10 X 0 X 1
X 0 X 0
B1=E0 E1
E1E0 E3E2 E1E0
00 00 01 11 10 X 0 0 0
01 X 1 X 1
11 0 0 X 0
10 X 1 X 1
E3E2
00 00 01 11 10 X 1 1 1
01 X 0 X 0
11 0 0 X 0
10 X 1 X 1
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Circuit diagram for BINARY to GRAY Code Conversion using X-OR gates
B3 B2 G3 G2
B1
G1
B0
G0
Truth Table: Binary i/p B3 B2 B1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Gray code o/p G2 G1 G0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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Experiment No. 7: BINARY TO GRAY AND GRAY TO BINARY

Aim: To verify Binary to gray conversion using EX-OR and Universal gates and to study and verify the truth table of Gray to Binary code converter. Apparatus Required:
. Sl no 1 Particulars IC 7486.7400 Quantity 1
Procedure:
1. Make the connections as shown in the fig. 2. Pin [14] of all ICS are connected to +5V and pin [7] to the ground. 3. The inputs are applied at G3, G2, G1, and G0 and the corresponding outputs at B3, B2, B1, and B0 are taken for Gray to Binary. 4. B3, B2, B1, and B0 are the inputs and the corresponding outputs
Theory:
This is a variable weighted code and is cyclic. This means that it is arranged so that every transition from one value to the next value involves only one bit change. The gray code is sometimes referred to as reflected binary, because the first eight values compare with those of the last 8 values, but in reverse order.
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Circuit diagram for BINARY to GRAY Code Conversion using NAND gates
Bo Go B1 G1 B2 G2 B3 G3
G3= B3
B1B0 B3B2 B1B0
G2= B2 B3 11 0 0 1 1 10 0 0 1 1 00 00 01 11 10 0 1 0 1 01 0 1 0 1 11 0 1 0 1 10 0 1 0 1
00 00 01 11 10 0 0 1 1
01 0 0 1 1
B3B2
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Circuit diagram for GRAY to BINARY Code Conversion using basic gates
G3 G2 B3 B2
G1
B1
G0
B0
Truth Table:
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GRAY i/p G2 G1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
G0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BINARY o/p B2 B1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1
B0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
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Circuit diagram for GRAY to BINARY Code Conversion using NAND gates
G0 Bo
G1 B1
G2 B2 G3 B3 K Map simplification: B3= G3

G1G0 G3G2 G1G0
B2= G2 G3 11 0 0 1 1 10 0 0 1 1 00 00 01 11 10 0 1 0 1 01 0 1 0 1 11 0 1 0 1 10 0 1 0 1
00 00 01 11 10 0 0 1 1
01 0 0 1 1
G3G2
B1= G1 G2 G3
G1G0
G1G0
B0= G0 G1 G2 G3 00 01 1 0 1 0 11 0 1 0 1 10 1 0 1 0 27
00
G3G2
01 11 0 1 0 1 1 0 1 0
10 1 0 1 0
G3G2
00 01 11 10
0 1 0 1
00 01 11 10
0 1 0 1
Logic Design Lab
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Multiplexer 74153:
1G 1 S1 2
1D3 1D2 1D1
3 4 5 6 7 8
7 4 1 5 3
16 15 14 13 12 11 10 9
Vcc 2G S0 2D3 2D2 2D1 2D0
1D0 1Y GND Truth Table:
2Y
Strobe(G) 1 0 0 0 0
S1 X 0 0 1 1
S0 X 0 1 0 1
Y L D0 D1 D2 D3
Multiplexer using NAND gates only S1 S0 Y= S1 S 0 D0+ S1 S0D1+S1 S 0 D2+S1S0D3
D0 D1 Y D2
D3 Truth Table: S1 0 0 1 1 S0 0 1 0 1 Y D0 D1 D2 D3
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Experiment No. 8: Multiplexer

Aim: To realize and verify the truth table of multiplexer using IC 74153 and NAND
gates.
Apparatus required:
Sl no 1 2 Particulars IC 7400,7420,74153 IC 7410 Range 1 Quantity 2 each 2
Procedure: a) IC 74153:
1. The Pin [16] is connected to + Vcc. 2. Pin [8] is connected to ground. 3. The inputs are applied either to A input or B input. 4. If MUX A has to be initialized, Ea is made low and if MUX B has to be initialized, Eb is made low. 5. Based on the selection lines one of the inputs will be selected at the output and thus the truth table is verified.
b) NAND gates:
1. Connections are made as shown in the Circuit diagram. 2. Change the values of the inputs as per the truth table and note down the outputs
Theory:
In electronics, a multiplexer or mux is a device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select bits, which are used to select which input line to send to the output. An electronic multiplexer can be considered as a multiple-input, single-output switch. An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal. An electronic multiplexer can be considered as a multiple-input, single-output switch.
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Demultiplexer 74139:
1G 1 1S0 2 1S1 3 1Y0 1Y1 1Y2 1Y3 GND Truth Table: G S1(A) S0(B) 1 X X 0 0 0 0 0 1 0 1 0 0 1 1 Y0 1 0 1 1 1 Y1 1 1 0 1 1 Y2 1 1 1 0 1 Y3 1 1 1 1 0 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc 2G 2S0 2S1 2Y0 2Y1 2Y2 2Y3
7 4 1 3 9
Demultiplexer using NAND gates only:

A B Y0= A+B Y1= A+ B Y0 Y1 Y2 Y3 Truth Table: Select Lines A B 0 0 0 1 1 0 1 1 Outputs Y1 Y2 1 1 0 1 1 0 1 1 Y2= A +B Y3= A + B
Y0 0 1 1 1
Y3 1 1 1 0
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Experiment No. 9: Demultiplexer

Aim: To realize and verify the truth table of demultiplexer using IC 74139 and NAND
gates.
Apparatus required:
Sl no 1 2 Particulars IC 7400,7420,74139 IC 7410 Range 1 Quantity 2 each 2
Procedure: 1. IC 74139:
1. The inputs are applied to either a input or b input 2. The demux is activated by making Ea low and Eb low. 3. The truth table is verified.
2. NAND gates:
1. Connections are made as shown in the Circuit diagram. 2. Change the values of the inputs as per the truth table and note down the outputs
Theory:
In electronics, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end. An electronic demultiplexer can be considered as a single-input, multiple-output switch.
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Half Adder using 74153
Full Adder using 74153
`
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Experiment No. 10: Half/Full Adder Using IC 74153

Aim: To realize half Adder and Full Adder using IC 74153. Apparatus required:
Sl No 1 Particulars IC 74153,7404 Quantity 1 Each
Procedure: (IC 74153)

1. The Pin [16] is connected to + Vcc. 2. Pin [8] is connected to ground. 3. The inputs are applied either to A input or B input. 4. In case of half adder using MUX, sum and carry is obtained by applying a constant inputs at 1D0, 1D1, 1D2, 1D3 and 2D0, 2D1, 2D2 and 2D3 and the corresponding values of select lines are changed as per table and the output is taken at 1Y as sum and 2Y as carry. 5. In full adder using MUX, the input is applied at A, B and C. According to the table corresponding outputs are taken at S and CY.
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Half Subtractor using 74153
Full Subtractor using 74153
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Experiment No. 12: Half/Full Subtractor Using IC 74153

Aim: To realize half Subtractor and Full Subtractor using IC 74153. Apparatus required:
Sl No 1 Particulars IC 74153,7404 Quantity 1 Each
Procedure: (IC 74153)

1. The Pin [16] is connected to + Vcc. 2. Pin [8] is connected to ground. 3. The inputs are applied either to A input or B input. 4. In case of half Subtractor using MUX, difference and borrow is obtained by applying a constant inputs at 1D0, 1D1, 1D2, 1D3 and 2D0, 2D1, 2D2 and 2D3 and the corresponding values of select lines are changed as per table and the output is taken at 1Y as difference and 2Y as borrow. 5. In full Subtractor using MUX, the input is applied at A, B and Bin. According to the table corresponding outputs are taken at diff and borrow.
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Circuit Diagram:
Gnd
2G 2A
7 4 1 3 9 2B
1Y 0 1 Y1 1Y 2 1Y 3 G0
B0 B1
Gnd
2G 2A
7 4 1 3 9 2B
2Y 0 2 Y1 2Y 2 2Y3 G1
B2
Gnd
1G 1A
7 4 1 3 9 1B
1Y 0 1 Y1 1Y 2 1Y3 G2
B3
G3
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Experiment no. 13: Binary To Gray Code Conversion Using 74139 Decoder
Aim: To perform the following code conversions using 74139 Decoder BCD to GRAY
code
Apparatus required:
Sl no 1 Particulars IC 74139.7400 Range Quantity 1
Procedure:
1. Connections are made as shown in circuit diagram 2. Truth Table is verified for different combinations of input
Truth Table Binary i/p B3 B2 B1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Gray code o/p G2 G1 G0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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a) One Bit Comparator using XOR Gate and Basic Gate s

AB
b) One Bit Comparator using NAND Gates

A A>B A=B AB 0 0 1 0
AB A B
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Experiment No. 13: Comparators

Aim: To verify the truth table of one bit and two bit comparators using logic gates. Apparatus Required:
Sl no 1 2 Particulars IC 7400,7404,7408 IC 7402,7432,7486 Quantity 2 each 1 each
Procedure:
1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Applying inputs check for the corresponding outputs. 4. The Outputs are verified.
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2-Bit Comparator:
Truth Table:
I/p O/p A1 A0 B1 B0 AB 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0
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K-map Simplification:
1) AB B1B0
A1A0
00 00 01 11 10 0 1 1 1
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0
AB ((A<B)+(A=B))
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4-Bit Comparator using IC 7485

B3 (A<B)in 1 2 3 16 Vcc A3 B2 A2 A1 B1 A0 B0
(A=B)in VCC 4 (A>B)in (A>B)out (A=B)out (A<B)out Gnd
5 6 7 8
I C 7 4 8 5
15 14 13 12 11 10 9
Example:
Let A= 1000 and B=1010 Here A3=1, A2=0, A1=0,A0=0 and B3=1, B2=0,B1=1, B0=0 Output: (A<B) is high, other two outputs are low
8-Bit Comparator using Two 7485:
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Experiment No. 14: Magnitude Comparator Using IC 7485

Aim: To compare two 4-Bit and 8-Bit data using IC 7485 Apparatus required:
Sl no 1 Particulars IC 7485 Quantity 1
Procedure:
1. Connections are made as shown in the circuit diagram 2. Supply voltage of 5 V is applied between Vcc and Gnd 3. The 3rd pin (A=B) in is Connected to Vcc 4. The 2nd and 4th pin (A>B)in and (A<B)in are connected to Gnd 5. Truth Table is verified for different combinations of input
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Circuit Diagram of 7-Segment Display:
True table of BCD Seven Segment Decoder & display

INPUTS B1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 a 0 1 0 0 1 0 1 0 0 0 1 0 0 0 1 b 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 c 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 OUTPUTS d 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 e 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 f 0 1 1 1 0 0 0 1 0 0 1 0 1 0 0 g 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 Display
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Experiment No. 15: Use of Decoder Chip to Drive LED Display

Aim: To conduct a suitable experiment to display the given data using 7-Segment LED
decoder driver using IC 7447
Apparatus required:
Sl no 1 Particulars IC 7447 Quantity 1
Procedure:
1. Fix the IC into the IC base Board 2. Connections are made as shown in the circuit diagram 3. Truth Table is verified for various input combinations.
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Decimal to BCD conversion using IC 74147

4 5 6 7 8 A2 A1 Gnd 1 2 3 4 5 6 7 8 16 Vcc 0 A3 3 2 1 9 A0
I C 7 4 1 4 7
15 14 13 12 11 10 9
Truth Table:
INPUTS 4 5 H H H H H H H H L H X L X X X X X X X X OUTPUTS A2 A1 H H H H H L H L L H L H L L L L H H H H
0 H X X X X X X X X X
1 H L X X X X X X X X
2 H H L X X X X X X X
3 H H H L X X X X X X
6 H H H H H H L X X X
7 H H H H H H H L X X
8 H H H H H H H H L X
9 H H H H H H H H H L
A3 H H H H H H H H L L
A0 H L H L H L H L H L
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Experiment No. 16: Priority Encoder

Aim: Realize a suitable circuit to convert decimal to BCD using IC 74147 Apparatus required:
Sl No 1 Particulars IC 74147 Quantity 1
Procedure:
1. Connection are made as shown in circuit diagram. 2. Truth table is verified.
Theory:
A priority encoder is a combinational circuit with of the inputs and outputs. Each
inputs is assigned a priority. The most significant bit of the input has the bits of the
highest priority while the least significant bit has the lowest priority. The
output are the binary index of the non-zero input bit with highest priority, all input bits with lower priority will be ignored. For example, when and , the behavior
of the priority encoder can be described as the following truth table:
Priority encoders are typically used when multiple components (e.g., processor, memory, I/O devices, etc.) are to share a common resource (e.g., a bus). Each component is Assigned a certain priority according to its nature, so that whenever there is a conflict, the component with the highest priority will be granted the usage of the resource.
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Circuit Diagram:
Master
r
Slave
Q
Clk
K
Q
Clr
Truth Table:
Mode Async hronous preset 0 1 1 Synch ronous 1 1 1 Clear 1 0 1 1 1 1 Jn Kn Clock Qn+1 X X 0 0 1 1 X X 0 1 0 1 0 0 1 0 Qn 0 1 Qn Qn 1 0 1
Qn
Status Set Reset No Change Reset Set Toggle
1 0 Qn
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Logic Design Lab
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Experiment No. 17: Flip-Flops

Aim: a) Rig up a Master Slave J-K Flip-Flop and verify its Truth Table.
b) Rig up a T & D Flip-Flop using Master Slave J-K Flip-Flop and verify its Truth table
Apparatus required:
Sl No 1 2 Particulars IC 7410 Ic 7400 Quantity 2 1
Procedure:
1. Connections are made as shown in circuit diagram 1, 2 and 3. 2. Suitable truth tables are verified. Theory: In digital circuits, a flip-flop is a term referring to an electronic circuit (a bistable multivibrator) that has two stable states and thereby is capable of serving as one bit of memory. Master-Slave JK Flip-flop The Master-Slave Flip-Flop is basically two JK bistable flip-flops connected together in a series configuration with the outputs from Q and Q from the "Slave" flip-flop being fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop as shown below. Master-Slave JK Flip-Flops
The input signals J and K are connected to the "Master" flip-flop which "locks" the input while the clock (Clk) input is high at logic level "1". As the clock input of the "Slave" flip-flop is the inverse (complement) of the "Master" clock input, the outputs from the
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D- FlipFlop:
Master
r
Slave
Q
Clr
Clk
Truth Table:
preset
Clear 1 1
Dn 0 1
Clock
Qn+1 0 1
Qn 1
1 1
1 0
Status Reset Set
T Flip Flop:
Master
Pr
Slave
Q
Q Clr
Clk
Truth Table:
preset
Clear 1 1
Tn 0 1
Clock High High
Qn+1 Qn
Qn
Qn 1 Qn
Status NC Toggle
1 1
Qn
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"Master" flip-flop are only seen by the "Slave" flip-flop when the clock input goes "LOW" to logic level "0". Therefore on the "High-to-Low" transition of the clock pulse the locked outputs of the "Master" flip-flop are fed through to the JK inputs of the "Slave" flip-flop making this type of flip-flop edge or pulse-triggered. Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock signal. D-FlipFlop: The D type flip-flop has only one input (D for Delay or Data) apart from the clock. The INDETERMINATE state is avoided with this flip-flop. When the clock goes high, D (a 0 or a 1) is transferred to Q. When the clock goes low, Q remains unchanged. Q stores the data until the clock goes high again, when new data may be available. T-FlipFlop: T(Toggle)-flip-flop toggles (Q changes state) when T is high. T acts as an ENABLE / INHIBIT control.
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Circuit Diagram of 3-Bit Asynchronous UP Counter:

QA Vcc Vcc PRE J Q J PRE Q J PRE Q QB QC
Clk
Clk
Clk
Clk
K Clr Vcc
K Clr
K
Clr
Truth Table:
Clock QC 0 0 1 0 2 0 3 0 4 1 5 1 6 1 7 1 8 0 QB 0 0 1 1 0 0 1 1 0 QA 0 1 0 1 0 1 0 1 0
Wave Forms:
Clk 0 1
QA
QB QC
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Experiment No. 18: Asynchronous Up/Down Counter Using 7476

Aim: 1) Rig up a 3-bit Asynchronous UP counter.
2) Rig up a 3-bit Asynchronous DOWN counter. 3) Rig up a Mod N counter
Apparatus required:
Sl No 1 Particulars IC 7476 Quantity 2
Procedure:
1. Connections are made as shown in circuit diagram. 2. Clock pulses are applied one by one at the clock i/p and the o/p is observed at QA, QB and QC. 3. Truth table is verified. 4. Continuous clock pulses are applied. 5. Waveforms at QA, QB and QC are observed on CRO.
Theory:
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of designs exist, Example:
y Asynchronous (ripple) counter changing state bits are used as clocks to
subsequent state flip-flops

y Synchronous counter all state bits change under control of a single clock
Result:
Truth Table is verified Fclk =.. FQA=. FQB=. FQC=.
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Circuit Diagram: 3 Bit Asynchronous DOWN Counter

Clk
Clk
Clk
Clk
K Clr Vcc
K Clr
K
Clr
Truth Table: Clock QC 0 1 1 1 2 1 3 1 4 0 5 0 6 0 7 0 8 1 QB 1 1 0 0 1 1 0 0 1 QA 1 0 1 0 1 0 1 0 1
Wave Forms:
Clock
QA
QB
QC
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Circuit Diagram: Mod 5 Counter

Clk
Clk
Clk
Clk
K
Clr
K
Clr
K Clr
Truth Table:
Clock QC 0 0 1 0 2 0 3 0 4 1 5 0 QB 0 0 1 1 0 0 QA 0 1 0 1 0 0
Wave Forms:
Clk
QA
QB QC
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Circuit Diagram: Mod 4 Down Counter:

QA QB QC
Vcc PRE J Q J PRE Q J PRE Q
Clk
Clk
Clk
Clk
K Clr
K Clr
K
Clr
Vcc
Truth Table:
Clock QC 0 1 1 1 2 1 3 1 4 1 QB 1 1 0 0 1 QA 1 0 1 0 1
Waveforms:
Clock
QA
QB
1 1 0
QC
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Circuit Diagram: Decade Counter 7490

Vcc QA QA QB QC
5 I/p A Clk 14
12
11
Mod 2
Mod5
10
1 2 I/p B R1
3 R2
6 S1
7 S2
Mode 8 Counter using 7490

Vcc QA QA QB QC
5 I/p A Clk 14
12
11
Mod 2
Mod5
10
1 2 I/p B R1
3 R2
6 S1
7 S2
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Experiment No. 19: Counter

Aim: Rig up Mod N Counter using 7490 Apparatus: Sl No 1 Procedure: 1. Connections are made as shown in the circuit diagram 2. Clock pulses are applied one by one at the i/p and the o/p is observed at QA, QB QC and QD. 3. Truth Table is verified. 4. Continuous clock pulses are applied. 5. Waveforms QA, , QB QC and QD are observed on CRO. Particulars IC 7490 Quantity 1 No
Result: 1) Fclk=.. 2) FQA= 3) FQB=. 4) FQC=. 5) FQD=..
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Truth Table:
Decade Counter Clock QD QC 0 0 0 1 0 0 2 0 0 3 0 0 4 0 1 5 0 1 6 0 1 7 0 1 8 1 0 9 1 0 10 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 Clock 0 1 2 3 4 5 6 7 8 Mod 8 Counter QD 0 0 0 0 0 0 0 0 0 QC 0 0 0 0 1 1 1 1 0 QB 0 0 1 1 0 0 1 1 0 QA 0 1 0 1 0 1 0 1 0
Waveforms for Mod 10 Counter:
0 0 0 0
1 0
0 1 0 0
1 1
0 0
1 0
0 1
1 1
0 0
1 0
0 0
0 0
0 0
1 0
1 0
1 0
1 0
0 1
0 1
0 0
Waveforms for Mod 8Counter:

Clk QA QB 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0
QC QD
0 0
0 0
1 0
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Circuit Diagram: Count from 3 to 8

Preset Value=3, N=6
16 Clk i/p Vcc 5 4 Vcc Count up
7 QD
6 QC
2 QB
3 QA 11
74193
Count Down
Load
8 14 Clear Borrow 13 Carry12 NC NC
DATA I/P 9
10
1 15 1
(0 1)=3
Truth Table:
Clock 0 1 2 3 4 5 6 QD 0 0 0 0 0 1 0 QC 0 1 1 1 1 0 0 QB 1 0 0 1 1 0 1 QA 1 0 1 0 1 0 1
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Experiment No. 20: Programmable 4 Bit Synchronous Up/Down Counter (Binary Counter)
Aim: Rig up a MOD N Synchronous Up/Down Counter using 74193 & 74192 Apparatus required:
Sl No 1 Particulars IC 74193,7400.7432 Quantity 1
Procedure:
1) Connections are made as shown in the circuit diagram with the load pin open 2) The Preset value is made available at the data inputs C,B and A. 3) The Load pin is made low so that the preset value appears at QD, QC, QB and QA 4) Now connect the o/p of the gate to the load i/p. 5) Clock pulses are applied and the truth table is verified. 6) Continuous clock pulses are applied.
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Preset value=12, N=8
16 Vcc Vcc Clk Count up 5 Count Down 4
7 QD QC
6 QB
2 QA
74193
Load
11
8 Clear 14 Borrow 13 NC NC Carry 12 DATA I/P D C B A 9 (1

10
1 15 0 0)=12
Truth Table:
Clock 0 1 2 3 4 5 6 7 5 QD 1 1 1 1 1 0 0 0 1 QC 1 0 0 0 0 1 1 1 1 QB 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0
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Preset Value=5, N=4
16 Clk i/p Vcc Vcc Count up 5 Count Down 4
7 QD QC
6 QB
2 QA
Load
11
74192
8
Borro NC
13 NC
Truth Table:
Clock 1 2 3 4 5 QD 0 0 0 1 0 QC 1 1 1 0 1 QB 0 1 1 0 0 QA 1 0 1 0 1
Clear 14
Carry 12
DATA I/P D C B A 9 (0
10
15
1 0
1)=5
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Preset value=8 , N=6
16 Vcc Vcc Clk Count up 5 Count Down 4
7 QD QC
6 QB
2 QA
74192
Load
11
8 Clear 14 Borrow 13 NC NC Carry 12 DATA I/P D C B A 9 (1

10
1 15 0 0)=8
Truth Table:
Clock 0 1 2 3 4 5 6 7 5 QD 1 1 1 1 1 0 0 0 1 QC 1 0 0 0 0 1 1 1 1 QB 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0
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Circuit Diagram of 3-Bit synchronous Counter:

QA Vcc QB QC
Vcc JA
PRE QA JB
PRE QB JC
PRE QC
Clk
Clk
Clk
KA Clr Vcc
QA
KB Clr
QB
KC Clr
QC
Clk Truth Table:
Clock QC 0 0 1 0 2 0 3 0 4 1 5 1 6 1 7 1
QB 0 0 1 1 0 0 1 1
QA 0 1 0 1 0 1 0 1
Wave Forms:
Clk 0 1 0 1
QA
QB QC
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Experiment No. 21: 3 BIT SYNCHRONOUS COUNTER

Aim: 1) To design and test a 3 bit synchronous counter using 7476 Apparatus: Sl No 1 Procedure: 1. Connections are made as shown in the circuit diagram 2. Clock pulses are applied one by one at the clock i/p and the o/p is observed at QA, QB and QC. 3. Truth table is verified 4. Continuous clock pulse are applied. 5. Waveforms at QA, QB and QC are observed on CRO Result: Truth Table is verified 1) Fclk =.. 2) FQA= 3) FQB= 4) FQC= Fclk =.. 2
Fclk =.. 4 Fclk =.. 8
Particulars IC 7476,7408
Quantity 1 Each
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State Diagram: 000 111 001
110
010 101 100
011
Excitation Table: State Change From 0 0 1 1 To 0 1 0 1 J-K Input J 0 1 X X K X X 1 0
Transition Table: Present State QC 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 QC 0 0 0 1 1 1 1 0 Next State QB 0 1 1 0 0 1 1 0 QA 1 0 1 0 1 0 1 0 0 0 0 1 X X X X JC KC X X X X 0 0 0 1 JB 0 1 X X 0 1 X X KB X X 0 1 X X 0 1 JA 1 X 1 X 1 X 1 X KA X 1 X 1 X 1 X 1
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Karnaugh Map to derive the flipflop input function: JA:

QAQB QC
KA:
QAQB
00 0 1 1 1
01 X X
11 X X JA=1
10 1 1
QC
00 0 1 X X
01 1 1
11 1 1 KA=1
10 X X
QAQB QAQB QC
00 0 1 0 0
01 1 1 JB=QA
11 X X
10 X X
QC
00 0 1 X X
01 X X
11 1 1 KB=QA
10 0 0
QAQB QC
QAQB
00 0 1 0 X
01 0 X
11 1 X
10 0 X
QC
00 0 1 X 0
01 X 0
11 X 1
10 X 0
JC=QB.QA
KC=QB.QA
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Circuit Diagram for serial in serial Out (SISO):
vcc
Serial Input
14 1
7495
Clock 9 13 12 11 10 7
6 M=0
QA
QB
QC
QD
Truth Table: Clock 1 2 3 4 5 6 7 Serial DO = 0 D1 = 1 D2 = 1 D3 = 1 X X X QA 0 1 1 1 X X X QB X 0 1 1 1 X X QC X X 0 1 1 1 X QD X X X 0 = D0 1 = D1 1 = D2 1 = D3
Circuit Diagram for serial in serial Out (SIPO/Right Shift):
vcc
Serial Input
14 1
7495
Clock 9 13 12 11 10 7
6 M=0
QA
QB
QC
QD
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Experiment No. 22: SHIFT REGISTERS

Aim: To conduct an experiment to perform the following operations on a given 4 bit data using IC 7495. i. SISO, ii. Right shift/SIPO, iii. PIPO, iv. PISO, v. left shift , vi, Ring counter Procedure: i) Serial In Serial Out: (SISO) 1. Connection is made as shown in the circuit diagram. 2. The shift register is loaded with 4 bits of data one by one serially. 3. At the end of the 4th clock pulse the first data do appears at QD. 4. Another clock pulse is applied; the second data d1 appears at QD. 5. Another clock pulse is applied; the third data d2 appears at QD. 6. Application of next clock pulse will enable the fourth data d3 to appear at QD. Thus the data applied serially at the input comes out serially at QD. ii) Right shift/Serial In Parallel Out (SIPO): 1. Connections are made as shown in the circuit diagram. 2. The data is applied at the serial input. 3. One clock pulse is applied at 1 (Right shift) and this data is observed at QA. 4. The next data is applied at serial input. 5. One more clock pulse is applied at clock 1 and it is observed that the data on QA will shift to QB and the new data applied will appear at QA. 6. Step 2 and 3 are repeated till all the 4 bits of data are entered one by one into the shift register.
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Truth Table for SIPO: Clock 1 2 3 4 Serial Data QA DO = 0 D1 = 1 D2 = 1 D3 = 1 0 1 1 1 QB QC X 0 1 1 X X 0 1 QD X X X 0 = D0
Circuit diagram for Parallel in Parallel Out: (PIPO)

A B C D
vcc
14 6 M=1
7495
Clock 8 13 12 11 10 7
Truth Table for PIPO:

Mode
1
QA
QB
QC
QD
Clock
1
Parallel data input A B C

1 0
A
D
1
C D
Parallel data output QA QB QC

1 0 1
QD
1
1
B
Circuit diagram for Parallel in Parallel Out: (PISO)
vcc
14 6 M=
9 Clock 8 13
7495
12 11 10 7
Mode=1 for Parallel loading Mode=0 for serial shifting
QA
QB
QC
QD
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iii) Parallel in serial Out: (PIPO): 1. Connections are made as shown in the circuit diagram. 2. The 4 bit data is applied at A, B, C & D. 3. Keeping the Mode control M =1, one clock pulse is applied. The data applied at A, B, C & D will appear at QA, QB, QC, & QD respectively. iv) Parallel in serial Out: (PISO): 1. Connections are made as shown in the circuit diagram. 2. The 4 bit data is applied at A, B, C & D. 3. Keeping the Mode control M =1, one clock pulse is applied. The data applied at A, B, C & D will appear at QA, QB, QC, & QD respectively. 4. Keeping the Mode control M = 0, clock pulse are applied one by one and data arriving out serially at QD is observed. Note: Mode = 1 for Parallel loading. Mode = 0 for serial shifting. v) Procedure for Left shift: 1. Connections are made as shown in the circuit diagram. 2. Apply the first data at D and apply one clock pulse. This data appears at QD. 3. Now the 2 nd data is made available at D and one clock pulse is applied. The data appears at QD to QC and new data appears at QD. 1.Step 3 is repeated until all the bits are entered one by one. 2. At the end of 4th clock pulse 4 bits are available at QA, QB, QC and QD.
.
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Truth Table for PISO:

Mode
1 0 0 0
Clock
1 2 3 4
Parallel data input A

1 X X X
Parallel data output C

1 X X X
B
0 X X X
D
1 X X X
QA
1 X X X
QB
0 1 X X
QC
1 0 1 X
QD
1 1 0 1
Data comes out serially at QD. Circuit diagram for Left Shift :
Serial I/P D M=1 6 8 9 5 4 7495 10 11 12 13 C 3 B 2 A
Clock 1
QD
QC
QB
QA
Note: Give Pin No.7 to Ground and Pin No.14 to Vcc. Truth Table for Left Shift:
Mode Clock Serial data Parallel data output input
1 1 1 1 1 2 3 4 1 0 1 1
QA
X X X 1
QB
X X 1 0
QC
X 1 0 1
QD
1 0 1 1
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vii) Ring Counter: 1. Connections are made as shown in the circuit diagram. 2. The data 1 0 0 0 is applied at A B C D respectively. 3. Keeping the mode M = 1, one clock pulse is applied. 4. Keeping the mode M = 0, one clock pulse are applied one by one and truth table is verified.
Circuit diagram for Ring Counter:

D C C B
6 8
2 1 13
7495
10 11 12
Clock 1
Serial I/P QD QC QB QA
Truth Table: Mode 1 0 0 0 0 0 Clock 1 2 3 4 5 6

QA QB QC QD
1 0 0 0 1
0 1 0 0 0
0 0 1 0 0
0 0 0 1 0
Repeated
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Basic Structure of a Sequence Generator:

NEXT STATE DECODER
QN-1 QN-2 Serial i/p Sequence=1001011,
Q1
Q0 Clk
SHIFT REGISTER Sequence Length=7
QA Mode 6 13
QB
QC 11
QD 10 14 Vcc=5V
12
7495
Clock Serial i/p 8 A B C Inputs 7 D
QA
1 0 0 1 0 1 1
QB
1 1 0 0 1 0 1 1
QC
1 1 1 0 0 1 0 1 1 1
QD
1 1 1 1 0 0 1 0 1
Y
0 0 1 0 1 1 1
QAQB
QcQD
00 00 01 11 X 10 X X 1
01 X X 1 0
11 1 0 X X
10 X X 0 1
Y= QB QC
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Logic Design Lab
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Experiment No. 23: SEQUENCE GENERATOR

Aim: Design of a sequence Generator using IC 7495 Procedure: 1) Make connections as per the cicuit diagram 2) By keeping the mode=1. Load the input through A,B,C,D as 1111 by giving one clock pulse 3) For count mode make mode=0 And observe the sequence at QA,QB,QC and QD.
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Additional Experiment
A combinational logic circuit has TWO control inputs C1, C2 and Two data inputs A , B and one output Y. the circuit performs one of the logic operations AND, OR,EQU(equivalence) or XOR(exclusive or) on the two inputs. The function performed depends on the control inputs,
C! C2 Function performed By circuit 0 0 OR 0 1 XOR 1 0 AND 1 1 EQU Design the Circuit with minimum number of Gates.
Solution: Procedure to be followed to design the required circuit. 1. 2. 3. 4. Get the truth table. Get switching equation from the truth table. Simplify the switching equation using K-map. Realize the simplified equation using basic gates.
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APPENDIX A PIN DETAILS:

I NAND I N
A A
A A A
A
A
A A A
Y A
Y A
7411
A A
Triple 3 - Input AND Gate
7413
Dual 4-Input NAND Schmitt Trigger
7420
1A 1B NC 1C 1D 1Q Gnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 2A 2B NC 2C 2D 2Q
Dual 4 - Input NAND Gate

Inputs A X X X 0 1 B X X X 1 C X 0 X 1 D 0 X X X 1 Out put Y 1 1 1 1 0
I A X X 0 1
Out put C 0 X X 1 Y 0 0 0 1
X 0 X 1
A B C
Symbol
Y = A.B.C
7427
Triple 3 - Input NOR Gate

Inputs Out put C 0 1 0 1 0 1 0 1 Q 1 0 0 0 0 0 0 0
7432
1A 1B 2A 2B 2C 2Q Gnd
1 2 3 4 5 6 7
7 4 2 7
14 13 12 11 10 9 8
VCC 1C 1Q 3A 3B 3C 3Q
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
1A 1B 1Q 2A 2B 2Q Gnd
1 2 3 4 5 6 7
7 4 3 2
A B C Symbol
A B Symbol
Y = A+B 0 1 2 3 4
Y = A+B+C
in configuration
in configuration
in configuration
in configuration
A
B C D
Quad 2 - Input NOR Gate 7447(OC)
14 13 12 11 10 9 8
VCC 4A 4B 4Q 3A 3B 3Q
In p u ts Outt pu A 0 0 1 B 0 1 0 Y 0 1 1
D1 D2 LT B1 /RB0 RB1 D3 D0 Gnd
1 2 3 4 5 6 7 8
in configuration
1A 1B NC 1C 1D 1Q Gnd
1 2 3 4 5 6 7
7 4 1 3
14 13 12 11 10 9 8
VCC 2D 2C NC 2B 2A 2Q
7 4 2 0
0 X
in configuration
Y = A.B.C.D Symbol
BCD to 7 - Segment Decoder

a f g b
7 4 4 7
16 15 14 13 12 11 10 9
VCC f g a b c d e
d c
I /p
I n p u ts
D3 D2 D1 D0 LT RBI BI/RB0 Q x x x x 0 x 1 8
x x x x x x 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 1 x x x 0 1 1 1 0 1 2
1 1 1 1 x 1 OC: Open Collector
5 6 7 8 9 10 11 12 13 14 15
00))2(
N I
AND
e 3 10)( '
v ` YXWVU 'X0)'X& ' e! st r e vvu EA6D A5@9 8 E @f i YXWVU
Y A
Y A
NAND
`!
q (p2 (p
#H FTSRQPFI#HG #F d ! c ! b ! ee% iEAiE h9 8 gf

S I
A
$#" ! ! ! $#" v 3 v
#H FTSRQPFI#HG #F 3 ! ( 00))2 10)( ' &!&% EA6D CB A5@9 8 7654 ` YXWVU X0&YYXe '(2 e2 'X0)'X& ' 3! st 3 r 00))( 2 10)( ' 3! vvu EA6D A5@9 8 7654 a ` YXWVU
$#" ! 3 $#" 3
3 ( 00))2 10)( ' q (p2 (p 10)( '
E A6D
RHTGHv #yx vx #HFTSRQPFI#HG #F ! t s ! r ! vvu iEAiE h9 9w iE hf i 8 gf
#H FTSRQPFI#HG #F ! st r ! ee% A5@9 8 7654 ! v ! vu ` H t s r
$#" ! ! !
$#" ! ! $#" ! v
O/p
15
83
Logic Design Lab
2011-12
7474
u al
Fl i f lo
7476
u a l J K Fli flo
7483
wit
P re e t &
lear
wit P re e t & l e a r
ull 4 it F Adder
Ou t u t
In u t
Out u t Q Q 1 0 0 1 1 1 0 1
0
1 1
NO ANGE
1 1
1 1
0 1
1 1
V S2
Pin configuration
1 1 1 1
X
X
1 1
0 TO E GG
Pin configuration
S Pre et lear
Pre Pre et lr lear
7485
4 it om arator
7486
1 2 3 4 5 6 7
Quad 2 In ut EX O Gate
V 4A 4 4Q 3A 3 3Q
7490
A ync ronou
ecade u
A2 A1
1
A0
0
Pin configuration
A
Y A+ Symbol
7493
A ync ronou
inary 4 it ounter
7495
4 it S ift egi t er w Parallel IN O T it ig t eft S ifting
02
x x
NOTE S ifting left require external connection ofQ to A,Q to ,Q to and erial data i entered at
In u t
Ou t u t
x x 1 1
ext
ext in t
1 1
Q Gnd
x 0 1
Pin configuration
1 1
0 x
x
0
Gnd
xx
7 4 1 2 1
S A0 A1 MS A2 E2 E3 E1 Q7
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1 2
A0 x x x 0 1 0 1 0 1 0 1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1E 1A0 1A1 1Q0 1Q1 1Q2 1Q3 Gnd
1 2 3 4 5 6 7 8
7 4 1 3 9
16 15 14 13 12 11 10 9
Vcc 2E 2A0 2A1 2Q0 2Q1 2Q2 2Q3
In ut
A S EN A1 A0
1 0 0 0 0 x x 0 0 1 1 0 1 0 1
Pin configuration
l q ~l
Q N A1 A2
1 2 3 4 5 6 7
14 13 12 11 10 9 8
V N N
A1 A2 0 x
Q 0
Q 1
In E nab le V E E E 1 2 3 Q x 1 x 7 Q x x 1 4 Q 0 x x 1 Q 1 0 0 3 Q 1 0 0 8 Q5 1 0 0 Q 1 0 0 1 0 0 1 0 0 Pin configuration 1 0 0 1 0 0
ut A d dre A2 A1 x x x x x x 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
74121
Mono table Multivibrator w S mitt Trigger it
74138
3 it inary ecoder emultiflexer, Inverting
74139
ecoder
Pin configuration
Pin configuration
N V N N
zw y r w
01
7 4 9 3
S Mode Gnd
7 4 9 5
1 1 1 0
lk 1
lk x x
Sin x x x 1 x
A x x Q x x
x x Q x x
r w
zw y
lk 2
1 2 3 4 5 6 7
14 13 12 11 10 9 8
lk 1 N Q0 Q3 Gnd Q1 Q2
Sin MS A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
V QA MS Q Q Q S lk lk
In ut
Out ut Parallel QA 0 A 0 1 0 Q
lk
Q 0
F unction
x x Q x x
x x 1 x x
No
0 0 0
0 0 0
1 0 0
ange oad S ift eft S ift ig t No ange
u a l 2 it in a ry e m u lti l e x e r In v e rtin g
Ou t ut
Q0
Q1 Q2 Q3
r q r w r x n
rr zw yx uur zw xy nr
w m
Pin configuration
r q zw y r rq zw y r xrx w l ~l
r r
w w
A< IN A IN A> IN A> O T A OT A< O T Gnd
7 4 8 5
V A3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
7 4 8 6
In u t A 0 0 1 1
Out ut Y 0 1 1 0
lk 2
01 02
0 1 0 1
N V S9 1 S9 2
1 2 3 4 5 6 7
7 4 9 0
14 13 12 11 10 9 8
Pin configuration
r r
xx u q qr
} l ~l
1A 1 1Q 2A 2 2Q Gnd
14 13 12 11 10 9 8
lk 1 N Q0 Q3 Gnd Q1 Q2
n r mm r
NO ANGE NO ANGE NO ANGE
0 1
w x w
3 2
po
1 lk 1D 1 V 2 2D 2 lk
1 2 3 4 5 6 7
7 4 7 4
14 13 12 11 10 9 8
1S 1Q 1Q Gnd 2Q 2Q 2S
S 0 1 0
1 0 0
K Q Q x x 1 0 x x 0 1 x x 1 1
1 lk 1Pre 1 lr 1J V 2 lk 2 Pre 2 lr
1 2 3 4 5 6 7 8
7 4 7 6
16 15 14 13 12 11 10 9
lr K 1K P re 1Q 0 1 x 1 0 x 1Q Gnd 0 0 x 2K 1 1 0 2Q 1 1 2Q 1 1 2J
J K x x x x x x
A4 S3 A3
A2
1 2 3 4 5 6 7 8
7 4 8 3
16 15 14 13 12 11 10 9
Pin configuration
w rr w
vu o l ~l
} ||
n r mmq po r ppoo xx r r t vu s l kjihgf
r xux r q qr
{ zw y { zwm y { zw y zwm y w zzw yy w
dd
r e
S4 YO YI Gnd
1
A1
S1
ounter
84
Logic Design Lab
2011-12
74147
Binar Deci al to BCD Priority Encoder

D4 D5 D6 D7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC D0 Q3 D3 D2
74148
3-Bit Binary Priority Encoder
74151
8:1 Data Selector ultiplexer with Strobe
D1 D9 Q0
Pi
fi ur ti
Pin confi uration
Pin confi uration
0 x 0 1 x 1
CE 0 x 1 0 0 0 0
Pin confi uration C 0 0 0 0 0 0
0 1 x 0 0
Pin confi uration
74192
Synchronous Deci al Up/down Counter with Preset & Clear

1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC D0 Clr C D C U S D2 D3
74193
Synchronous Binary 4-Bit Up/down Counter with Preset & Clear

D1 Q1 Q0 1 2 3 4 5 6 7 8
74266 (OC 1A 1B 1Q 2Q 2A 2B Gnd 1 2 3 4 5 6 7
Quad 2 - Input EX - NOR Gate

14 13 12 11 10 9 8 VCC 4A 4B 4Q 3Q 3A 3B
Q2 Q3 Gnd
Cl -D Cl -U Q2 Q3 Gnd
Pin configuration
Clr 1 0 0 0 0 0 0 0 S x 0 1 1 1 1 1 1
CD 4011
1A 1B 1Q
Q 2 - Input N D Gate uad AN

1 2 3 4 5 6 7
CD 4093
1A 1B 1Q 2Q 2B 2A Gnd 1 2 3 4 5 6 7
2Q 2B 2A Gnd
4 0 1 1
14 VDD 13 4A 12 4B 11 4Q 10 3Q 9 3B 8 3A
Inputs Out put A 1 x 0 B 1 0 x Y 0 1 1
Pin configuration
In puts
Outputs C l U C l D Q3 Q2 Q1 Q0 C U CYD x x 0 0 0 0 1 1 x x L o ad 1 1 C o un t U p 1 1 1 C o un t D o w n 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1
Outputs Clr S Cl U Cl D Q3 Q2 Q1 Q0 CYU CYD x 0 0 0 0 1 1 1 x x x L o ad 1 1 0 0 x Count Up 0 1 1 1 1 0 1 1 C ount D ow n 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1
D1 Q1 Q0 Cl -D Cl -U
7 4 1 9 2
7 4 1 9 3
Pin configuration
16 15 14 13 12 11 10 9
VCC D0 Clr CYD CYU S D2 D3
7 4 2 6 6
Pin configuration
A B
In puts
Y = A+ B
Symbol
741
NC Inv Non-Inv
1 2 3 4
Q 2 - Input N D Schimtt Trigger uad AN

14 13 12 11 10 9 8 VDD 4A 4B 4Q 3Q 3B 3A
-VCC
7 4 1
4 0 9 3
555
Gnd Trigger Input Output
1 2 3 4
Reset Pin configuration
5 5 5
Pin confi uration
0 1 x 1 1
Inputs Out put

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1
OC: Open Collector
Op - Amp
8 7 6 5
NC +VC C Output NC
8 7 6 5
+VCC Discharge Threshold Control Voltage
Outputs S S LU /D C l Q3 Q2 Q1 Q0 1 0 0 0 0 0 x x L oad 0 x x o Change 1 Count U p 1 0 1 1 Count D ow n 1 0 0 0 1 0 1 0 0 1 1 0
In puts
7 4 1 5 3
1S R (MSB S1 1D3 1D2 1D1 1D0 1Q Gnd
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Out Inputs VCC put 2S R S R A1 A0 Q S0(LSB 1 x x 0 2D3 0 0 0 D0 2D2 0 0 1 D1 2D1 0 1 0 D2 2D0 0 1 1 D3 2Q
1SELA/B 1A 1B 1Q 2A 1D0 1Q Gnd
1 2 3 4 5 6 7 8
7 4 1 5 7
16 15 14 13 12 11 10 9
VCC E 4A
Inputs
Out put
SL 4B E 4Q 1 x 3A 0 0 3B 0 0 3Q
A B
Q x x 0
CE SELU/D Q2 Q3 Gnd
74153
Dual 4:1 Data Selector Multiplexor with Strobe
74157
Quad 2:1 Data 74190 Selector/Multiplexer

D1 Q1 Q0
Synchronous Deci al Up/down Counter with Preset 7 4 1 9 0

16 15 14 13 12 11 10 9 VCC D0 Cl RC C S D2 D3
1 2 3 4 5 6 7 8
RC
1 1 1 1 1 1
T im er
D8 Q2 Q1 Gnd
E Q2 Q1 Gnd
Q Q E Gnd
7 4 1 4 7
D4 D5 D6 D7
1 2 3 4 5 6 7 8
7 4 1 4 8
16 15 14 13 12 11 10 9
VCC FQ GS D3 D2 D1 D0 Q0
D3 D2 D1 D0
1 2 3 4 5 6 7 8
7 4 1 5 1
16 15 14 13 12 11 10 9
VCC D4 D5
E A2 A1 A0 Q 1 x x x 1 D0 D6 1 D1 D7 0 0 1 0 D2 A 0(LSB - - - - - - - - A1 A2(MSB - - - - 0 1 1 1 D7
Output Q 1 D0 D1 D2 D7
85
Logic Design Lab
2011-12
APPENDIX B VIVA QUESTIONS: 1. What are Analog Systems? Give Examples. 2. What are Digital Systems? Give Examples.
3. Mention the disadvantages of Analog systems over Digital systems? 4. Explain Boolean Algebra? 5. State Principle of Duality? 6. State Demorgans Law? 7. Define Positive Logic and Negative Logic. 8. Define Literal. 9. Define MINTERM, MAX TERM. 10. Define a complementary function 11. Explain Shannons reduction theorem 12. Which are the basic gates, universal gates 13. Define combinational network with example 14. Define Sequential Network with example 15. Define Double-Rail and Single -Rail logic 16. When a Boolean Expression is called completely specified? 17. Explain the significance of a Dont care function 18. Explain the criteria of minimality. 19. Define implies, Subsumes, implicants. 20. What are Prime Implicants? 21. What is irredundant disjunctive normal formula? 22. What is an implicate? 23. What is a MAP? 24. Explain the significance of Map 25. What is a minimal Sum, Minimal product? 26. Explain Quine mccluskey method 27. Explain VEM method of reduction 28. Explain Binary Adder, Subtractor 29. Explain various scales of integration 30. Define carry look ahead Adder 31. Define Comparator
86
Logic Design Lab
2011-12
32. Define Decoder 33. Define Encoder 34. Give an example for Min term generator 35. Give an example for Max term generator 36. Define priority encoder 37. Explain Multiplexing action 38. Define PAL, PLA and PROM 39. Differentiate between ROM and RAM 40. What is a Memory? 41. What is internal state and secondary state? 42. What is Flip Flop, Latch 43. Explain Basic Bi stable element 44. What is a meta stable state? 45. Define setting and clearing in terms of flip-flop 46. Explain SR Latch 47. Give an application of SR Latch 48. Explain gated SR Latch, gated D Latch 49. Explain Timing Diagram 50. Explain Propagation Delay in gates 51. Explain set and hold time in latches 52. Explain Master-Slave Flip-Flops 53. Explain the significance of edge-triggering 54. Explain Data Lock Out 55. Give the characteristic equations of JK, D and T Flip Flops. 56. Define Registers with examples 57. Define Counters with example 58. Explain ripple counter, asynchronous , synchronous counter 59. Explain Race around condition 60. List the basic logic series 61. Explain Semiconductor diode behavior. 62. What is saturating Logic? 63. Explain Fan-Out and Fan-in in gates
87
Logic Design Lab
2011-12
Question Bank
1. Simplify and realize the given Boolean Expression using Basic Logic gates and verify the truth table ( two expressions to be given) 2. Simplify and realize the given Boolean Expression using Universal Gates and verify the truth table ( two expressions to be given) 3. Realise and verify the truth table of a full adder and half adder using XOR and basic gates 4. Realise and verify the truth table of a full Subtractor and Half Subtarctor using XOR and basic gates 5. Realise and verify the truth table of a full adder and half adder using NAND gates only 6. Realise and verify the truth table of a full subtractor and half subtractor using NAND gates only 7. Conduct a suitable experiment on 7483 IC to realize the following operation on the given 4 bit data a) Addition b) 2s Complement subtraction 8. Conduct an experiment to convert the given BCD data to excess-3 code using minimum number of basic gates 9. Conduct an experiment to convert the given excess-3 data to BCD using minimum number of basic gates 10. Realise using XOR gates and verify the truth table of 11. a) Binary to gray converter b) Gray to Binary Converter (use basic gates) 12. Realise using XOR gates and verify the truth table of a) Binary to gray converter (use NAND gates only) 13. Realise using XOR gates and verify the truth table of 14. a) Gray to Binary Converter (use NAND gates only) 15. Conduct an experiment to verify the TT of IC 74153 Mux and realize a Half/full 16. adder circuit 17. Conduct an experiment to verify the TT of IC 74153 Mux and realize a Half/full subtractor circuit 18. Conduct an experiment to verify the TT of IC 74139 decoder and realize a Binary to gray code converter 19. Realize a two bit comparator using basic gates only
88
Logic Design Lab
2011-12
20. Realize a two bit comparator using NAND gates only 21. Realize a 8 Bit comparator using IC 7485 22. Conduct a suitable experiment to display the given data using 7-segment LED Decoder Verify the truth table of a given Priority encoder(IC 74147) Realise and verify the truth Table of Master Slave JK Flip Flop using NAND gates Realise and verify the truth Table of Master Slave D Flip Flop using NAND gates Realise and verify the truth Table of Master Slave T Flip Flop using NAND gates
23. 24.
25.
26.
27. Realise a 3-bit binary asynchronous up counter using IC 7476 (N<=7) and verify its truth table 28. Realise a 3-bit binary asynchronous down counter using IC 7476 (N<=7) and verify its truth table 29. Realise a Mod N binary synchronous counter using 7476 and verify the truth table 30. Realise a Modulo N counter using 7490, Write down the expected functional table and verify its truth table and also display the waveform. 31. Realise a Modulo N counter using 74192 with a given preset value and verify its truth table (N, preset value to be specified N<=10). Display the waveform 32. Realise a Modulo N counter using 74193 with a given preset value and verify its truth table (N, preset value to be specified N<=15). Display the waveform 33. Use IC 7495 Shift registers to display the following operations 34. a) SIPO b) SISO c) PIPO
35. Use IC 7495 Shift registers to display the following operations 36. a) Shift Left b) Right Shift c) Ring Count
37. Design and realize a sequence generator for the sequence.
89

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Logic Design Lab

a. AND GATE (7408)

c. NOT GATE( 7404)

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Experiment No. 1: Verification of Logic Gates

Dept. of ECE, CIT, Gubbi

Logic Design Lab

d) NAND GATE (7400)

e) NOR GATE (7402)

f) EX-OR GATE (7486)

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Using only NAND gates A B C

Using only NOR gates A B C

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Experiment No. 2: Simplification and Realization of Boolean Expression

Apparatus required: IC Trainer Kit, patch chords, IC 7408, IC 7432, IC 7400,

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Using NAND gates

Using NOR gates

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Using Basic gates:

Dept. of ECE, CIT, Gubbi

Logic Design Lab

b) Half Adder using NAND Gates A

Truth table A 0 0 1 1 B 0 1 0 1 SUM (S) 0 1 1 0 CARRY (C) 0 0 0 1

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Experiment No 3: Half Adder & Full Adder

Dept. of ECE, CIT, Gubbi

Logic Design Lab

b) Full Adder using NAND Gates only

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Truth Table: A 0 0 1 1 B 0 1 0 1 Diff(D) 0 1 1 0 Borrow ( Bo ) 0 1 0 0

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Experiment No 4: Half Subtractor & Full Subtractor

Dept. of ECE, CIT, Gubbi

Logic Design Lab

2. Full Subtractor using NAND Gates only A D= A B C B C Bo= A B+C(A B)

Truth Table: A 0 0 0 0 1 1 1 1 B C 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Diff 0 1 1 0 1 0 0 1 Borrow 0 1 1 1 0 0 0 1 B0= A B+C(A B)

Dept. of ECE, CIT, Gubbi

Logic Design Lab

K-Map Simplification a) DIFFERENCE:

Dept. of ECE, CIT, Gubbi

Logic Design Lab

PARALLEL ADDER/SUBTRACTOR Circuit

Ctrl =0 to add =1 to subtract

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Experiment No. 5: Parallel Adder/ Subtractor

Dept. of ECE, CIT, Gubbi

Logic Design Lab

Circuit diagram for BCD to Excess-3 Code Conversion

Dept. of ECE, CIT, Gubbi