Fixed Point Routines

AN617
Fixed Point Routines

Author: Frank J. Testa FJT Consulting
FIXED POINT ARITHMETIC

Unsigned xed point binary numbers, A, can be represented in the form
n1
INTRODUCTION
This application note presents an implementation of the following xed point math routines for the PICmicro microcontroller families: Multiplication Division Routines for the PICmicro microcontroller families are provided in a variety of xed point formats, including both unsigned and signed twos complement arithmetic.
A =
k=0
a( k) 2
n1 kr
= 2
k=0
a ( k ) 2,
where n is the number of bits, a(k) is the kth bit with a(0) = LSb, and r indicates the location of the radix point. For example, in the case where A is an integer, r = 0 and when A is a fraction less than one, r = n. The value of r only affects the interpretation of the numbers in a xed point calculation, with the actual binary representation of the numbers independent of the value of r. Factoring out of the above sum, it simply locates the radix point of the representation and is analogous to an exponent in a oating point system. Using the notation Qi.j to denote a xed point binary number with i bits to the left of the radix point and j to the right, the above n-bit format is in Qn-r.r. With care, xed point calculations can be performed on operands in different Q formats. Although the radix point must be aligned for addition or subtraction, multiplication provides an illustrative example of the simple interpretive nature of r. Consider the unsigned product of a Q20.4 number with a Q8.8. After calling the appropriate unsigned 24x16 bit multiply for these xed point arguments, the 40-bit xed point result is in Q28.12, where the arguments of the Q notation are summed respectively. Similar arguments can be made for twos complement arithmetic, where the negative representation of a positive number is obtained by reversing the value of each bit and incrementing the result by one. Producing a unique representation of zero, and covering the range -2n-1 to 2n-1 - 1, this is more easily applied in addition and subtraction operations and is therefore the most commonly used method of representing positive and negative numbers in xed point arithmetic. The above analysis in Q notation can be employed to build dedicated xed point algorithms, leading to improved performance over oating point methods in cases where the size of the arguments required for the range and precision of the calculations is not large enough to destroy gains made by xed point methods.
1996 Microchip Technology Inc.
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FIXED POINT FORMATS
The xed point library routines supports 8-,16-, 24- and 32-bit formats in the combinations shown in Table 1. These general format combinations are implemented in both signed and unsigned versions. Additional unsigned routines are implemented with arguments reduced by one bit to accommodate the case of operations on signed numbers, with arguments known to be nonnegative, thereby, resulting in some performance improvement.
TABLE 1:
FIXED POINT LIBRARY ROUTINE SUMMARY TABLE

Format Multiplication Library Names Format
Division Library Names PIC16C5X/PIC16CXXX Routines FXD0808S, FXD0808U, FXD0807U, FXD0707U FXD1608S, FXD1608U, FXD1607U, FXD1507U FXD1616S, FXD1616U, FXD1515U FXD2416S, FXD2416U, FXD2315U FXD2424S, FXD2424U, FXD2323U FXD3216S, FXD3216U, FXD3115U FXD3224S, FXD3224U, FXD3123U FXD3232S, FXD3232U, FXD3131U PIC17CXXX Functions FXD0808S, FXD0808U, FXD0807U, FXD0707U FXD1608S, FXD1608U, FXD1607U, FXD1507U FXD1616S, FXD1616U, FXD1615U, FXD1515U FXD2416S, FXD2416U, FXD2415U, FXD2315U FXD2424S, FXD2424U, FXD2423U, FXD2323U FXD3216S, FXD3216U, FXD3215U, FXD3115U FXD3224S, FXD3224U, FXD3223U, FXD3123U FXD3232S, FXD3232U, FXD3231U, FXD3131U
8/8 16/8 16/16 24/16 24/24 32/16 32/24 32/32
FXM0808S, FXM0808U, FXM0807U FXM1608S, FXM1608U, FXM1607U, FXM1507U FXM1616S, FXM1616U, FXM1515U FXM2416S, FXM2416U, FXM2315U FXM2424S, FXM2424U, FXM2323U FXM3216S, FXM3216U, FXM3115U FXM3224S, FXM3224U, FXM3123U FXM3232S, FXM3232U, FXM3131U
8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32
8/8 16/8 16/16 24/16 24/24 32/16 32/24 32/32
FXM0808S, FXM0808U FXM1608S, FXM1608U FXM1616S, FXM1616U FXM2416S, FXM2416U FXM2424S, FXM2424U FXM3216S, FXM3216U FXM3224S, FXM3224U FXM3232S, FXM3232U
8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32
Note: U - unsigned math operation, S - signed math operation
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DATA RAM REQUIREMENTS
Table 2 shows the contiguous data RAM locations that are used by the library.
TABLE 2:
AARGB7 AARGB6 AARGB5 AARGB4 AARGB3 AARGB2 AARGB1 AARGB0 AEXP SIGN FPFLAGS BARGB3 BARGB2 BARGB1 BARGB0 BEXP TEMPB3 TEMPB2 TEMPB1 TEMPB0 = = = =
DATA RAM REQUIREMENTS

REMB3 REMB2 REMB1 REMB0
remainder MSB
AARG MSB AARG exponent sign exception flags and option bits
BARG MSB BARG exponent
temporary storage
These denitions are identical with those used by the IEEE 754 compliant oating point library[5], AN575.
USAGE
Multiplication assumes the multiplicand in AARG, multiplier in BARG, and produces the result in AARG. Division assumes a dividend in AARG, divisor in BARG, and quotient in AARG with remainder in REM.
EXAMPLE 1:
TWO BYTE ADDITION/SUBTRACTION ROUTINES

MOVF ADDWF MOVF BTFSC INCFSZ ADDWF AARGB1,W BARGB1 AARGB0,W _C AARGB0,W BARGB0 AARGB1,W BARGB1 AARGB0,W _C AARGB0,W BARGB0
ADD
ADDITION/SUBTRACTION
Because of the generally trivial nature of addition and subtraction, the call and return overhead outweighs the need for explicit routines and so they are not included in the library. However, the PIC16C5X/PIC16CXXX families do not have an add with carry or subtract with borrow instruction, leading to subtleties regarding production of a correct carry-out in a multiple byte add or subtract. In the case of a two byte add or subtract, the most elegant solution to these difculties, requiring 6 cycles, appears to be given by the following code in Example 1.
SUB
MOVF SUBWF MOVF BTFSS INCFSZ SUBWF
The four instructions after the initial add/subtract, can be easily concatenated for operations involving more than two bytes. Because addition and subtraction are required in standard algorithms for multiplication and division, these issues permeate the implementation of both xed and oating point algorithms for the PIC16C5X/PIC16CXXX families.
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MULTIPLICATION
The existing library of xed point math routines for the PICmicro families of microcontrollers contains multiplication routines in the following format combinations: The signed xed point multiply routines require proper handling of the fact that the 8x8 hardware multiply is unsigned. It can be proven (see Appendix C) that the product of signed numbers in twos complement representation can be obtained by computing their product as if they were unsigned and for each negative argument, subtract the opposite argument from the most signicant bits of the product. In most cases, the optimal algorithm is to simply apply this at the end of the corresponding unsigned method to achieve the signed product. The implementation for the PIC16CXXX family uses a standard sequential add-shift algorithm, negating both factors if BARG < 0, to produce the positive multiplier required by the method. Analogous to simple longhand binary multiplication, the multiplier bits are sequentially tested, with one indicating an add-shift and zero simply a shift. The shift is required to align the partial product for the next possible add[1]. Two examples are shown in Example 2.
8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32
The xed point multiply routine FXMxxyy, takes an xx-bit multiplicand in AARG, a yy-bit multiplier in BARG and returns the (xx+yy)-bit product in AARG. For the PIC17 family, both unsigned and signed algorithms use extended precision application of the 8x8 hardware multiply currently available. The essence of an extended precision interpretation is to view each argument as a concatenation of bytes of different orders of magnitude and evaluate the product by evaluating all 8x8 terms in the algebraic expansion. For example, the 24x16 multiply yields a 40-bit product and contains 6 individual 8x8 terms in its expansion. (AARGB0216+AARGB128+AARGB220) (BARGB028+BARGB120) = AARGB0BARGB0224 +
EXAMPLE 2:
MULTIPLICATION EXAMPLES
= FXM2416S(-4123006,24715) = 0xE84647F896 = -101900093290
FXM2416S(0xC11682,0x608B)
FXM1616U(0x0458,0x822C) = FXM1616U(1112,33324) = 0x02356F20 = 37056288
AARGB2BARGB120
(AARGB1BARGB1+AARGB2BARGB0)28 +
(AARGB0BARGB1+AARGB1BARGB0)216 +
This is completely analogous to arithmetic in base 28 = 256, where the respective digit products must be aligned according to their orders of magnitude before summation. It is important to note that no carryout beyond the sum of the lengths of the arguments can occur[1]. This fact is helpful in constructing algorithms for cases with a large number of terms. For example, the 32x16 case containing 8 individual 8x8 terms, can be viewed as a 24x16 product between the 3 least signicant bytes of AARG with BARG, producing no carryout, followed by augmentation with the remaining two terms. This philosophy has been applied in optimizing the unsigned algorithms, using the shorter products as building blocks for the larger ones.
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Table 3 shows PIC17CXXX Fixed Point multiplication performance data. The listed routines can be found in Appendix F.
TABLE 3:
Routine
PIC17CXXX FIXED POINT MULTIPLY PERFORMANCE DATA

Max Cycles 14 9 24 15 42 29 59 43 84 68 76 57 111 93 148 128 Min Cycles 14 9 21 15 34 29 49 43 72 68 64 57 97 93 132 128 Average Cycles 14 9 23 15 38 29 54 43 78 68 70 57 104 93 140 128 Program Memory 10 5 20 11 38 25 55 39 80 64 72 53 107 89 144 124 Data Memory 3 3 4 4 8 7 10 8 12 12 12 9 15 15 18 18
FXM0808S FXM0808U FXM1608S FXM1608U FXM1616S FXM1616U FXM2416S FXM2416U FXM2424S FXM2424U FXM3216S FXM3216U FXM3224S FXM3224U FXM3232S FXM3232U
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Table 4 shows the PIC16C5X/PIC16CXXX Fixed Point Multiply performance data. The listed routines can be found in Appendix D.
TABLE 4:
Routine
PIC16C5X/PIC16CXXX FIXED POINT MULTIPLY PERFORMANCE DATA

Max Cycles 91 76 70 110 129 86 284 259 247 353 328 321 533 497 481 440 415 395 656 620 587 841 794 787 Min Cycles 9 57 51 11 61 27 11 110 105 132 113 108 241 258 230 48 116 111 253 201 255 411 443 392 Average Cycles 85 74 67 85 105 64 235 214 205 281 260 248 432 401 390 327 304 291 502 470 457 686 645 631 Program Memory 33 21 23 44 31 35 74 58 63 92 70 76 126 98 107 98 84 91 152 151 129 189 168 168 Data Memory 5 4 4 7 7 7 9 9 9 12 12 12 13 13 13 9 9 9 15 15 15 17 17 17
FXM0808S FXM0808U FXM0707U FXM1608S FXM1608U FXM1507U FXM1616S FXM1616U FXM1515U FXM2416S FXM2416U FXM2315U FXM2424S FXM2424U FXM2323U FXM3216S FXM3216U FXM3115U FXM3224S FXM3224U FXM3123U FXM3232S FXM3232U FXM3131U
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DIVISION
The xed point divide routine FXPDxxyy, takes an xx-bit dividend in AARG, a yy-bit divisor in BARG and returns the xx-bit quotient in AARG and yy-bit remainder in REM. Unlike multiplication, division is not deterministic, requiring a trial-and-error sequential shift and subtract process. Binary division is less complicated than decimal division because the possible quotient digits are only zero or one. If the divisor is less than the partial remainder, the corresponding quotient bit is set to one followed by a shift and subtract. Otherwise, the divisor is greater than the partial remainder, the quotient bit is set to zero and only a shift is performed. The intermediate partial remainder may be restored at each stage as in restoring division, or corrected at the end as in nonrestoring division. Implementation dependent trade-offs between worst case versus average performance affect the choice between these two approaches, and therefore, macros for each method are provided. Note: A test for divide by zero exception is not performed and must be explicitly provided by the user.
AARG = BARG QUOTIENT + REMAINDER,
The results of the division process for AARG/BARG, satisfy the relation
where the remainder has the same sign as the quotient, and represents the fraction of the result in units of the denominator BARG. Some simple examples are given in Example 3.
EXAMPLE 3:
DIVISION EXAMPLES
FXD1608S(0xC116,0x60) = 0xFF59, 0xB6 FXD1616U(0x9543,0x4AA1) = 0x0002, 0x0001
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Table 5 shows the PIC17CXXX Fixed Point Divide performance data. The listed routines can be found in Appendix G
TABLE 5:
Routine
PIC17CXXX FIXED POINT DIVIDE PERFORMANCE DATA

Max Cycles 91 78 69 64 162 196 133 128 219 247 188 182 315 352 283 275 387 422 352 344 415 468 375 368 514 566 476 466 610 665 567 558 Min Cycles 85 74 69 64 44 170 133 128 200 227 182 177 291 342 272 266 361 415 344 337 382 459 363 357 477 553 459 451 572 650 555 547 Average Cycles 89 77 69 64 156 183 133 128 211 244 184 179 305 347 277 270 377 419 347 341 400 463 369 362 496 560 465 457 593 655 560 552 Program Memory 77 74 65 60 146 195 129 124 241 243 216 218 353 453 339 330 482 577 460 448 476 608 451 442 639 769 612 600 800 930 773 758 Data Memory 4 3 3 3 5 4 4 4 7 6 6 6 8 8 8 8 10 10 9 9 9 9 8 8 11 11 10 10 13 13 12 12
FXD0808S FXD0808U FXD0807U FXD0707U FXD1608S FXD1608U FXD1607U FXD1507U FXD1616S FXD1616U FXD1615U FXD1515U FXD2416S FXD2416U FXD2415U FXD2315U FXD2424S FXD2424U FXD2423U FXD2323U FXD3216S FXD3216U FXD3215U FXD3115U FXD3224S FXD3224U FXD3223U FXD3123U FXD3232S FXD3232U FXD3231U FXD3131U
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Table 6 shows the PIC16C5X/PIC16CXXX Fixed Point Divide performance data. The listed routines can be found in Appendix E.
TABLE 6:
Routine
PIC16C5X/PIC16CXXX FIXED POINT DIVIDE PERFORMANCE DATA

Max Cycles 131 103 91 83 181 297 177 169 334 376 292 447 524 402 570 641 520 584 694 534 747 853 692 909 1012 851 Min Cycles 36 95 91 83 49 237 177 169 302 316 277 408 504 382 528 624 502 67 671 509 695 830 668 855 990 828 Average Cycles 109 102 91 83 159 269 177 169 315 371 280 427 510 388 549 630 508 561 680 518 722 838 676 885 998 836 Program Memory 41 15 21 44 67 41 41 44 74 27 45 140 172 120 253 226 211 201 243 160 280 299 232 357 364 304 Data Memory 5 4 4 4 6 7 5 5 8 7 7 8 8 7 12 13 12 10 9 9 11 11 10 13 13 13
FXD0808S FXD0808U FXD0807U FXD0707U FXD1608S FXD1608U FXD1607U FXD1507U FXD1616S FXD1616U FXD1515U FXD2416S FXD2416U FXD2315U FXD2424S FXD2424U FXD2323U FXD3216S FXD3216U FXD3115U FXD3224S FXD3224U FXD3123U FXD3232S FXD3232U FXD3131U
REFERENCES
1. 2. 3. 4. 5. Cavanagh, J.J.F., Digital Computer Arithmetic, McGraw-Hill,1984. Hwang, K., Computer Arithmetic, John Wiley & Sons, 1979. Scott, N.R., Computer Number Systems & Arithmetic, Prentice Hall, 1985. Knuth, D.E., The Art of Computer Programming, Volume 2, Addison-Wesley, 1981. F.J.Testa, IEEE 754 Compliant Floating Point Routines, AN575, Embedded Control Handbook, Microchip Technology Inc., 1995.
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APPENDIX A: ALGORITHMS
Several algorithms for decimal to binary conversion are given below. The integer and fractional conversion algorithms are useful in both native assembly as well as high level languages.
A.2
Fractional conversion algorithm[3]:
Given a fraction F, where d(k) are the bit values of its n bit binary representation with d(1) = MSB,
A.1
Integer conversion algorithm[3]:
F =
k=1
d( k) 2
Given an integer I, where d(k) are the bit values of its n- bit binary representation with d(0) = LSB,
n1
k=0 F(k) = F
I =
k=0
d( k) 2
while k <= n d(k) = F(k) 2 F(k+1) = fractional part of F(k) 2 k = k + 1 endw
k=0 I(k) = I while I(k) = ! 0 d(k) = remainder of I(k)/2 I(k+1) = I(k)/2 k = k + 1 endw where denotes the greatest integer function (or ceiling function).
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APPENDIX B: FLOWCHARTS
FIGURE B-1: MULTIPLICATION FLOWCHART FOR PIC16CXX
FXMxxU FXMxxS
i=0 clear high order partial product
i=0 clear high order partial product
multiplier bit i = 1? No
Yes
multiplier < 0?
Yes
No add multiplicand to high order partial product
negate multiplier and multiplicand save sign of result
right shift partial product i=i+1
multiplier bit i = 1? No
Yes
add multiplicand to high order partial product
Yes i < n? right shift partial product with sign extension i=i+1
No
Return and indicate no error
Yes i < n - 1?
No
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FIGURE B-2: MULTIPLICATION FLOWCHART FOR PIC17CXXX
FXMxxU
FXMxxS
Compute, add aligned byte products of AARG * BARG
Compute, add aligned byte products of AARG * BARG
AARG < 0?
Yes
No
subtract BARG from most signicant bytes of product
Yes BARG < 0?
No
subtract AARG from most signicant bytes of product
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FIGURE B-3: DIVISION FLOWCHART
FXDxxS
FXDxxU
A
left shift (remainder, quotient)
i=0 clear remainder partial quotient = dividend
compute sign of quotient
Yes No i < n? No Yes Return and indicate no error left shift (remainder, quotient) dividend < 0? subtract division from partial remainder Yes negate divisor divisor < 0?
subtract divisor from partial remainder
Yes result > 0?
No partial quotient LSb = 1
No negate dividend restore partial quotient, LSb = 0
Yes result > 0? i=0 clear remainder partial quotient = dividend
No
restore partial quotient, LSb = 0
restore partial quotient, LSb = 0
Yes i < n - 1?
No
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APPENDIX C:
Consider arguments to a twos complement multiply expressed in the form
A = am 1 2 + Au ,
B = bn 1 2 + Bu
m1
where
Au
i=0
n1
ai 2
Bu
i=0
bi 2
Then with being the unsigned product of the twos complement representations and the correction term c given by Case 1:
p = A
B = p A u B u
p + c
c am 1 bn 1 2
m+n
m n am 1 Bu 2 + bn 1 Au 2 }
am 1 = bn 1 = 1
For this case with both arguments negative we obtain where and yielding the bounds The bounded quantity can then be expressed in the form where is the result of truncating the above bounded quantity to m+n bits. This gives the nal value for the correction term in the form where the term has been cancelled by the carry during the evaluation of leading to the result Case 2:
m n Bu 2 + Au 2 } n1 n 2 Bu < 2 c = 2
m+n
m1
2 Bu 2 + Au 2 < 2 m n Bu 2 + Au 2 Bu 2 + Au 2 2
m n m+n
m+n
Au < 2
m
m n m+n+1
Tu < 2
m+n
+ Tu
c = T u 2
m+n
Bu 2 + Au 2
p = p + c = p Tu am 1
bn 1
= 0
The case with one or both arguments positive gives the simpler result where and therefore a carry out is not possible.
m n c = a m 1 Bu 2 + bn 1 Au 2 } c <2
m+n
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Please check the Microchip BBS for the latest version of the source code. For BBS access information, see Section 6, Microchip Bulletin Board Service information, page 6-3.
APPENDIX D: MULTIPLY ROUTINES FOR THE PIC16C5X/PIC16CXXX

Table of Contents for Appendix D D.1 32x32 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 15 D.2 32x24 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 37 D.3 32x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 55 D.4 24x24 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 69 D.5 24x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 85 D.6 16x16 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 97 D.7 16x8 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines ........................................................................ 108 D.8 8x8 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines .......................................................................... 116
D.1
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
32x32 PIC16C5X/PIC16CXXX Fixed Point Multiply Routines

RCS Header $Id: fxm22.a16 2.3 1996/10/16 14:23:23 F.J.Testa Exp $ $Revision: 2.3 $ 32x32 PIC16 FIXED POINT MULTIPLY ROUTINES Input: fixed point arguments in AARG and BARG
Output: product AARGxBARG in AARG All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed multiply application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine FXM3232S FXM3232U FXM3131U Clocks 889 856 836 Function 32x32 -> 64 bit signed fixed point multiply 32x32 -> 64 bit unsigned fixed point multiply 31x31 -> 62 bit unsigned fixed point multiply
The above timings are based on the looped macros. If space permits, approximately 128-168 clocks can be saved by using the unrolled macros.
;********************************************************************************************** ;********************************************************************************************** ; 32x32 Bit Multiplication Macros macro 2+13+6*26+25+2+7*27+26+2+7*28+27+2+6*29+28+9 = 851 clks 2+7*6+5+1+7*6+5+1+7*6+5+2+6*6+5+6 = 192 clks DM: 17
SMUL3232L ; ; ;
Max Timing: Min Timing:
PM: 31+25+2+26+2+27+2+28+9 = 152
MOVLW MOVWF LOOPSM3232A RRF BTFSC
0x8 LOOPCOUNT
BARGB3, F _C
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GOTO DECFSZ GOTO MOVWF LOOPSM3232B RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPSM3232C RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPSM3232D RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALOOPSM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALSM3232NA RLF RRF RRF RRF RRF RRF DECFSZ GOTO BARGB3, F _C ALSM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F ALOOPSM3232 BARGB0, F _C DLSM3232NA LOOPCOUNT, F LOOPSM3232D AARGB0 AARGB1 AARGB2 AARGB3 0x00 BARGB1, F _C CLSM3232NA LOOPCOUNT, F LOOPSM3232C 0x7 LOOPCOUNT BARGB2, F _C BLSM3232NA LOOPCOUNT, F LOOPSM3232B LOOPCOUNT ALSM3232NA LOOPCOUNT, F LOOPSM3232A LOOPCOUNT
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MOVLW MOVWF BLOOPSM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLSM3232NA RLF RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPSM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLSM3232NA RLF RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW BARGB1, F _C CLSM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F LOOPCOUNT, F CLOOPSM3232 0x7 BARGB2, F _C BLSM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPSM3232 0x8 LOOPCOUNT 0x8 LOOPCOUNT
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MOVWF DLOOPSM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF DLSM3232NA RLF RRF RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RLF RRF RRF RRF RRF RRF RRF RRF RRF endm UMUL3232L ; ; ; macro 2+15+6*25+24+2+7*26+25+2+7*27+26+2+7*28+27 = 842 clks 2+7*6+5+1+7*6+5+1+7*6+5+1+7*6+5+6 = 197 clks DM: 17 BARGB0, F _C DLSM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F LOOPCOUNT, F DLOOPSM3232 SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7, LOOPCOUNT
F F F F F F F F
PM: 38+24+2+25+2+26+2+27+9 = 155 MOVLW MOVWF 0x08 LOOPCOUNT
LOOPUM3232A RRF BTFSC GOTO DECFSZ GOTO MOVWF BARGB3, F _C ALUM3232NAP LOOPCOUNT, F LOOPUM3232A LOOPCOUNT
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LOOPUM3232B RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3232C RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3232D RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALUM3232NAP BCF GOTO BCF GOTO BCF GOTO BCF GOTO BARGB0, F _C DLUM3232NAP LOOPCOUNT, F LOOPUM3232D AARGB0 AARGB1 AARGB2 AARGB3 0x00 _C ALUM3232NA _C BLUM3232NA _C CLUM3232NA _C DLUM3232NA BARGB1, F _C CLUM3232NAP LOOPCOUNT, F LOOPUM3232C LOOPCOUNT BARGB2, F _C BLUM3232NAP LOOPCOUNT, F LOOPUM3232B LOOPCOUNT
BLUM3232NAP
CLUM3232NAP
DLUM3232NAP
ALOOPUM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM3232NA RRF RRF RRF AARGB0, F AARGB1, F AARGB2, F BARGB3, F _C ALUM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
DS00617B-page 19
AN617
RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3232NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLUM3232NA RRF RRF RRF RRF RRF RRF AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F BARGB1, F _C CLUM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPUM3232 0x08 LOOPCOUNT BARGB2, F _C BLUM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB3, F AARGB4, F LOOPCOUNT, F ALOOPUM3232 0x08 LOOPCOUNT
DS00617B-page 20
AN617
RRF DECFSZ GOTO MOVLW MOVWF DLOOPUM3232 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF DLUM3232NA RRF RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F LOOPCOUNT, F DLOOPUM3232 BARGB0, F _C DLUM3232NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB6, F LOOPCOUNT, F CLOOPUM3232 0x08 LOOPCOUNT
UMUL3131L ; ; ;
macro 2+15+6*25+24+2+7*26+25+2+7*27+26+2+6*28+27+8 = 822 clks 2+7*6+5+1+7*6+5+1+7*6+5+2+6*6+5+6 = 192 clks DM: 17
PM: 39+24+2+25+2+26+2+27+8 = 155 MOVLW MOVWF 0x8 LOOPCOUNT
LOOPUM3131A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3131B RRF BTFSC GOTO BARGB2, F _C BLUM3131NAP BARGB3, F _C ALUM3131NAP LOOPCOUNT, F LOOPUM3131A LOOPCOUNT
DS00617B-page 21
AN617
DECFSZ GOTO MOVWF LOOPUM3131C RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPUM3131D RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALUM3131NAP BCF GOTO BCF GOTO BCF GOTO BCF GOTO BARGB0, F _C DLUM3131NAP LOOPCOUNT, F LOOPUM3131D AARGB0 AARGB1 AARGB2 AARGB3 0x00 _C ALUM3131NA _C BLUM3131NA _C CLUM3131NA _C DLUM3131NA BARGB1, F _C CLUM3131NAP LOOPCOUNT, F LOOPUM3131C 0x7 LOOPCOUNT LOOPCOUNT, F LOOPUM3131B LOOPCOUNT
BLUM3131NAP
CLUM3131NAP
DLUM3131NAP
ALOOPUM3131 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM3131NA RRF RRF RRF RRF RRF DECFSZ AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BARGB3, F _C ALUM3131NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
DS00617B-page 22
AN617
GOTO MOVLW MOVWF BLOOPUM3131 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3131NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM3131 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLUM3131NA RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F LOOPCOUNT, F CLOOPUM3131 BARGB1, F _C CLUM3131NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPUM3131 0x08 LOOPCOUNT BARGB2, F _C BLUM3131NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F ALOOPUM3131 0x08 LOOPCOUNT
DS00617B-page 23
AN617
MOVLW MOVWF DLOOPUM3131 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF DLUM3131NA RRF RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RRF RRF RRF RRF RRF RRF RRF RRF endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F LOOPCOUNT, F DLOOPUM3131 AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7, F F F F F F F F BARGB0, F _C DLUM3131NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F 0x07 LOOPCOUNT
SMUL3232 ; ; ;
macro Max Timing: Min Timing: 9+7*22+8*23+8*24+7*25+9 = 723 clks 62+6 = 68 clks DM: 16
PM: 68+6+7*22+8*23+8*24+7*25+9 = 788
variable i = 0 while i < 8 BTFSC GOTO BARGB3,i SM3232NA#v(i)
variable i = i + 1
DS00617B-page 24
AN617
endw variable i = 8 while i < 16 BTFSC GOTO BARGB2,i-8 SM3232NA#v(i)
variable i = i + 1 endw variable i = 16 while i < 24 BTFSC GOTO BARGB1,i-16 SM3232NA#v(i)
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN SM3232NA0 RLF RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC i < 8 BARGB3,i SM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4,
F F F F F
SM3232A#v(i)
DS00617B-page 25
AN617
SM3232NA#v(i) INCFSZ ADDWF RLF RRF RRF RRF RRF RRF TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF RRF i < 16 BARGB2,i-8 SM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
SM3232A#v(i)
SM3232NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF i < 24 BARGB1,i-16 SM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W
SM3232A#v(i)
SM3232NA#v(i)
DS00617B-page 26
AN617
RRF RRF RRF RRF RRF RRF RRF AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, F F F F F F F
variable i = i + 1 endw variable i = 24 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF RRF RRF RRF i < 31 BARGB0,i-24 SM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F
SM3232A#v(i)
SM3232NA#v(i)
variable i = i + 1 endw RLF RRF RRF RRF RRF RRF RRF RRF RRF endm SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7,
F F F F F F F F
UMUL3232 ; ; ;
macro Max Timing: Min Timing: 9+8*21+8*22+8*23+8*24 = 729 clks 63+6 = 69 clks DM: 16
PM: 69+6+8*21+8*22+8*23+8*24 = 795
DS00617B-page 27
AN617
variable i = 0 BCF while i < 8 BTFSC GOTO BARGB3,i UM3232NA#v(i) _C ; clear carry for first right shift
variable i = i + 1 endw variable i = 8 while i < 16 BTFSC GOTO BARGB2,i-8 UM3232NA#v(i)
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM3232NA0 RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO i < 8 BARGB3,i UM3232NA#v(i) AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
AARGB0, AARGB1, AARGB2, AARGB3, AARGB4,
F F F F F
DS00617B-page 28
AN617
UM3232A#v(i) MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
UM3232NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF i < 16 BARGB2,i-8 UM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
UM3232A#v(i)
UM3232NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ i < 24 BARGB1,i-16 UM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W
UM3232A#v(i)
DS00617B-page 29
AN617
ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF RRF AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F
UM3232NA#v(i)
variable i = i + 1 endw
variable i = 24 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF RRF RRF i < 32 BARGB0,i-24 UM3232NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F
UM3232A#v(i)
UM3232NA#v(i)
endm
UMUL3131 ; ; ;
macro Max Timing: Min Timing: 9+7*21+8*22+8*23+7*24+9 = 693 clks 62+6 = 68 clks DM: 16
PM: 68+6+7*22+8*23+8*24+7*25+9 = 788
DS00617B-page 30
AN617
variable i = 24 while i < 31 BTFSC GOTO BARGB0,i-24 UM3131NA#v(i)
CLRF CLRF CLRF CLRF RETURN UM3131NA0 RRF RRF RRF RRF RRF variable i = 1 while BTFSS i < 8
AARGB0 AARGB1 AARGB2 AARGB3
; if we get here, BARG = 0
F F F F F
BARGB3,i
DS00617B-page 31
AN617
UM3131A#v(i) GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF UM3131NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
UM3131NA#v(i)
UM3131A#v(i)
UM3131NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC i < 24 BARGB1,i-16 UM3131NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C
UM3131A#v(i)
DS00617B-page 32
AN617
INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF RRF TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F
UM3131NA#v(i)
variable i = i + 1 endw variable i = 24 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF RRF RRF i < 31 BARGB0,i-24 UM3131NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F AARGB6, F AARGB7, F
UM3131A#v(i)
UM3131NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF RRF RRF RRF RRF endm AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7, F F F F F F F F
DS00617B-page 33
AN617
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; 32x32 Bit Signed Fixed Point Multiply 32x32 -> 64 Input: 32 bit signed fixed point multiplicand in AARGB0 32 bit signed fixed point multiplier in BARGB0 CALL FXM3232S
Use:
Output: 64 bit signed fixed point product in AARGB0 Result: AARG Max Timing: <-AARG x BARG B > 0 B < 0
15+851+2 = 868 clks 36+851+2 = 889 clks 15+192 = 207 clks DM: 17
Min Timing:
PM: 36+152+1 = 189
FXM3232S
CLRF CLRF CLRF CLRF CLRF MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF BTFSS GOTO COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF
AARGB4 AARGB5 AARGB6 AARGB7 SIGN AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F BARGB0,MSB M3232SOK BARGB3, BARGB2, BARGB1, BARGB0, BARGB3, _Z BARGB2, _Z BARGB1, _Z BARGB0, AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, F F F F F F F F F F F F F F F F
; clear partial product
DS00617B-page 34
AN617
BTFSC GOTO M3232SOK MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF SMUL3232L RETLW M3232SX CLRF CLRF CLRF CLRF RLF RRF RRF RRF RRF RETLW 0x00 AARGB4 AARGB5 AARGB6 AARGB7 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F 0x00 BARGB0,MSB M3232SX AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM3232U CLRF CLRF CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL3232L RETLW 0x00 AARGB4 AARGB5 AARGB7 AARGB6 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3 ; clear partial product 32x32 Bit Unsigned Fixed Point Multiply 32x32 -> 64 Input: 32 bit unsigned fixed point multiplicand in AARGB0 32 bit unsigned fixed point multiplier in BARGB0 CALL FXM3232U
Use:
Output: 64 bit unsigned fixed point product in AARGB0 Result: AARG Max Timing: Min Timing: <-AARG x BARG
12+842+2 = 856 clks 12+197 = 209 clks DM: 17
PM: 12+155+1 = 168
DS00617B-page 35
AN617
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM3131U CLRF CLRF CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL3131L RETLW 0x00 AARGB4 AARGB5 AARGB7 AARGB6 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3 ; clear partial product 31x31 Bit Unsigned Fixed Point Divide 31x31 -> 62 Input: 31 bit unsigned fixed point multiplicand in AARGB0 31 bit unsigned fixed point multiplier in BARGB0 CALL FXM3131U
Use:
12+822+2 = 836 clks 12+192 = 204 clks DM: 17
PM: 12+155+1 = 168
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 36
AN617
D.2
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 32x24 Bit Multiplication Macros macro 2+13+6*26+25+2+7*27+26+2+6*28+27+8 = 618 clks 2+7*6+5+1+7*6+5+2+6*6+5+6 = 146 clks DM: 15
SMUL3224L ; ; ;
PM: 25+25+2+26+2+27+8 = 115
MOVLW MOVWF LOOPSM3224A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPSM3224B RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF
0x8 LOOPCOUNT
BARGB2,F _C ALSM3224NA LOOPCOUNT,F LOOPSM3224A LOOPCOUNT
BARGB1,F _C BLSM3224NA LOOPCOUNT,F LOOPSM3224B 0x7 LOOPCOUNT
DS00617B-page 37
AN617
LOOPSM3224C RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALOOPSM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALSM3224NA RLF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPSM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLSM3224NA RLF RRF RRF BARGB1,F _C BLSM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F SIGN,W AARGB0,F AARGB1,F BARGB2,F _C ALSM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F LOOPCOUNT,F ALOOPSM3224 0x8 LOOPCOUNT BARGB0,F _C CLSM3224NA LOOPCOUNT,F LOOPSM3224C AARGB0 AARGB1 AARGB2 AARGB3 0x00
DS00617B-page 38
AN617
RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPSM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLSM3224NA RLF RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RLF RRF RRF RRF RRF RRF RRF RRF endm UMUL3224L ; ; ; macro 2+15+6*25+24+2+7*26+25+2+7*27+26 = 617 clks 2+7*6+5+1+7*6+5+1+7*6+5+6 = 151 clks DM: 15 BARGB0,F _C CLSM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F LOOPCOUNT,F CLOOPSM3224 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F LOOPCOUNT,F BLOOPSM3224 0x7 LOOPCOUNT
PM: 31+24+2+25+2+26+2+27 = 139 MOVLW MOVWF 0x08 LOOPCOUNT
LOOPUM3224A RRF BTFSC GOTO BARGB2,F _C ALUM3224NAP
DS00617B-page 39
AN617
DECFSZ GOTO MOVWF LOOPUM3224B RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3224C RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALUM3224NAP BCF GOTO BCF GOTO BCF GOTO BARGB0,F _C CLUM3224NAP LOOPCOUNT,F LOOPUM3224C AARGB0 AARGB1 AARGB2 AARGB3 0x00 _C ALUM3224NA _C BLUM3224NA _C CLUM3224NA BARGB1,F _C BLUM3224NAP LOOPCOUNT,F LOOPUM3224B LOOPCOUNT LOOPCOUNT,F LOOPUM3224A LOOPCOUNT
BLUM3224NAP
CLUM3224NAP
ALOOPUM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM3224NA RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F LOOPCOUNT,F ALOOPUM3224 0x08 LOOPCOUNT BARGB2,F _C ALUM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F
DS00617B-page 40
AN617
BLOOPUM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3224NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM3224 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLUM3224NA RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO endm AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F LOOPCOUNT,F CLOOPUM3224 BARGB0,F _C CLUM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F LOOPCOUNT,F BLOOPUM3224 0x08 LOOPCOUNT BARGB1,F _C BLUM3224NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F
DS00617B-page 41
AN617
UMUL3123L ; ; ; macro 2+15+6*25+24+2+7*26+25+2+6*27+26+7 = 597 clks 2+7*6+5+1+7*6+5+2+6*6+5+6 = 146 clks DM: 15
PM: 31+24+2+25+2+26+7 = 117 MOVLW MOVWF 0x8 LOOPCOUNT
LOOPUM3123A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3123B RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPUM3123C RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW ALUM3123NAP BCF GOTO BCF GOTO BCF GOTO BARGB0,F _C CLUM3123NAP LOOPCOUNT,F LOOPUM3123C AARGB0 AARGB1 AARGB2 AARGB3 0x00 _C ALUM3123NA _C BLUM3123NA _C CLUM3123NA BARGB1,F _C BLUM3123NAP LOOPCOUNT,F LOOPUM3123B 0x7 LOOPCOUNT BARGB2,F _C ALUM3123NAP LOOPCOUNT,F LOOPUM3123A LOOPCOUNT
BLUM3123NAP
CLUM3123NAP
ALOOPUM3123 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ BARGB2,F _C ALUM3123NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W
DS00617B-page 42
AN617
ADDWF MOVF BTFSC INCFSZ ADDWF ALUM3123NA RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM3123 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3123NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM3123 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC BARGB0,F _C CLUM3123NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F LOOPCOUNT,F BLOOPUM3123 0x07 LOOPCOUNT BARGB1,F _C BLUM3123NA TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F LOOPCOUNT,F ALOOPUM3123 0x08 LOOPCOUNT AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F
DS00617B-page 43
AN617
INCFSZ ADDWF CLUM3123NA RRF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RRF RRF RRF RRF RRF RRF RRF endm AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F LOOPCOUNT,F CLOOPUM3123 AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F TEMPB0,W AARGB0,F
SMUL3224 ; ; ;
macro Max Timing: Min Timing: 9+7*22+8*23+7*24+8 = 523 clks 40+6 = 46 clks DM: 14
PM: 46+6+7*22+8*23+7*24+8 = 566
variable i = i + 1
DS00617B-page 44
AN617
endw CLRF CLRF CLRF CLRF RETURN SM3224NA0 RLF RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF i < 8 BARGB2,i SM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F
SM3224A#v(i)
SM3224NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF i < 16 BARGB1,i-8 SM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F
SM3224A#v(i)
DS00617B-page 45
AN617
SM3224NA#v(i) RLF RRF RRF RRF RRF RRF RRF SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF RRF RRF i < 23 BARGB0,i-16 SM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F
SM3224A#v(i)
SM3224NA#v(i)
variable i = i + 1 endw RLF RRF RRF RRF RRF RRF RRF RRF endm SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F
UMUL3224 ; ; ;
macro Max Timing: Min Timing: 9+8*21+8*22+8*23 = 537 clks 41+6 = 47 clks DM: 14
PM: 47+6+8*21+8*22+8*23 = 581
DS00617B-page 46
AN617
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM3224NA0 RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ i < 8 BARGB2,i UM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F
UM3224A#v(i)
DS00617B-page 47
AN617
UM3224NA#v(i) ADDWF RRF RRF RRF RRF RRF AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF i < 16 BARGB1,i-8 UM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F
UM3224A#v(i)
UM3224NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF i < 24 BARGB0,i-16 UM3224NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F
UM3224A#v(i)
UM3224NA#v(i)
DS00617B-page 48
AN617
RRF RRF RRF AARGB4,F AARGB5,F AARGB6,F
variable i = i + 1 endw endm
UMUL3123 ; ; ;
PM: 47+5+7*22+8*23+7*24+7 = 565
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM3123NA0 RRF RRF RRF RRF RRF AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F
DS00617B-page 49
AN617
variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF i < 8 BARGB2,i UM3123NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F
UM3123A#v(i)
UM3123NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF i < 16 BARGB1,i-8 UM3123NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F
UM3123A#v(i)
UM3123NA#v(i)
variable i = i + 1 endw variable i = 16 while i < 23
DS00617B-page 50
AN617
UM3123A#v(i) BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF RRF BARGB0,i-16 UM3123NA#v(i) TEMPB3,W AARGB3,F TEMPB2,W _C TEMPB2,W AARGB2,F TEMPB1,W _C TEMPB1,W AARGB1,F TEMPB0,W _C TEMPB0,W AARGB0,F AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F
UM3123NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; FXM3224S Use: 32x24 Bit Signed Fixed Point Multiply 32x24 -> 56 Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1, AARGB2, AARGB3 24 bit signed fixed point multiplier in BARGB0, BARGB1, BARGB2 CALL FXM3224S AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F AARGB5,F AARGB6,F
14+618+2 = 634 clks 32+618+2 = 652 clks 14+146 = 160 clks DM: 15 AARGB4 AARGB5 AARGB6 SIGN
Min Timing:
PM: 36+115+1 = 152 CLRF CLRF CLRF CLRF
DS00617B-page 51
AN617
MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF BTFSS GOTO COMF COMF COMF INCF BTFSC INCF BTFSC INCF COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF BTFSC GOTO M3224SOK MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF SMUL3224L RETLW M3224SX CLRF CLRF CLRF RLF RRF RRF RRF RRF RRF RETLW 0x00 AARGB4 AARGB5 AARGB6 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB4,F 0x00 AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F BARGB0,MSB M3224SOK BARGB2, BARGB1, BARGB0, BARGB2, _Z BARGB1, _Z BARGB0, AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, F F F F F F F F F F F F F F
BARGB0,MSB M3224SX AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3
;**********************************************************************************************
DS00617B-page 52
AN617
;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; FXM3224U CLRF CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL3224L RETLW 0x00 AARGB4 AARGB5 AARGB6 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3 ; clear partial product Use: 32x24 Bit Unsigned Fixed Point Multiply 32x24 -> 56 Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2, AARGB3 24 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2 CALL FXM3224U
11+617+2 = 630 clks 11+151 = 162 clks DM: 15
PM: 11+139+1 = 151
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; FXM3123U CLRF CLRF CLRF AARGB4 AARGB5 AARGB6 ; clear partial product Use: 31x23 Bit Unsigned Fixed Point Divide 31x23 -> 54 Input: 31 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2, AARGB3 23 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2 CALL FXM3123U
11+597+2 = 610 clks 11+146 = 157 clks DM: 15
PM: 11+117+1 = 129
DS00617B-page 53
AN617
MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL3123L RETLW 0x00 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 54
AN617
D.3
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 32x16 Bit Multiplication Macros macro 2+13+6*26+25+2+6*27+26+7 = 393 clks 2+7*6+5+2+6*6+5+6 = 98 clks DM: 11
SMUL3216L ; ; ;
Max Timing: Min Timing: PM: 19+60 = 79
MOVLW MOVWF LOOPSM3216A RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPSM3216B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF
0x8 LOOPCOUNT
BARGB1, F _C ALSM3216NA LOOPCOUNT, F LOOPSM3216A 0x7 LOOPCOUNT
BARGB0, F _C BLSM3216NA LOOPCOUNT, F LOOPSM3216B AARGB0 AARGB1
DS00617B-page 55
AN617
CLRF CLRF RETLW ALOOPSM3216 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALSM3216NA RLF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPSM3216 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLSM3216NA RLF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RLF RRF BARGB0, F _C BLSM3216NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPSM3216 TEMPB0,W AARGB0, F BARGB1, F _C ALSM3216NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F ALOOPSM3216 0x7 LOOPCOUNT AARGB2 AARGB3 0x00
DS00617B-page 56
AN617
RRF RRF RRF RRF RRF endm UMUL3216L ; ; ; macro 2+15+6*25+24+2+7*26+25 = 400 clks 2+7*6+5+1+7*6+5+6 = 103 clks DM: 11 MOVLW MOVWF LOOPUM3216A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM3216B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW BLUM3216NAP BCF GOTO ALUM3216NAP BCF GOTO ALOOPUM3216 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ BARGB1, F _C ALUM3216NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W _C ALUM3216NA _C BLUM3216NA BARGB0, F _C BLUM3216NAP LOOPCOUNT, F LOOPUM3216B AARGB0 AARGB1 AARGB2 AARGB3 0x00 BARGB1, F _C ALUM3216NAP LOOPCOUNT, F LOOPUM3216A LOOPCOUNT 0x08 LOOPCOUNT AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F
Max Timing: Min Timing: PM: 73
DS00617B-page 57
AN617
ADDWF ALUM3216NA RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM3216 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3216NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPUM3216 BARGB0, F _C BLUM3216NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F ALOOPUM3216 0x08 LOOPCOUNT AARGB0, F
UMUL3115L ; ; ;
macro 2+15+6*25+24+2+6*26+25+6 = 380 clks 2+7*6+5+2+6*6+5+6 = 96 clks DM: 11 MOVLW MOVWF 0x8 LOOPCOUNT
LOOPUM3115A RRF BTFSC GOTO DECFSZ GOTO MOVLW BARGB1, F _C ALUM3115NAP LOOPCOUNT, F LOOPUM3115A 0x7
DS00617B-page 58
AN617
MOVWF LOOPUM3115B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF CLRF RETLW BLUM3115NAP BCF GOTO ALUM3115NAP BCF GOTO ALOOPUM3115 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM3115NA RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM3115 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC BARGB0, F _C BLUM3115NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F ALOOPUM3115 0x07 LOOPCOUNT BARGB1, F _C ALUM3115NA TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F _C ALUM3115NA _C BLUM3115NA BARGB0, F _C BLUM3115NAP LOOPCOUNT, F LOOPUM3115B AARGB0 AARGB1 AARGB2 AARGB3 0x00 LOOPCOUNT
DS00617B-page 59
AN617
INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM3115NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO RRF RRF RRF RRF RRF RRF endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F BLOOPUM3115 AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
SMUL3216 ; ; ;
macro Max Timing: Min Timing: 5+8+7*20+7*21+5 = 305 clks 5+24+21+7 = 57 clks DM: 10
PM: 5+24+21+6+5+7*20+7*21+5 = 353
variable i = 0 BTFSC COMF MOVF MOVWF RLF while i < 8 BTFSC GOTO BCF BARGB1,i SM3216NA#v(i) AARGB4,7-i SIGN,MSB AARGB4, F AARGB4,W AARGB5 SIGN,W
variable i = i + 1 endw variable i = 8 while i < 15 BTFSC GOTO BCF BARGB0,i-8 SM3216NA#v(i) AARGB5,15-i
DS00617B-page 60
AN617
CLRF CLRF CLRF CLRF CLRF RETURN SM3216NA0 RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF i < 8 BARGB1,i SM3216NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, F F F F F AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, F F F F F AARGB0 AARGB1 AARGB2 AARGB3 AARGB5 ; if we get here, BARG = 0
SM3216A#v(i)
SM3216NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF i < 15 BARGB0,i-8 SM3216NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
SM3216A#v(i)
DS00617B-page 61
AN617
SM3216NA#v(i) RRF RRF RRF RRF RRF RRF AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F
variable i = i + 1 endw RRF RRF RRF RRF RRF RRF endm AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F
UMUL3216 ; ; ;
macro Max Timing: Min Timing: 1+8+7*21+8*22 = 332 clks 1+2*8+2*8+6 = 39 clks DM: 10
PM: 1+2*8+2*8+6+7*21+8*22 = 362
variable i = 0 BCF _ C ; clear carry for first right shift
while i < 8 BTFSC GOTO BARGB1,i UM3216NA#v(i)
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM3216NA0 RRF RRF RRF RRF RRF AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
F F F F F
DS00617B-page 62
AN617
variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF i < 8 BARGB1,i UM3216NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
UM3216A#v(i)
UM3216NA#v(i)
UM3216A#v(i)
UM3216NA#v(i)
DS00617B-page 63
AN617
UMUL3115 ; ; ; macro Max Timing: Min Timing: 9+7*21+7*22+6 = 316 clks 1+30+6 = 37 clks DM: 10
PM: 1+30+10+7*21+7*22+6 = 348
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM3115NA0 RRF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF i < 8 BARGB1,i UM3115NA#v(i) TEMPB3,W AARGB3, F TEMPB2,W _C TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
F F F F F
UM3115A#v(i)
UM3115NA#v(i)
DS00617B-page 64
AN617
RRF RRF RRF RRF AARGB1, AARGB2, AARGB3, AARGB4, F F F F
UM3115A#v(i)
UM3115NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; 32x16 Bit Signed Fixed Point Multiply 32x16 -> 32 Input: 16 bit signed fixed point multiplicand in AARGB0 16 bit signed fixed point multiplier in BARGB0 CALL FXM3216S AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F
Use:
13+393+2 = 408 clks 28+393+2 = 423 clks
DS00617B-page 65
AN617
; ; Min Timing: PM: 18+79+1 = 98 13+98 = 111 clks DM: 9
FXM3216S
CLRF CLRF CLRF MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF BTFSS GOTO COMF COMF INCF BTFSC INCF COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF BTFSC GOTO
AARGB4 AARGB5 SIGN AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F BARGB0,MSB M3216SOK BARGB1, BARGB0, BARGB1, _Z BARGB0, AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, F F F F F F F F F F F F
BARGB0,MSB M3216SX AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3
M3216SOK
MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF SMUL3216L RETLW
0x00
M3216SX
CLRF CLRF RLF RRF RRF RRF RRF
AARGB4 AARGB5 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F
DS00617B-page 66
AN617
RRF RETLW AARGB4,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM3216U CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL3216L RETLW 0x00 AARGB4 AARGB5 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3 ; clear partial product 32x16 Bit Unsigned Fixed Point Multiply 32x16 -> 32 Input: 16 bit unsigned fixed point multiplicand in AARGB0 16 bit unsigned fixed point multiplier in BARGB0 CALL FXM3216U
Use:
Output: 32 bit unsigned fixed point product in AARGB0 Result: AARG Max Timing: Min Timing: PM: 10+73+1 = 84 <-AARG x BARG
10+400+2 = 412 clks 10+104 = 114 clks DM: 9
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM3115U CLRF CLRF MOVF MOVWF MOVF AARGB4 AARGB5 AARGB0,W TEMPB0 AARGB1,W ; clear partial product 31x15 Bit Unsigned Fixed Point Divide 31x15 -> 30 Input: 15 bit unsigned fixed point multiplicand in AARGB0 15 bit unsigned fixed point multiplier in BARGB0 CALL FXM3115U
Use:
10+380+2 = 392 clks 10+96 = 106 clks DM: 9
DS00617B-page 67
AN617
MOVWF MOVF MOVWF MOVF MOVWF UMUL3115L RETLW 0x00 TEMPB1 AARGB2,W TEMPB2 AARGB3,W TEMPB3
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 68
AN617
D.4
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 24x24 Bit Multiplication Macros macro 2+12+6*21+20+2+7*22+21+2+6*23+22+7 = 506 clks 2+7*6+5+1+7*6+5+2+6*6+5+5 = 145 clks DM: 13
SMUL2424L ; ; ;
PM: 24+20+2+21+2+22+7 = 98
MOVLW MOVWF LOOPSM2424A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPSM2424B RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF
0x8 LOOPCOUNT
BARGB2, F _C ALSM2424NA LOOPCOUNT, F LOOPSM2424A LOOPCOUNT
BARGB1, F _C BLSM2424NA LOOPCOUNT, F LOOPSM2424B 0x7 LOOPCOUNT
DS00617B-page 69
AN617
LOOPSM2424C RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF RETLW ALOOPSM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALSM2424NA RLF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPSM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLSM2424NA RLF RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BARGB1, F _C BLSM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPSM2424 0x7 LOOPCOUNT BARGB2, F _C ALSM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPSM2424 0x8 LOOPCOUNT BARGB0, F _C CLSM2424NA LOOPCOUNT, F LOOPSM2424C AARGB0 AARGB1 AARGB2 0x00
DS00617B-page 70
AN617
CLOOPSM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLSM2424NA RLF RRF RRF RRF RRF RRF RRF DECFSZ GOTO RLF RRF RRF RRF RRF RRF RRF endm UMUL2424L ; ; ; macro 2+14+6*20+19+2+7*21+20+2+7*22+21 = 501 clks 2+7*6+5+1+7*6+5+1+7*6+5+5 = 150 clks DM: 13 BARGB0, F _C CLSM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F CLOOPSM2424 SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5,
F F F F F F
PM: 23+20+2+21+2+22 = 88
MOVLW MOVWF LOOPUM2424A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM2424B RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM2424C
0x08 LOOPCOUNT
BARGB2, F _C ALUM2424NAP LOOPCOUNT, F LOOPUM2424A LOOPCOUNT
BARGB1, F _C BLUM2424NAP LOOPCOUNT, F LOOPUM2424B LOOPCOUNT
DS00617B-page 71
AN617
RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF RETLW CLUM2424NAP BCF GOTO BLUM2424NAP BCF GOTO ALUM2424NAP BCF GOTO ALOOPUM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM2424NA RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM2424NA RRF AARGB0, F BARGB1, F _C BLUM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPUM2424 0x08 LOOPCOUNT BARGB2, F _C ALUM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F _C ALUM2424NA _C BLUM2424NA _C CLUM2424NA BARGB0, F _C CLUM2424NAP LOOPCOUNT, F LOOPUM2424C AARGB0 AARGB1 AARGB2 0x00
DS00617B-page 72
AN617
RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM2424 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLUM2424NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F CLOOPUM2424 BARGB0, F _C CLUM2424NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPUM2424 0x08 LOOPCOUNT
UMUL2323L ; ; ;
macro 2+15+6*20+19+2+7*21+20+2+6*22+21+6 = 486 clks 2+7*6+5+1+7*6+5+2+6*6+5+5 = 145 clks DM: 13
PM: 24+20+2+21+2+22+6 = 97
MOVLW MOVWF LOOPUM2323A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM2323B RRF BTFSC GOTO DECFSZ GOTO
0x8 LOOPCOUNT
BARGB1, F _C BLUM2323NAP LOOPCOUNT, F LOOPUM2323B
DS00617B-page 73
AN617
MOVLW MOVWF LOOPUM2323C RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF RETLW CLUM2323NAP BCF GOTO BLUM2323NAP BCF GOTO ALUM2323NAP BCF GOTO ALOOPUM2323 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM2323NA RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM2323 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC BARGB1, F _C BLUM2323NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPUM2323 0x08 LOOPCOUNT BARGB2, F _C ALUM2323NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F _C ALUM2323NA _C BLUM2323NA _C CLUM2323NA BARGB0, F _C CLUM2323NAP LOOPCOUNT, F LOOPUM2323C AARGB0 AARGB1 AARGB2 0x00 0x7 LOOPCOUNT
DS00617B-page 74
AN617
INCFSZ ADDWF BLUM2323NA RRF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF CLOOPUM2323 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLUM2323NA RRF RRF RRF RRF RRF RRF DECFSZ GOTO RRF RRF RRF RRF RRF RRF endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F LOOPCOUNT, F CLOOPUM2323 AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F BARGB0, F _C CLUM2323NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPUM2323 0x07 LOOPCOUNT TEMPB0,W AARGB0, F
SMUL2424 ; ; ;
PM: 51+4+7*17+8*18+7*19+7 = 466
DS00617B-page 75
AN617
variable i = i + 1 endw CLRF CLRF CLRF RETURN SM2424NA0 RLF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF i < 8 BARGB2,i SM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
SIGN,W AARGB0, AARGB1, AARGB2, AARGB3,
F F F F
SM2424A#v(i)
SM2424NA#v(i)
variable i = i + 1 endw variable i = 8
DS00617B-page 76
AN617
while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF i < 16 BARGB1,i-8 SM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
SM2424A#v(i)
SM2424NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF RRF i < 23 BARGB0,i-16 SM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F TEMPB0,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
SM2424A#v(i)
SM2424NA#v(i)
variable i = i + 1 endw RLF RRF RRF RRF RRF RRF RRF endm TEMPB0,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
UMUL2424
macro
DS00617B-page 77
AN617
; ; ; Max Timing: Min Timing: 8+8*17+8*18+8*19 = 440 clks 49+5 = 54 clks DM: 12
PM: 54+4+8*17+8*18+8*19 = 490
variable i = i + 1 endw CLRF CLRF CLRF RETURN UM2424NA0 RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC i < 8 BARGB2,i UM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
AARGB0, AARGB1, AARGB2, AARGB3,
F F F F
UM2424A#v(i)
DS00617B-page 78
AN617
UM2424NA#v(i) INCFSZ ADDWF RRF RRF RRF RRF TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF i < 16 BARGB1,i-8 UM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
UM2424A#v(i)
UM2424NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF i < 24 BARGB0,i-16 UM2424NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
UM2424A#v(i)
UM2424NA#v(i)
DS00617B-page 79
AN617
UMUL2323 ; ; ; macro Max Timing: Min Timing: 8+7*17+8*18+7*19+7 = 411 clks 46+5 = 51 clks DM: 12
PM: 51+4+7*17+8*18+7*19+7 = 466
variable i = i + 1 endw CLRF CLRF CLRF CLRF RETURN UM2323NA0 RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC i < 8 BARGB2,i UM2323NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C AARGB0 AARGB1 AARGB2 AARGB3 ; if we get here, BARG = 0
F F F F
UM2323A#v(i)
DS00617B-page 80
AN617
INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F
UM2323NA#v(i)
UM2323A#v(i)
UM2323NA#v(i)
variable i = i + 1 endw variable i = 16 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF RRF i < 23 BARGB0,i-16 UM2323NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F AARGB5, F
UM2323A#v(i)
UM2323NA#v(i)
variable i = i + 1
DS00617B-page 81
AN617
endw RRF RRF RRF RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXM2424S 24x24 Bit Signed Fixed Point Multiply 24x24 -> 48 Input: 24 bit signed fixed point multiplicand in AARGB0 24 bit signed fixed point multiplier in BARGB0 CALL FXM2424S AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, AARGB5, F F F F F F
Use:
12+506+2 = 520 clks 27+506+2 = 535 clks 12+145 = 157 clks DM: 13 AARGB3 AARGB4 AARGB5 SIGN AARGB0,W AARGB1,W AARGB2,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F BARGB0,MSB M2424SOK BARGB2, BARGB1, BARGB0, BARGB2, _Z BARGB1, _Z BARGB0, AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, F F F F F F F F F F F
Min Timing:
PM: 27+98+1 = 126 CLRF CLRF CLRF CLRF MOVF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF BTFSS GOTO COMF COMF COMF INCF BTFSC INCF BTFSC INCF COMF COMF COMF INCF BTFSC INCF
DS00617B-page 82
AN617
BTFSC INCF BTFSC GOTO M2424SOK MOVF MOVWF MOVF MOVWF MOVF MOVWF SMUL2424L RETLW M2424SX CLRF CLRF CLRF RLF RRF RRF RRF RRF RETLW 0x00 AARGB3 AARGB4 AARGB5 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F 0x00 _Z AARGB0, F BARGB0,MSB M2424SX AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM2424U CLRF CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL2424L RETLW 0x00 AARGB3 AARGB4 AARGB5 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 ; clear partial product 24x24 Bit Unsigned Fixed Point Multiply 24x24 -> 48 Input: 24 bit unsigned fixed point multiplicand in AARGB0 24 bit unsigned fixed point multiplier in BARGB0 CALL FXM2424U
Use:
9+501+2 = 512 clks 9+150 = 159 clks DM: 13
;**********************************************************************************************
DS00617B-page 83
AN617
;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM2323U CLRF CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL2323L RETLW 0x00 AARGB3 AARGB4 AARGB5 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 ; clear partial product 23x23 Bit Unsigned Fixed Point Divide 23x23 -> 46 Input: 23 bit unsigned fixed point multiplicand in AARGB0 23 bit unsigned fixed point multiplier in BARGB0 CALL FXM2323U
Use:
9+486+2 = 497 clks 9+145 = 154 clks DM: 13
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 84
AN617
D.5
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

SMUL2416L ; ; ;
PM: 19+20+2+21+6 = 68
0x8 LOOPCOUNT
DS00617B-page 85
AN617
CLRF RETLW ALOOPSM2416 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALSM2416NA RLF RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPSM2416 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLSM2416NA RLF RRF RRF RRF RRF RRF DECFSZ GOTO BARGB0, F _C BLSM2416NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPSM2416 BARGB1, F _C ALSM2416NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPSM2416 0x7 LOOPCOUNT AARGB2 0x00
RLF RRF RRF RRF RRF RRF endm UMUL2416L ; macro
SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4,
F F F F F
Max Timing:
2+14+6*20+19+2+7*21+20 = 324 clks
DS00617B-page 86
AN617
; ; Min Timing: 2+7*6+5+1+7*6+5+5 = 102 clks DM: 12
PM: 18+20+2+21 = 61
MOVLW MOVWF LOOPUM2416A RRF BTFSC GOTO DECFSZ GOTO MOVWF LOOPUM2416B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF RETLW BLUM2416NAP BCF GOTO ALUM2416NAP BCF GOTO ALOOPUM2416 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM2416NA RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM2416 RRF
0x08 LOOPCOUNT
BARGB0, F _C BLUM2416NAP LOOPCOUNT, F LOOPUM2416B AARGB0 AARGB1 AARGB2 0x00
_C BLUM2416NA
_C ALUM2416NA
BARGB1, F _C ALUM2416NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPUM2416 0x08 LOOPCOUNT
BARGB0, F
DS00617B-page 87
AN617
BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM2416NA RRF RRF RRF RRF RRF DECFSZ GOTO endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPUM2416 _C BLUM2416NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
UMUL2315L ; ; ;
macro 2+15+6*20+19+2+6*21+20+5 = 309 clks 2+7*6+5+1+6*6+5+5 = 96 clks DM: 12
PM: 19+20+2+21+5 = 67
MOVLW MOVWF LOOPUM2315A RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPUM2315B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF CLRF RETLW BLUM2315NAP BCF GOTO ALUM2315NAP BCF
0x8 LOOPCOUNT
BARGB1, F _C ALUM2315NAP LOOPCOUNT, F LOOPUM2315A 0x7 LOOPCOUNT
BARGB0, F _C BLUM2315NAP LOOPCOUNT, F LOOPUM2315B AARGB0 AARGB1 AARGB2 0x00
_C BLUM2315NA
_C
DS00617B-page 88
AN617
GOTO ALOOPUM2315 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF ALUM2315NA RRF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM2315 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BLUM2315NA RRF RRF RRF RRF RRF DECFSZ GOTO RRF RRF RRF RRF RRF endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F LOOPCOUNT, F BLOOPUM2315 AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, F F F F F BARGB0, F _C BLUM2315NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F ALOOPUM2315 0x07 LOOPCOUNT BARGB1, F _C ALUM2315NA TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F ALUM2315NA
SMUL2416 ;
macro Max Timing: 8+7*17+7*18+6 = 259 clks
DS00617B-page 89
AN617
; ; Min Timing: 30+5 = 35 clks DM: 11 PM: 30+4+7*17+7*18+6 = 285
variable i = i + 1 endw CLRF CLRF CLRF RETURN SM2416NA0 RLF RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF i < 8 BARGB1,i SM2416NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
SIGN,W AARGB0, AARGB1, AARGB2, AARGB3,
F F F F
SM2416A#v(i)
SM2416NA#v(i)
variable i = i + 1 endw variable i = 8
DS00617B-page 90
AN617
while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF RRF RRF RRF RRF RRF i < 15 BARGB0,i-8 SM2416NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
SM2416A#v(i)
SM2416NA#v(i)
variable i = i + 1 endw RLF RRF RRF RRF RRF RRF endm SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, AARGB4,
F F F F F
UMUL2416 ; ; ;
macro Max Timing: Min Timing: 8+8*17+8*18 = 288 clks 33+5 = 38 clks DM: 11
PM: 37+4+8*17+8*18 = 321
variable i = i + 1
DS00617B-page 91
AN617
endw CLRF CLRF CLRF RETURN UM2416NA0 RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF i < 8 BARGB1,i UM2416NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
F F F F
UM2416A#v(i)
UM2416NA#v(i)
UM2416A#v(i)
UM2416NA#v(i)
DS00617B-page 92
AN617
UMUL2315 ; ; ; macro Max Timing: Min Timing: 8+7*17+7*18+6 = 259 clks 31+5 = 36 clks DM: 11
PM: 35+4+7*17+7*18+6 = 290
variable i = i + 1 endw CLRF CLRF CLRF RETURN UM2315NA0 RRF RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF i < 8 BARGB1,i UM2315NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
F F F F
UM2315A#v(i)
UM2315NA#v(i)
variable i = i + 1
DS00617B-page 93
AN617
endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF RRF i < 15 BARGB0,i-8 UM2315NA#v(i) TEMPB2,W AARGB2, F TEMPB1,W _C TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F AARGB4, F
UM2315A#v(i)
UM2315NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXM2416S 24x16 Bit Signed Fixed Point Multiply 24x16 -> 40 Input: 24 bit signed fixed point multiplicand in AARGB0 16 bit signed fixed point multiplier in BARGB0 CALL FXM2416S AARGB0, AARGB1, AARGB2, AARGB3, AARGB4, F F F F F
Use:
11+321+2 = 334 clks 23+321+2 = 346 clks 11+97 = 108 clks DM: 12 AARGB3 AARGB4 SIGN AARGB0,W AARGB1,W AARGB2,W _Z 0x00
Min Timing: PM: 23+68+1 = 92 CLRF CLRF CLRF MOVF IORWF IORWF BTFSC RETLW
DS00617B-page 94
AN617
MOVF XORWF MOVWF BTFSC COMF AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F
BTFSS GOTO COMF COMF INCF BTFSC INCF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC GOTO M2416SOK MOVF MOVWF MOVF MOVWF MOVF MOVWF SMUL2416L RETLW M2416SX CLRF CLRF RLF RRF RRF RRF RRF RETLW
BARGB0,MSB M2416SOK BARGB1, BARGB0, BARGB1, _Z BARGB0, AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, _Z AARGB0, F F F F F F F F F F
BARGB0,MSB M2416SX AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2
0x00 AARGB3 AARGB4 SIGN,W AARGB0,F AARGB1,F AARGB2,F AARGB3,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; 24x16 Bit Unsigned Fixed Point Multiply 24x16 -> 40 Input: 24 bit unsigned fixed point multiplicand in AARGB0 16 bit unsigned fixed point multiplier in BARGB0 CALL FXM2416U
Use:
8+324+2 = 334 clks 8+102 = 110 clks
DS00617B-page 95
AN617
; FXM2416U CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL2416L RETLW 0x00 AARGB3 AARGB4 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 ; clear partial product PM: 8+61+1 = 70 DM: 12
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM2315U CLRF CLRF MOVF MOVWF MOVF MOVWF MOVF MOVWF UMUL2315L RETLW 0x00 AARGB3 AARGB4 AARGB0,W TEMPB0 AARGB1,W TEMPB1 AARGB2,W TEMPB2 ; clear partial product 23x15 Bit Unsigned Fixed Point Divide 23x15 -> 38 Input: 23 bit unsigned fixed point multiplicand in AARGB0 15 bit unsigned fixed point multiplier in BARGB0 CALL FXM2315U
Use:
8+309+2 = 319 clks 8+96 = 104 clks DM: 12
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 96
AN617
D.6
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

SMUL1616L ; ; ;
0x8 LOOPCOUNT
DS00617B-page 97
AN617
RETLW ALOOPSM1616 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF ALSM1616NA RLF RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPSM1616 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF BLSM1616NA RLF RRF RRF RRF RRF DECFSZ GOTO RLF RRF RRF RRF RRF endm UMUL1616L ; ; ; macro 2+13+6*15+14+2+7*16+15 = 248 clks 2+7*6+5+1+7*6+5+4 = 101 clks DM: 9 MOVLW MOVWF LOOPUM1616A RRF BTFSC GOTO DECFSZ BARGB1, F _C ALUM1616NAP LOOPCOUNT, F 0x08 LOOPCOUNT BARGB0, F _C BLSM1616NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F BLOOPSM1616 SIGN,W AARGB0, AARGB1, AARGB2, AARGB3, BARGB1, F _C ALSM1616NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F ALOOPSM1616 0x7 LOOPCOUNT 0x00
F F F F
DS00617B-page 98
AN617
GOTO MOVWF LOOPUM1616B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF RETLW BLUM1616NAP BCF GOTO ALUM1616NAP BCF GOTO ALOOPUM1616 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF ALUM1616NA RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM1616 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF BLUM1616NA RRF RRF RRF RRF DECFSZ GOTO endm AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F BLOOPUM1616 BARGB0, F _C BLUM1616NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F ALOOPUM1616 0x08 LOOPCOUNT BARGB1, F _C ALUM1616NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F _C ALUM1616NA _C BLUM1616NA BARGB0, F _C BLUM1616NAP LOOPCOUNT, F LOOPUM1616B AARGB0 AARGB1 0x00 LOOPUM1616A LOOPCOUNT
DS00617B-page 99
AN617
UMUL1515L ; ; ; macro 2+13+6*15+14+2+6*16+15+4 = 236 clks 2+7*6+5+2+6*6+5+4 = 97 clks DM: 9 MOVLW MOVWF LOOPUM1515A RRF BTFSC GOTO DECFSZ GOTO MOVLW MOVWF LOOPUM1515B RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF RETLW BLUM1515NAP BCF GOTO ALUM1515NAP BCF GOTO ALOOPUM1515 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF ALUM1515NA RRF RRF RRF DECFSZ GOTO MOVLW MOVWF BLOOPUM1515 RRF BTFSS GOTO BARGB0, F _C BLUM1515NA AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F ALOOPUM1515 0x07 LOOPCOUNT BARGB1, F _C ALUM1515NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F _C ALUM1515NA _C BLUM1515NA BARGB0, F _C BLUM1515NAP LOOPCOUNT, F LOOPUM1515B AARGB0 AARGB1 0x00 BARGB1, F _C ALUM1515NAP LOOPCOUNT, F LOOPUM1515A 0x7 LOOPCOUNT 0x8 LOOPCOUNT
DS00617B-page 100
AN617
MOVF ADDWF MOVF BTFSC INCFSZ ADDWF BLUM1515NA RRF RRF RRF RRF DECFSZ GOTO AARGB0, F AARGB1, F AARGB2, F AARGB3, F LOOPCOUNT, F BLOOPUM1515 TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F
RRF RRF RRF RRF endm
F F F F
SMUL1616 ; ; ;
macro Max Timing: Min Timing: 5+6+7*11+7*12+4 = 176 clks 5+24+21+5 = 55 clks DM: 8
PM: 5+3*8+3*7+6+7*11+7*12+4 = 221 variable i = 0 BTFSC COMF MOVF MOVWF RLF while i < 8 BTFSC GOTO BCF BARGB1,i SM1616NA#v(i) AARGB2,7-i SIGN,MSB AARGB2, F AARGB2,W AARGB3 SIGN,W
variable i = i + 1 endw variable i = 8 while i < 15 BTFSC GOTO BCF BARGB0,i-8 SM1616NA#v(i) AARGB3,15-i
variable i =i + 1 endw CLRF CLRF RETURN AARGB0 AARGB1 ; if we get here, BARG = 0
DS00617B-page 101
AN617
SM1616NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF i < 8 BARGB1,i SM1616NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB0, F AARGB1, F AARGB2, F
SM1616A#v(i)
SM1616NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF i < 15 BARGB0,i-8 SM1616NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, AARGB1, AARGB2, AARGB3, F F F F
SM1616A#v(i)
SM1616NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF endm AARGB0, AARGB1, AARGB2, AARGB3, F F F F
UMUL1616 ; ; ;
macro Max Timing: Min Timing: 1+6+7*11+8*12 = 180 clks 1+2*8+2*8+4 = 37 clks DM: 8
PM: 1+2*8+2*8+4+7*11+8*12 = 210
DS00617B-page 102
AN617
variable i = i + 1 endw CLRF CLRF RETURN UM1616NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF i < 8 BARGB1,i UM1616NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB0 AARGB1 ; if we get here, BARG = 0
AARGB0, F AARGB1, F AARGB2, F
UM1616A#v(i)
UM1616NA#v(i)
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF i < 16 BARGB0,i-8 UM1616NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F
UM1616A#v(i)
UM1616NA#v(i)
DS00617B-page 103
AN617
RRF RRF AARGB2, F AARGB3, F
UMUL1515 ; ; ;
macro Max Timing: Min Timing: 7+7*11+7*12+4 = 172 clks 1+16+14+4 = 35 clks DM: 8
PM: 1+2*8+2*7+6+7*11+7*12+4 = 202
variable i = i + 1 endw CLRF CLRF RETURN UM1515NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF i < 8 BARGB1,i UM1515NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB0 AARGB1 ; if we get here, BARG = 0
UM1515A#v(i)
UM1515NA#v(i)
DS00617B-page 104
AN617
variable i = i + 1 endw variable i = 8 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF RRF i < 15 BARGB0,i-8 UM1515NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB3, F
UM1515A#v(i)
UM1515NA#v(i)
variable i = i + 1 endw RRF RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXM1616S 16x16 Bit Signed Fixed Point Multiply 16x16 -> 32 Input: 16 bit signed fixed point multiplicand in AARGB0 16 bit signed fixed point multiplier in BARGB0 CALL FXM1616S AARGB0, AARGB1, AARGB2, AARGB3, F F F F
Use:
9+249+2 = 260 clks 18+249+2 = 269 clks 9+96 = 105 clks DM: 9 AARGB2 AARGB3 SIGN AARGB0,W AARGB1,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB
Min Timing: PM: 18+55+1 = 74 CLRF CLRF CLRF MOVF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC
DS00617B-page 105
AN617
COMF BTFSS GOTO COMF COMF INCF BTFSC INCF COMF COMF INCF BTFSC INCF BTFSC GOTO M1616SOK MOVF MOVWF MOVF MOVWF SMUL1616L RETLW 0x00 SIGN,F BARGB0,MSB M1616SOK BARGB1, BARGB0, BARGB1, _Z BARGB0, AARGB1, AARGB0, AARGB1, _Z AARGB0, F F F F F F F F
BARGB0,MSB M1616SX AARGB0,W TEMPB0 AARGB1,W TEMPB1
M1616SX
CLRF CLRF RLF RRF RRF RRF RETLW
AARGB2 AARGB3 SIGN,W AARGB0,F AARGB1,F AARGB2,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM1616U CLRF CLRF MOVF MOVWF MOVF MOVWF AARGB2 AARGB3 AARGB0,W TEMPB0 AARGB1,W TEMPB1 ; clear partial product 16x16 Bit Unsigned Fixed Point Multiply 16x16 -> 32 Input: 16 bit unsigned fixed point multiplicand in AARGB0 16 bit unsigned fixed point multiplier in BARGB0 CALL FXM1616U
Use:
6+248+2 = 256 clks 6+101 = 107 clks DM: 9
DS00617B-page 106
AN617
UMUL1616L RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM1515U CLRF CLRF MOVF MOVWF MOVF MOVWF UMUL1515L RETLW 0x00 AARGB2 AARGB3 AARGB0,W TEMPB0 AARGB1,W TEMPB1 ; clear partial product 15x15 Bit Unsigned Fixed Point Divide 15x15 -> 30 Input: 15 bit unsigned fixed point multiplicand in AARGB0 15 bit unsigned fixed point multiplier in BARGB0 CALL FXM1515U
Use:
6+236+2 = 244 clks 6+97 = 103 clks DM: 9
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 107
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D.7
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 16x08 Bit Multiplication Macros macro 2+11+5*16+15+4 = 112 clks 2+6*6+5+4 = 47 clks DM: 7
SMUL1608L ; ; ;
MOVLW MOVWF LOOPSM1608A RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF RETLW LOOPSM1608 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC
0x07 LOOPCOUNT
BARGB0, F _C LSM1608NA LOOPCOUNT, F LOOPSM1608A AARGB0 AARGB1 0x00
BARGB0, F _C LSM1608NA TEMPB1,W AARGB1, F TEMPB0,W _C
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INCFSZ ADDWF LSM1608NA RLF RRF RRF RRF DECFSZ GOTO RLF RRF RRF RRF endm UMUL1608L ; ; ; macro 2+13+6*15+14 = 119 clks 2+7*6+5+4 = 54 clks DM: 7 MOVLW MOVWF LOOPUM1608A RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF RETLW LUM1608NAP BCF GOTO LOOPUM1608 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF DECFSZ GOTO endm BARGB0, F _C LUM1608NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F LOOPUM1608 _C LUM1608NA BARGB0, F _C LUM1608NAP LOOPCOUNT, F LOOPUM1608A AARGB0 AARGB1 0x00 0x08 LOOPCOUNT TEMPB0,W AARGB0, F SIGN,W AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F LOOPSM1608 SIGN,W AARGB0, F AARGB1, F AARGB2, F
LUM1608NA
UMUL1507L ;
macro 2+13+5*15+14+3 = 107 clks
Max Timing:
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; ; Min Timing: PM: 29 MOVLW MOVWF LOOPUM1507A RRF BTFSC GOTO DECFSZ GOTO CLRF CLRF RETLW LUM1507NAP BCF GOTO LOOPUM1507 RRF BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF DECFSZ GOTO RRF RRF RRF endm BARGB0, F _C LUM1507NA TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F LOOPCOUNT, F LOOPUM1507 AARGB0, F AARGB1, F AARGB2, F _C LUM1507NA BARGB0, F _C LUM1507NAP LOOPCOUNT, F LOOPUM1507A AARGB0 AARGB1 0x00 2+6*6+5+4 = 47 clks DM: 7 0x07 LOOPCOUNT
LUM1507NA
SMUL1608 ; ; ;
macro Max Timing: Min Timing: 3+6+6*11+3 = 78 clks 3+21+5 = 29 clks DM: 6
PM: 3+3*7+7+6*11+3 = 100 variable i =0 BTFSC COMF RLF while i < 7 BTFSC GOTO BCF SIGN,MSB AARGB2, F SIGN,W
BARGB0,i SM1608NA#v(i) AARGB2,7-i
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variable i = i + 1 endw CLRF CLRF CLRF RETURN SM1608NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF i < 7 BARGB0,i SM1608NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB0, F AARGB1, F AARGB2, F AARGB0 AARGB1 AARGB2 ; if we get here, BARG = 0
SM1608A#v(i)
SM1608NA#v(i)
variable i = i + 1 endw RRF RRF RRF endm AARGB0, F AARGB1, F AARGB2, F
UMUL1608 ; ; ;
macro Max Timing: Min Timing: 1+6+7*11 = 84 clks 1+2*8+4 = 21 clks DM: 4
PM: 1+2*8+4+6*7 = 63 variable i = 0 BCF while i < 8 BTFSC GOTO _C
; clear carry for first right shift
BARGB0,i UM1608NA#v(i)
variable i = i + 1 endw CLRF CLRF AARGB0 AARGB1 ; if we get here, BARG = 0
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RETURN UM1608NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RRF RRF RRF i < 8 BARGB0,i UM1608NA#v(i) TEMPB1,W AARGB1, F TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F AARGB0, F AARGB1, F AARGB2, F
UM1608A#v(i)
UM1608NA#v(i)
UMUL1507 ; ; ;
macro Max Timing: Min Timing: 7+6*12+4 = 83 clks 14+3 = 17 clks DM: 6
PM: 2*7+7+6*12+4 = 97 variable i = 0 BCF while i < 7 BTFSC GOTO _C
variable i = i + 1 endw CLRF CLRF RETURN UM1507NA0 RRF RRF RRF variable i = 1 while BTFSS GOTO MOVF ADDWF i < 7 BARGB0,i UM1507NA#v(i) TEMPB1,W AARGB1, F AARGB0 AARGB1 ; if we get here, BARG = 0
UM1507A#v(i)
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MOVF BTFSC INCFSZ ADDWF RRF RRF RRF TEMPB0,W _C TEMPB0,W AARGB0, F AARGB0, F AARGB1, F AARGB2, F
UM1507NA#v(i)
variable i = i + 1 endw RRF RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXM1608S 16x8 Bit Signed Fixed Point Multiply 16x8 -> 24 Input: 16 bit signed fixed point multiplicand in AARGB0 8 bit signed fixed point multiplier in BARGB0 CALL FXM1608S AARGB0, F AARGB1, F AARGB2, F
Use:
8+112+2 = 122 clks 14+112+2 = 128 clks 8+47 = 55 clks DM: 7 AARGB2 SIGN AARGB0,W AARGB1,W _Z 0x00 AARGB0,W BARGB0,W TEMPB0 TEMPB0,MSB SIGN,F BARGB0,MSB M1608SOK BARGB0,F BARGB0,F AARGB1, AARGB0, AARGB1, _Z AARGB0, F F F F
Min Timing: PM: 14+29+1 = 44 CLRF CLRF MOVF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF BTFSS GOTO COMF INCF COMF COMF INCF BTFSC INCF BTFSC GOTO
; make multiplier BARG > 0
BARGB0,MSB M1608SX
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M1608SOK MOVF MOVWF MOVF MOVWF SMUL1608 RETLW M1608SX CLRF RLF RRF RRF RRF RETLW 0x00 AARGB2 SIGN,W AARGB0,F AARGB1,F AARGB2,F 0x00 AARGB0,W TEMPB0 AARGB1,W TEMPB1
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM1608U 16x8 Bit Unsigned Fixed Point Multiply 16x8 -> 24 Input: 16 bit unsigned fixed point multiplicand in AARGB0 8 bit unsigned fixed point multiplier in BARGB0 CALL FXM1608U
Use:
Output: 24 bit unsigned fixed point product in AARGB0 Result: AARG Max Timing: Min Timing: PM: 5+26+1 = 31 CLRF MOVF MOVWF MOVF MOVWF UMUL1608L RETLW 0x00 <-AARG x BARG
5+119+2 = 126 clks 5+54 = 59 clks DM: 7 AARGB2 AARGB0,W TEMPB0 AARGB1,W TEMPB1 ; clear partial product
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; 15x7 Bit Unsigned Fixed Point Divide 15x7 -> 22 Input: 15 bit unsigned fixed point multiplicand in AARGB0 7 bit unsigned fixed point multiplier in BARGB0 CALL FXM0807U
Use:
5+107+2 = 114 clks 5+47 = 52 clks
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; FXM1507U PM: 5+29+1 = 35 CLRF MOVF MOVWF MOVF MOVWF UMUL1507 RETLW 0x00 DM: 7 AARGB2 AARGB0,W TEMPB0 AARGB1,W TEMPB1 ; clear partial product
;********************************************************************************************** ;**********************************************************************************************
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D.8
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 08x08 Bit Multiplication Macros macro 3+10+5*9+8+3 = 69 clks 3+6*6+5+3 = 47 clks DM: 5 MOVLW MOVWF MOVF LOOPSM0808A RRF BTFSC GOTO DECFSZ GOTO CLRF RETLW LOOPSM0808 RRF BTFSC ADDWF RLF RRF RRF DECFSZ BARGB0, F _C AARGB0, F SIGN, F AARGB0, F AARGB1, F LOOPCOUNT, F BARGB0, F _C LSM0808NA LOOPCOUNT, F LOOPSM0808A AARGB0 0x00 0x07 LOOPCOUNT AARGB0,W
SMUL0808L ; ; ;
LSM0808NA
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GOTO RLF RRF RRF LOOPSM0808 SIGN, F AARGB0, F AARGB1, F
endm UMUL0808L ; ; ; macro 3+12+6*8+7 = 70 clks 3+7*6+5+3 = 53 clks DM: 4 MOVLW MOVWF MOVF LOOPUM0808A RRF BTFSC GOTO DECFSZ GOTO CLRF RETLW LUM0808NAP BCF GOTO LOOPUM0808 RRF BTFSC ADDWF RRF RRF DECFSZ GOTO endm BARGB0, F _C AARGB0, F AARGB0, F AARGB1, F LOOPCOUNT, F LOOPUM0808 _C LUM0808NA BARGB0, F _C LUM0808NAP LOOPCOUNT, F LOOPUM0808A AARGB0 0x00 0x08 LOOPCOUNT AARGB0,W
LUM0808NA
UMUL0707L ; ; ;
macro 3+12+5*8+7+2 = 64 clks 3+6*6+5+3 = 47 clks DM: 4 MOVLW MOVWF MOVF 0x07 LOOPCOUNT AARGB0,W
LOOPUM0707A RRF BTFSC GOTO DECFSZ GOTO BARGB0, F _C LUM0707NAP LOOPCOUNT, F LOOPUM0707A
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CLRF RETLW LUM0707NAP BCF GOTO LOOPUM0707 RRF BTFSC ADDWF RRF RRF DECFSZ GOTO RRF RRF endm BARGB0, F _C AARGB0, F AARGB0, F AARGB1, F LOOPCOUNT, F LOOPUM0707 AARGB0, F AARGB1, F _C LUM0707NA AARGB0 0x00
LUM0707NA
SMUL0808 ; ; ;
PM: 1+2*7+5+6*5+3 = 53 variable i = 0 MOVF while i < 7 BTFSC GOTO AARGB0,W
BARGB0,i SM0808NA#v(i)
variable i = i + 1 endw CLRF RETURN SM0808NA0 RLF RRF RRF variable i = 1 while BTFSC ADDWF RLF RRF RRF i < 7 BARGB0,i AARGB0 SIGN AARGB0 AARGB1 AARGB0 ; if we get here, BARG = 0
SIGN AARGB0 AARGB1
SM0808NA#v(i)
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RLF RRF RRF endm SIGN AARGB0 AARGB1
UMUL0808 ; ; ;
macro Max Timing: Min Timing: 2+5+7*4 = 35 clks 2+16+3 = 21 clks DM: 3
PM: 2+2*8+4+7*4 = 50 variable i = 0 BCF MOVF while i < 8 BTFSC GOTO _C AARGB0,W
variable i = i + 1 endw CLRF RETURN UM0808NA0 RRF RRF variable i = 1 while BTFSC ADDWF RRF RRF i < 8 BARGB0,i AARGB0, F AARGB0, F AARGB1, F AARGB0 ; if we get here, BARG = 0
AARGB0, F AARGB1, F
UM0808NA#v(i)
UMUL0707 ; ; ;
PM: 2+2*7+4+6*4+2 = 46 variable i = 0 BCF MOVF while i < 7 _C AARGB0,W
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BTFSC GOTO BARGB0,i UM0707NA#v(i)
variable i = i + 1 endw CLRF RETURN UM0707NA0 RRF RRF variable i = 1 while BTFSC ADDWF RRF RRF i < 7 BARGB0,i AARGB0, F AARGB0, F AARGB1, F AARGB0 ; if we get here, BARG = 0
AARGB0, F AARGB1, F
UM0707NA#v(i)
variable i = i + 1 endw RRF RRF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; FXM0808S 8x8 Bit Signed Fixed Point Multiply 8x8 -> 16 Input: 8 bit signed fixed point multiplicand in AARGB0 8 bit signed fixed point multiplier in BARGB0 CALL FXM0808S AARGB0, F AARGB1, F
Use:
12+69+2 = 83 clks 17+69+2 = 88 clks 12+47 = 59 clks 6 clks DM: 5 AARGB1 SIGN AARGB0,W _Z 0x00 BARGB0,W TEMPB3 TEMPB3,MSB SIGN, F
Min Timing:
A = 0
PM: 17+21+1 = 39 CLRF CLRF MOVF BTFSC RETLW XORWF MOVWF BTFSC COMF
BTFSS
BARGB0,MSB
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GOTO COMF INCF COMF INCF BTFSC GOTO M0808SOK SMUL0808L RETLW M0808SX CLRF RLF RRF RRF RETLW 0x00 AARGB1 SIGN, W AARGB0, F AARGB1, F 0x00 M0808SOK BARGB0, F BARGB0, F AARGB0, F AARGB0, F BARGB0,MSB M0808SX ; make multiplier BARG > 0
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; FXM0808U 8x8 Bit Unsigned Fixed Point Multiply 8x8 -> 16 Input: 8 bit unsigned fixed point multiplicand in AARGB0 8 bit unsigned fixed point multiplier in BARGB0 CALL FXM0808U
Use:
Output: 8 bit unsigned fixed point product in AARGB0 Result: AARG Max Timing: Min Timing: PM: 1+19+1 = 21 CLRF UMUL0808L RETLW 0x00 <-AARG x BARG
1+70+2 = 73 clks 1+53 = 54 clks DM: 4 AARGB1 ; clear partial product
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; 7x7 Bit Unsigned Fixed Point Divide 7x7 -> 14 Input: 7 bit unsigned fixed point multiplicand in AARGB0 7 bit unsigned fixed point multiplier in BARGB0 CALL FXM0707U
Use:
1+64+2 = 67 clks 1+47 = 48 clks
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; FXM0707U PM: 1+21+1 = 23 CLRF UMUL0707L RETLW 0x00 DM: 4 AARGB1 ; clear partial product
;********************************************************************************************** ;**********************************************************************************************
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APPENDIX E: PIC16C5X/PIC16CXX DIVIDE ROUTINES

Table of Contents for Appendix E E.1 32/32 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 123 E.2 32/24 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 145 E.3 32/16 PIC16C5X/PIC16CXX Fixed Point Divide Routines ........................................................................... 163 E.4 24/24 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 178 E.5 24/16 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 193 E.6 16/16 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ......................................................................... 205 E.7 16/8 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ........................................................................... 216 E.8 8/8 PIC16C5X/PIC16CXXX Fixed Point Divide Routines ............................................................................. 228
E.1
; ;
32/32 PIC16C5X/PIC16CXXX Fixed Point Divide Routines

RCS Header $Id: fxd22.a16 2.4 1997/02/27 03:03:17 F.J.Testa Exp $ $Revision: 2.4 $
; 32/32 PIC16 FIXED POINT DIVIDE ROUTINES ; ; Input: fixed point arguments in AARG and BARG ; ; Output: quotient AARG/BARG followed by remainder in REM ; ; All timings are worst case cycle counts ; ; It is useful to note that the additional unsigned routines requiring a non-power of two ; argument can be called in a signed divide application where it is known that the ; respective argument is nonnegative, thereby offering some improvement in ; performance. ; ; Routine Clocks Function ; ; FXD3232S 929 32 bit/32 bit -> 32.32 signed fixed point divide ; ; FXD3232U 1031 32 bit/32 bit -> 32.32 unsigned fixed point divide ; ; FXD3131U 869 31 bit/31 bit -> 31.31 unsigned fixed point divide ; ;********************************************************************************************** ;********************************************************************************************** ; 32/32 Bit Division Macros macro 17+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+16 = 863 clks 17+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 819 clks DM: 13 BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W
SDIV3232L ; ; ;
PM: 17+7*38+16 = 299 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF
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BTFSS INCFSZ SUBWF RLF MOVLW MOVWF LOOPS3232A RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB0,LSB SADD22LA REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22LA REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPS3232A AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB0,LSB SADD22L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W
SOK22LA
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BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3232B RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB1,LSB SADD22LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
SOK22L8
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SOK22LB RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3232C RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF AARGB1, F LOOPCOUNT, F LOOPS3232B AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB1,LSB SADD22L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB2,LSB SADD22LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F
SOK22L16
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MOVF BTFSS INCFSZ SUBWF GOTO SADD22LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22L24 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW BARGB0,W _C BARGB0,W REMB0, F SOK22LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPS3232C AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB2,LSB SADD22L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F 7
SOK22LC
SOK22L24
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MOVWF LOOPS3232D RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD22LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF SOK22LD RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF SOK22L endm LOOPCOUNT AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB3,LSB SADD22LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK22LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F LOOPCOUNT, F LOOPS3232D AARGB3,LSB SOK22L BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
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UDIV3232L ; ; ; macro 24+6*32+31+31+6*32+31+31+6*32+31+31+6*32+31+16 = 1025 clks 24+6*31+30+30+6*31+30+30+6*31+30+30+6*31+30+3 = 981 clks DM: 13 CLRF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF RLF MOVLW MOVWF LOOPU3232A RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22LA ADDWF TEMP AARGB0,W REMB3, F BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F Max Timing: Min Timing: PM: 359
_C 1 TEMP, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB0,LSB UADD22LA REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22LA REMB3, F
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AN617
MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF UOK22LA RLF DECFSZ GOTO RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB0, F LOOPCOUNT, F LOOPU3232A AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB0,LSB UADD22L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C
DS00617B-page 130
AN617
MOVLW ADDWF UOK22L8 RLF MOVLW MOVWF LOOPU3232B RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF RLF 1 TEMP, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB1,LSB UADD22LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F LOOPCOUNT, F LOOPU3232B AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F
UOK22LB
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AN617
MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU3232C RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BARGB3,W AARGB1,LSB UADD22L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB2,LSB UADD22LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W
UOK22L16
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AN617
BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22L24 ADDWF MOVF BTFSC INCFSZ ADDWF _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F LOOPCOUNT, F LOOPU3232C AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB2,LSB UADD22L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F
UOK22LC
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AN617
MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF UOK22L24 RLF MOVLW MOVWF LOOPU3232D RLF RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD22LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB3, F 7 LOOPCOUNT AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,W AARGB3,LSB UADD22LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK22LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB3, F
UOK22LD
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DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK22L endm UDIV3131L ; ; ; macro 17+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+16 = 863 clks 17+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 819 clks DM: 13 BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB0,LSB UADD11LA REMB3, F BARGB2,W _C BARGB2,W REMB2, F LOOPCOUNT, F LOOPU3232D AARGB3,LSB UOK22L BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
PM: 17+7*38+16 = 299 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPU3131A
RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF
DS00617B-page 135
AN617
MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11LA REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPU3131A AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB0,LSB UADD11L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11L8 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK11LA
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UOK11L8 RLF MOVLW MOVWF LOOPU3131B RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ AARGB1, F 7 LOOPCOUNT AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB1,LSB UADD11LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11LB REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPU3131B AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB1,LSB UADD11L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W
UOK11LB
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AN617
SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3131C RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11L16 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB2,LSB UADD11LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11LC REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F
UOK11L16
UOK11LC
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DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD11L24 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3131D RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS LOOPCOUNT, F LOOPU3131C AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB2,LSB UADD11L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK11L24 REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F 7 LOOPCOUNT AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,W AARGB3,LSB UADD11LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C
UOK11L24
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INCFSZ SUBWF GOTO UADD11LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK11LD RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK11L endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; 32/32 Bit Signed Fixed Point Divide 32/32 -> 32.32 Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 32 bit fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 CALL FXD3232S BARGB0,W REMB0, F UOK11LD REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F LOOPCOUNT, F LOOPU3131D AARGB3,LSB UOK11L BARGB3,W REMB3, F BARGB2,W _C BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
Use:
Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 32 bit fixed point remainder in REMB0, REMB1, REMB2, REMB3 Result: AARG, REM Max Timing: <-AARG / BARG = = = = 896 clks 929 clks 929 clks 916 clks 12 clks A A A A A > > < < = 0, 0, 0, 0, 0 B B B B > < > < 0 0 0 0
28+863+5 38+863+28 38+863+28 48+863+5
Min Timing:
28+819+5
= 852 clks
A > 0, B > 0
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AN617
; ; ; ; FXD3232S 38+819+28 = 885 clks 38+819+28 = 885 clks 48+819+5 = 872 clks PM: 48+299+27+67 = 441 CLRF CLRF CLRF CLRF CLRF MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF CA3232S BTFSS GOTO COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF C3232SX MOVF IORWF MOVWF BTFSC GOTO SDIV3232L BTFSC GOTO TEMPB3,LSB C3232SX4 ; test exception flag SIGN REMB0 REMB1 REMB2 REMB3 AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA3232S BARGB3, BARGB2, BARGB1, BARGB0, BARGB3, _Z BARGB2, _Z BARGB1, _Z BARGB0, F F F F F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 DM: 15
; clear partial remainder
AARGB0,MSB C3232SX AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C3232SX1 F F F F F F F F
C3232S
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AN617
C3232SOK BTFSS RETLW COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF RETLW C3232SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF CLRF CLRF CLRF CLRF GOTO CLRF CLRF CLRF CLRF INCF RETLW COMF COMF COMF COMF INCF GOTO INCF BTFSC INCF BTFSC INCF SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, REMB3, REMB2, REMB1, REMB0, REMB3, _Z REMB2, _Z REMB1, _Z REMB0, 0x00 BARGB0,MSB C3232SX3 AARGB0,MSB C3232SX2 AARGB0,W REMB0 AARGB1,W REMB1 AARGB2,W REMB2 AARGB3,W REMB3 AARGB0 AARGB1 AARGB2 AARGB3 C3232SOK AARGB0 AARGB1 AARGB2 AARGB3 AARGB3,F 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3232S REMB3,F _Z REMB2,F _Z REMB1,F ; test BARG exception ; test AARG exception F F F F F F F F F F F F F F F F
; quotient = 0, remainder = AARG
C3232SX2
; quotient = 1, remainder = 0
C3232SX3
; numerator = 0x7FFFFFFF + 1
C3232SX4
; increment remainder and test for ; overflow
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AN617
BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO CLRF CLRF CLRF CLRF INCF BTFSC INCF BTFSC INCF BTFSC INCF BTFSS GOTO BSF RETLW _Z REMB0,F BARGB3,W REMB3,W _Z C3232SOK BARGB2,W REMB2,W _Z C3232SOK BARGB1,W REMB1,W _Z C3232SOK BARGB0,W REMB0,W _Z C3232SOK REMB0 REMB1 REMB2 REMB3 AARGB3,F _Z AARGB2,F _Z AARGB1,F _Z AARGB0,F AARGB0,MSB C3232SOK FPFLAGS,NAN 0xFF
; if remainder overflow, clear ; remainder, increment quotient and
; test for overflow exception
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD3232U 32/32 Bit Unsigned Fixed Point Divide 32/32 -> 32.32 Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 CALL FXD3232U
Use:
Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 32 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3 Result: AARG, REM Max Timing: Max Timing: <-AARG / BARG
4+1025+2 = 1031 clks 4+981+2 = 987 clks DM: 13 REMB0 REMB1 REMB2 REMB3
PM: 4+359+1 = 364 CLRF CLRF CLRF CLRF UDIV3232L RETLW 0x00
;********************************************************************************************** ;**********************************************************************************************
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; ; ; ; ; ; ; ; ; ; FXD3131U 31/31 Bit Unsigned Fixed Point Divide 31/31 -> 31.31 Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2, BARGB3 CALL FXD3131U
Use:
Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3 Result: AARG, REM Max Timing: Min Timing: <-AARG / BARG
4+863+2 = 869 clks 4+819+2 = 825 clks DM: 13 REMB0 REMB1 REMB2 REMB3
PM: 4+299+1 = 304 CLRF CLRF CLRF CLRF UDIV3131L RETLW 0x00
;********************************************************************************************** ;**********************************************************************************************
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E.2
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

RCS Header $Id: fxd24.a16 2.3 1996/10/16 14:23:57 F.J.Testa Exp $ $Revision: 2.3 $ 32/24 PIC16 FIXED POINT DIVIDE ROUTINES Input: fixed point arguments in AARG and BARG
Output: quotient AARG/BARG followed by remainder in REM All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed divide application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine FXD3224S FXD3224U FXD3123U Clocks 759 867 705 Function 32 bit/24 bit -> 32.24 signed fixed point divide 32 bit/24 bit -> 32.24 unsigned fixed point divide 31 bit/23 bit -> 31.23 unsigned fixed point divide
;********************************************************************************************** ;********************************************************************************************** ; 32/24 Bit Division Macros macro 13+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+12 = 700 clks 13+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 660 clks DM: 10 BARGB2,W REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB0,F 7 LOOPCOUNT AARGB0,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB0,LSB SADD24LA REMB2,F BARGB1,W _C
SDIV3224L ; ; ;
PM: 11+3*58+43 = 228 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPS3224A
RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS
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INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3224B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24LA REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB0,F LOOPCOUNT,F LOOPS3224A AARGB1,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB0,LSB SADD24L8 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24L8 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB1,F 7 LOOPCOUNT AARGB1,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB1,LSB SADD24LB REMB2,F
SOK24LA
SOK24L8
DS00617B-page 146
AN617
MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3224C RLF RLF RLF RLF MOVF BTFSS GOTO BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24LB REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB1,F LOOPCOUNT,F LOOPS3224B AARGB2,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB1,LSB SADD24L16 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24L16 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB2,F 7 LOOPCOUNT AARGB2,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB2,LSB SADD24LC
SOK24LB
SOK24L16
DS00617B-page 147
AN617
SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24L24 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3224D RLF RLF RLF RLF MOVF REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24LC REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB2,F LOOPCOUNT,F LOOPS3224C AARGB3,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB2,LSB SADD24L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB3,F 7 LOOPCOUNT AARGB3,W REMB2,F REMB1,F REMB0,F BARGB2,W
SOK24LC
SOK24L24
DS00617B-page 148
AN617
BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD24LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF SOK24L endm UDIV3224L ; ; ; macro 20+6*27+26+26+6*27+26+26+6*27+26+26+6*27+26+12 = 862 clks 20+6*26+25+25+6*26+25+25+6*26+25+25+6*26+25+3 = 822 clks DM: 11 TEMP AARGB0,W REMB2,F BARGB2,W REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W AARGB3,LSB SADD24LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F SOK24LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB3,F LOOPCOUNT,F LOOPS3224D AARGB3,LSB SOK24L BARGB2,W REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F
SOK24LD
PM: 18+3*75+40+12 = 295 CLRF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ
DS00617B-page 149
AN617
SUBWF CLRW BTFSS MOVLW SUBWF RLF MOVLW MOVWF LOOPU3224A RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS REMB0,F
_C 1 TEMP,F AARGB0,F 7 LOOPCOUNT AARGB0,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB0,LSB UADD24LA REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24LA REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F AARGB0,F LOOPCOUNT,F LOOPU3224A AARGB1,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB0,LSB UADD24L8 REMB2,F BARGB1,W _C
UOK24LA
DS00617B-page 150
AN617
INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU3224B RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24L8 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F AARGB1,F 7 LOOPCOUNT AARGB1,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB1,LSB UADD24LB REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24LB REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C
UOK24L8
DS00617B-page 151
AN617
MOVLW ADDWF UOK24LB RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU3224C RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF 1 TEMP,F AARGB1,F LOOPCOUNT,F LOOPU3224B AARGB2,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB1,LSB UADD24L16 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24L16 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F AARGB2,F 7 LOOPCOUNT AARGB2,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB2,LSB UADD24LC REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W
UOK24L16
DS00617B-page 152
AN617
BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24L24 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24LC REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F AARGB2,F LOOPCOUNT,F LOOPU3224C AARGB3,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB2,LSB UADD24L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F
UOK24LC
DS00617B-page 153
AN617
UOK24L24 RLF MOVLW MOVWF LOOPU3224D RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD24LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK24L endm UDIV3123L macro AARGB3,F 7 LOOPCOUNT AARGB3,W REMB2,F REMB1,F REMB0,F TEMP,F BARGB2,W AARGB3,LSB UADD24LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F UOK24LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F _C 1 TEMP,F AARGB3,F LOOPCOUNT,F LOOPU3224D AARGB3,LSB UOK24L BARGB2,W REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F
UOK24LD
DS00617B-page 154
AN617
; ; ; Max Timing: Min Timing: 13+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+12 = 700 clks 13+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 660 clks DM: 10 BARGB2,W REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB0,F 7 LOOPCOUNT AARGB0,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB0,LSB UADD13LA REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13LA REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB0,F LOOPCOUNT,F LOOPU3123A AARGB1,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB0,LSB UADD13L8 REMB2,F BARGB1,W
PM: 11+3*58+43 = 228 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPU3123A
RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO
UADD13LA
ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF
UOK13LA
DS00617B-page 155
AN617
BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3123B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13L8 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB1,F 7 LOOPCOUNT AARGB1,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB1,LSB UADD13LB REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13LB REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB1,F LOOPCOUNT,F LOOPU3123B AARGB2,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB1,LSB UADD13L16
UOK13L8
UOK13LB
DS00617B-page 156
AN617
SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3123C RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13L16 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB2,F 7 LOOPCOUNT AARGB2,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB2,LSB UADD13LC REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13LC REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB2,F LOOPCOUNT,F LOOPU3123C AARGB3,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB2,LSB
UOK13L16
UOK13LC
DS00617B-page 157
AN617
GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13L24 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3123D RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD13LD ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF UADD13L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13L24 REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB3,F 7 LOOPCOUNT AARGB3,W REMB2,F REMB1,F REMB0,F BARGB2,W AARGB3,LSB UADD13LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F UOK13LD REMB2,F BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F AARGB3,F LOOPCOUNT,F LOOPU3123D AARGB3,LSB UOK13L BARGB2,W REMB2,F
UOK13L24
UOK13LD
DS00617B-page 158
AN617
MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK13L endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FXD3224S 32/24 Bit Signed Fixed Point Divide 32/24 -> 32.24 Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 24 bit fixed point divisor in BARGB0, BARGB1, BARGB2 CALL FXD3224S BARGB1,W _C BARGB1,W REMB1,F BARGB0,W _C BARGB0,W REMB0,F
Use:
Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 24 bit fixed point remainder in REMB0, REMB1, REMB2 Result: AARG, REM Max Timing: <-AARG / BARG = = = = 732 clks 759 clks 759 clks 749 clks 11 clks 692 719 749 709 clks clks clks clks A A A A A A A A A > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
27+700+5 34+700+25 34+700+25 44+700+5
Min Timing:
27+660+5 34+660+25 34+660+25 44+660+5
= = = =
B B B B
> < > <
0 0 0 0
PM: 44+228+24+62 = 358 CLRF CLRF CLRF CLRF MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF INCF SIGN REMB0 REMB1 REMB2 AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA3224S BARGB2, BARGB1, BARGB0, BARGB2, F F F F
DM: 13
; clear exception flag ; if MSB set, negate BARG
DS00617B-page 159
AN617
BTFSC INCF BTFSC INCF CA3224S BTFSS GOTO COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF C3224SX MOVF IORWF MOVWF BTFSC GOTO SDIV3224L BTFSC GOTO C3224SOK BTFSS RETLW COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF COMF COMF COMF INCF BTFSC INCF BTFSC INCF RETLW C3224SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF MOVF MOVWF MOVF TEMPB3,LSB C3224SX4 SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, REMB2, REMB1, REMB0, REMB2, _Z REMB1, _Z REMB0, 0x00 BARGB0,MSB C3224SX3 AARGB0,MSB C3224SX2 AARGB1,W REMB0 AARGB2,W REMB1 AARGB3,W ; test BARG exception ; test AARG exception F F F F F F F F F F F F F F ; test exception flag _Z BARGB1, F _Z BARGB0, F AARGB0,MSB C3224SX AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C3224SX1 F F F F F F F F ; if MSB set, negate AARG
C3224S
DS00617B-page 160
AN617
MOVWF BCF RLF RLF MOVF MOVWF CLRF CLRF CLRF GOTO CLRF INCF CLRF CLRF CLRF RETLW COMF COMF COMF COMF INCF GOTO INCF BTFSC INCF BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO CLRF CLRF CLRF INCF BTFSC INCF BTFSC INCF BTFSC INCF BTFSS GOTO BSF RETLW REMB2 REMB0,MSB AARGB1,F AARGB0,F AARGB0,W AARGB3 AARGB0 AARGB1 AARGB2 C3224SOK AARGB3 AARGB3,F AARGB2 AARGB1 AARGB0 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3224S REMB2,F _Z REMB1,F _Z REMB0,F BARGB2,W REMB2,W _Z C3224SOK BARGB1,W REMB1,W _Z C3224SOK BARGB0,W REMB0,W _Z C3224SOK REMB0 REMB1 REMB2 AARGB3,F _Z AARGB2,F _Z AARGB1,F _Z AARGB0,F AARGB0,MSB C3224SOK FPFLAGS,NAN 0xFF
C3224SX2
C3224SX3
C3224SX4
; increment remainder and test for
; overflow
; if remainder overflow, clear
; remainder, increment quotient and
;********************************************************************************************** ;********************************************************************************************** ; ; ; 32/24 Bit Unsigned Fixed Point Divide 32/24 -> 32.24 Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2
DS00617B-page 161
AN617
; ; ; ; ; ; ; FXD3224U Use: CALL FXD3224U Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 Result: AARG, REM Max Timing: Min Timing: <-AARG / BARG
3+862+2 = 867 clks 3+822+2 = 827 clks DM: 11 REMB0 REMB1 REMB2
PM: 3+295+1 = 299 CLRF CLRF CLRF UDIV3224L RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD3123U 31/23 Bit Unsigned Fixed Point Divide 31/23 -> 31.23 Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2 CALL FXD3123U
Use:
Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 Result: AARG, REM Max Timing: Min Timing: <-AARG / BARG
;********************************************************************************************** ;********************************************************************************************** END
DS00617B-page 162
AN617
E.3
; ;
32/16 PIC16C5X/PIC16CXX Fixed Point Divide Routines

; 32/16 PIC16 FIXED POINT DIVIDE ROUTINES ; ; Input: fixed point arguments in AARG and BARG ; ; Output: quotient AARG/BARG followed by remainder in REM ; ; All timings are worst case cycle counts ; ; It is useful to note that the additional unsigned routines requiring a non-power of two ; argument can be called in a signed divide application where it is known that the ; respective argument is nonnegative, thereby offering some improvement in ; performance. ; ; Routine Clocks Function ; ; FXD3216S 595 32 bit/16 bit -> 32.16 signed fixed point divide ; ; FXD3216U 703 32 bit/16 bit -> 32.16 unsigned fixed point divide ; ; FXD3115U 541 31 bit/15 bit -> 31.15 unsigned fixed point divide ; ;********************************************************************************************** ;********************************************************************************************** ; 32/16 Bit Division Macros macro 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks DM: 9 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF LOOPS3216A RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26LA ADDWF MOVF BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB SADD26LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26LA REMB1, F BARGB0,W
SDIV3216L ; ; ;
DS00617B-page 163
AN617
BTFSC INCFSZ ADDWF SOK26LA RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26L8 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3216B RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26LB ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPS3216A AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB SADD26L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD26LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPS3216B AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD26L16
SOK26L8
SOK26LB
DS00617B-page 164
AN617
SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26L16 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS3216C RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26LC ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26L24 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB2,LSB SADD26LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPS3216C AARGB3,W REMB1, F REMB0, F BARGB1,W AARGB2,LSB SADD26L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F 7
SOK26L16
SOK26LC
SOK26L24
DS00617B-page 165
AN617
MOVWF LOOPS3216D RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD26LD ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF SOK26L endm UDIV3216L ; ; ; macro 16+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+8 = 699 clks 16+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 663 clks DM: 9 CLRF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF RLF MOVLW MOVWF TEMP AARGB0,W REMB1, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB0, F 7 LOOPCOUNT LOOPCOUNT AARGB3,W REMB1, F REMB0, F BARGB1,W AARGB3,LSB SADD26LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK26LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F LOOPCOUNT, F LOOPS3216D AARGB3,LSB SOK26L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
SOK26LD
DS00617B-page 166
AN617
LOOPU3216A RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26LA ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26L8 ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW AARGB0,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB0,LSB UADD26LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB0, F LOOPCOUNT, F LOOPU3216A AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB0,LSB UADD26L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F 7
UOK26LA
UOK26L8
DS00617B-page 167
AN617
MOVWF LOOPU3216B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26LB ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26L16 ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF LOOPCOUNT AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB1,LSB UADD26LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F LOOPCOUNT, F LOOPU3216B AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB1,LSB UADD26L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F
UOK26LB
UOK26L16
DS00617B-page 168
AN617
MOVLW MOVWF LOOPU3216C RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26LC ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26L24 ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB2,LSB UADD26LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F LOOPCOUNT, F LOOPU3216C AARGB3,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB2,LSB UADD26L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F
UOK26LC
DS00617B-page 169
AN617
UOK26L24 RLF MOVLW MOVWF LOOPU3216D RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD26LD ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK26L endm UDIV3115L ; ; ; macro 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks DM: 9 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F 7 LOOPCOUNT AARGB3,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB3,LSB UADD26LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK26LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB3, F LOOPCOUNT, F LOOPU3216D AARGB3,LSB UOK26L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK26LD
DS00617B-page 170
AN617
RLF MOVLW MOVWF LOOPU3115A RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15LA ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15L8 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3115B RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ AARGB0, F 7 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD15LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPU3115A AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD15L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD15LB REMB1, F BARGB0,W _C BARGB0,W
UOK15LA
UOK15L8
DS00617B-page 171
AN617
SUBWF GOTO UADD15LB ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15L16 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3115C RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15LC ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF REMB0, F UOK15LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPU3115B AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD15L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB2,LSB UADD15LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPU3115C AARGB3,W REMB1, F
UOK15LB
UOK15L16
UOK15LC
DS00617B-page 172
AN617
RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15L24 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU3115D RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD15LD ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK15L endm ;********************************************************************************************** ;********************************************************************************************** ; ; 32/16 Bit Signed Fixed Point Divide 32/16 -> 32.16 Input: 32 bit fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 REMB0, F BARGB1,W AARGB2,LSB UADD15L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15L24 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F 7 LOOPCOUNT AARGB3,W REMB1, F REMB0, F BARGB1,W AARGB3,LSB UADD15LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK15LD REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB3, F LOOPCOUNT, F LOOPU3115D AARGB3,LSB UOK15L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK15L24
UOK15LD
DS00617B-page 173
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; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FXD3216S Use: 16 bit fixed point divisor in BARGB0, BARGB1 CALL FXD3216S
Output: 32 bit fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 16 bit fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: <-AARG / BARG = = = = 568 clks 589 clks 595 clks 582 clks 10 clks 532 553 559 546 clks clks clks clks DM: 12 SIGN REMB0 REMB1 AARGB0,W AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,W BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA3216S BARGB1, BARGB0, BARGB1, _Z BARGB0, F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG A A A A A A A A A > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
26+537+5 30+537+22 36+537+22 40+537+5
Min Timing:
26+501+5 30+501+22 36+501+22 40+501+5
= = = =
B B B B
> < > <
0 0 0 0
PM: 40+157+21+55 = 273 CLRF CLRF CLRF MOVF IORWF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF BTFSC INCF
CA3216S
BTFSS GOTO COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF
AARGB0,MSB C3216SX AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, AARGB0,W BARGB0,W F F F F F F F F
C3216SX
MOVF IORWF
DS00617B-page 174
AN617
MOVWF BTFSC GOTO C3216S SDIV3216L BTFSC GOTO C3216SOK BTFSS RETLW COMF COMF COMF COMF INCF BTFSC INCF BTFSC INCF BTFSC INCF COMF COMF INCF BTFSC INCF RETLW C3216SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF MOVF MOVWF BCF RLF RLF RLF MOVF MOVWF MOVF MOVWF CLRF CLRF GOTO CLRF INCF CLRF CLRF CLRF RETLW COMF COMF COMF COMF INCF GOTO INCF TEMPB3,LSB C3216SX4 SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, _Z AARGB2, _Z AARGB1, _Z AARGB0, REMB1, REMB0, REMB1, _Z REMB0, 0x00 BARGB0,MSB C3216SX3 AARGB0,MSB C3216SX2 AARGB2,W REMB0 AARGB3,W REMB1 REMB0,MSB AARGB2,F AARGB1,F AARGB0,F AARGB0,W AARGB2 AARGB1,W AARGB3 AARGB0 AARGB1 C3216SOK AARGB3 AARGB3,F AARGB2 AARGB1 AARGB0 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3216S REMB1,F ; test BARG exception ; test AARG exception F F F F F F F F F F F F ; test exception flag TEMP TEMP,MSB C3216SX1
C3216SX2
C3216SX3
C3216SX4
DS00617B-page 175
AN617
BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO CLRF CLRF INCF BTFSC INCF BTFSC INCF BTFSC INCF BTFSS GOTO BSF RETLW _Z REMB0,F BARGB1,W REMB1,W _Z C3216SOK BARGB0,W REMB0,W _Z C3216SOK REMB0 REMB1 AARGB3,F _Z AARGB2,F _Z AARGB1,F _Z AARGB0,F AARGB0,MSB C3216SOK FPFLAGS,NAN 0xFF ; overflow
; overflow
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD3216U 32/16 Bit Unsigned Fixed Point Divide 32/16 -> 32.16 Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 16 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD3216U
Use:
Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 16 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: Max Timing: <-AARG / BARG
2+699+2 = 703 clks 2+663+2 = 667 clks DM: 9 REMB0 REMB1
PM: 2+240+1 = 243 CLRF CLRF UDIV3216L RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; 31/15 Bit Unsigned Fixed Point Divide 31/15 -> 31.15 Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 15 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD3115U
Use:
Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 15 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM <-AARG / BARG
DS00617B-page 176
AN617
; ; ; FXD3115U Max Timing: Min Timing: 2+537+2 = 541 clks 2+501+2 = 505 clks DM: 9 REMB0 REMB1
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 177
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E.4
; ;

; 24/24 PIC16 FIXED POINT DIVIDE ROUTINES ; ; Input: fixed point arguments in AARG and BARG ; ; Output: quotient AARG/BARG followed by remainder in REM ; ; All timings are worst case cycle counts ; ; It is useful to note that the additional unsigned routines requiring a non-power of two ; argument can be called in a signed divide application where it is known that the ; respective argument is nonnegative, thereby offering some improvement in ; performance. ; ; Routine Clocks Function ; ; FXD2424S 581 24 bit/24 bit -> 24.24 signed fixed point divide ; ; FXD2424U 676 24 bit/24 bit -> 24.24 unsigned fixed point divide ; ; FXD2323U 531 23 bit/23 bit -> 23.23 unsigned fixed point divide ;********************************************************************************************** ;**********************************************************************************************
24/24 Bit Division Macros macro 13+6*22+21+21+6*22+21+21+6*22+21+12 = 526 clks 13+6*21+20+20+6*21+20+20+6*21+20+3 = 494 clks DM: 12 BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB0,LSB SADD44LA REMB2, F BARGB1,W _C BARGB1,W
SDIV2424L ; ; ;
PM: 11+3*51+31+12 = 207 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPS2424A
RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ
DS00617B-page 178
AN617
SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD44LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD44L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS2424B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK44LA REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPS2424A AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB0,LSB SADD44L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK44L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB1,LSB SADD44LB REMB2, F BARGB1,W
SOK44LA
SOK44L8
DS00617B-page 179
AN617
BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD44LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD44L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS2424C RLF RLF RLF RLF MOVF BTFSS GOTO _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK44LB REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPS2424B AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB1,LSB SADD44L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK44L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB2,LSB SADD44LC
SOK44LB
SOK44L16
DS00617B-page 180
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SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD44LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF SOK44L endm UDIV2424L ; ; ; macro 20+6*28+27+27+6*28+27+27+6*28+27+12 = 671 clks 20+6*27+26+26+6*27+26+26+6*27+26+3 = 639 clks DM: 13 TEMP AARGB0,W REMB2, F BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK44LC REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPS2424C AARGB2,LSB SOK44L BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
SOK44LC
PM: 18+2*76+40+12 = 222 CLRF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW
DS00617B-page 181
AN617
BTFSS MOVLW SUBWF RLF MOVLW MOVWF LOOPU2424A RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD44LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF _C 1 TEMP, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,W AARGB0,LSB UADD44LA REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK44LA REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB0, F LOOPCOUNT, F LOOPU2424A AARGB1,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,W AARGB0,LSB UADD44L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W
UOK44LA
DS00617B-page 182
AN617
BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD44L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU2424B RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD44LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF _C BARGB0,W REMB0, F _C 1 TEMP, F UOK44L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,W AARGB1,LSB UADD44LB REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK44LB REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F
UOK44L8
DS00617B-page 183
AN617
UOK44LB RLF DECFSZ GOTO RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD44L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU2424C RLF RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF AARGB1, F LOOPCOUNT, F LOOPU2424B AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,W AARGB1,LSB UADD44L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK44L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,W AARGB2,LSB UADD44LC REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK44L16
DS00617B-page 184
AN617
CLRW BTFSS MOVLW SUBWF GOTO UADD44LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK44L endm UDIV2323L ; ; ; macro 13+6*22+21+21+6*22+21+21+6*22+21+12 = 526 clks 13+6*21+20+20+6*21+20+20+6*21+20+3 = 494 clks DM: 12 BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W _C 1 TEMP, F UOK44LC REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F LOOPCOUNT, F LOOPU2424C AARGB2,LSB UOK44L BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK44LC
PM: 11+3*51+31+12 = 207 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPU2323A
RLF
DS00617B-page 185
AN617
RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD33LA ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD33L8 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF REMB2, F REMB1, F REMB0, F BARGB2,W AARGB0,LSB UADD33LA REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK33LA REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPU2323A AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB0,LSB UADD33L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK33L8 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT
UOK33LA
UOK33L8
DS00617B-page 186
AN617
LOOPU2323B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD33LB ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD33L16 ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB1,LSB UADD33LB REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK33LB REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPU2323B AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB1,LSB UADD33L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK33L16 REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F
UOK33LB
UOK33L16
DS00617B-page 187
AN617
MOVLW MOVWF LOOPU2323C RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD33LC ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF MOVF BTFSC INCFSZ ADDWF UOK33L endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; 24/24 Bit Signed Fixed Point Divide 24/24 -> 24.24 Input: 24 bit fixed point dividend in AARGB0, AARGB1,AARGB2 24 bit fixed point divisor in BARGB0, BARGB1, BARGB2 CALL FXD2424S 7 LOOPCOUNT AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,W AARGB2,LSB UADD33LC REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK33LC REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPU2323C AARGB2,LSB UOK33L BARGB2,W REMB2, F BARGB1,W _C BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK33LC
Use:
Output: 24 bit fixed point quotient in AARGB0, AARGB1,AARGB2 24 bit fixed point remainder in REMB0, REMB1, REMB2
DS00617B-page 188
AN617
; ; ; ; ; ; ; ; ; ; ; FXD2424S Result: AARG, REM Max Timing: <-AARG / BARG = = = = 557 clks 581 clks 581 clks 571 clks 10 clks 525 549 549 539 clks clks clks clks A A A A A A A A A > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0 26+526+5 33+526+22 33+526+22 40+526+5
Min Timing:
26+494+5 33+494+22 33+494+22 40+494+5
= = = =
B B B B
> < > <
0 0 0 0
PM: 40+207+21+53 = 321 CLRF CLRF CLRF CLRF MOVF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF INCF BTFSC INCF BTFSC INCF SIGN REMB0 REMB1 REMB2 AARGB0,W AARGB1,W AARGB2,W _Z 0x00 AARGB0,W BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA2424S BARGB2, BARGB1, BARGB0, BARGB2, _Z BARGB1, _Z BARGB0, F F F F F F
DM: 14
; clear exception flag ; if MSB set, negate BARG
CA2424S
BTFSS GOTO COMF COMF COMF INCF BTFSC INCF BTFSC INCF
AARGB0,MSB C2424SX AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C2424SX1 F F F F F F
; if MSB set, negate AARG
C2424SX
MOVF IORWF MOVWF BTFSC GOTO SDIV2424L
C2424S
DS00617B-page 189
AN617
BTFSC GOTO C2424SOK BTFSS RETLW COMF COMF COMF INCF BTFSC INCF BTFSC INCF COMF COMF COMF INCF BTFSC INCF BTFSC INCF RETLW C2424SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF MOVF MOVWF MOVF MOVWF CLRF CLRF CLRF GOTO CLRF CLRF CLRF INCF RETLW COMF COMF COMF INCF GOTO INCF BTFSC INCF BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO MOVF TEMPB3,LSB C2424SX4 SIGN,MSB 0x00 AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, _Z AARGB0, REMB2, REMB1, REMB0, REMB2, _Z REMB1, _Z REMB0, 0x00 BARGB0,MSB C2424SX3 AARGB0,MSB C2424SX2 AARGB0,W REMB0 AARGB1,W REMB1 AARGB2,W REMB2 AARGB0 AARGB1 AARGB2 C2424SOK AARGB0 AARGB1 AARGB2 AARGB2,F 0x00 AARGB0,F AARGB1,F AARGB2,F TEMPB3,F C2424S REMB2,F _Z REMB1,F _Z REMB0,F BARGB2,W REMB2,W _Z C2424SOK BARGB1,W REMB1,W _Z C2424SOK BARGB0,W ; test BARG exception ; test AARG exception F F F F F F F F F F F F ; test exception flag
; quotient = 0, remainder = AARG
C2424SX2
C2424SX3
; numerator = 0x7FFFFF + 1
C2424SX4
DS00617B-page 190
AN617
SUBWF BTFSS GOTO CLRF CLRF CLRF INCF BTFSC INCF BTFSC INCF BTFSS GOTO BSF RETLW REMB0,W _Z C2424SOK REMB0 REMB1 REMB2 AARGB2,F _Z AARGB1,F _Z AARGB0,F AARGB0,MSB C2424SOK FPFLAGS,NAN 0xFF
; if remainder overflow, clear ; remainder, increment quotient and ; test for overflow exception
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD2424U 24/24 Bit Unsigned Fixed Point Divide 24/24 -> 24.24 Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 CALL FXD2424U
Use:
Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 Result: AARG, REM Max Timing: Max Timing: <-AARG / BARG
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; 23/23 Bit Unsigned Fixed Point Divide 23/23 -> 23.23 Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARBB2 CALL FXD2323U
Use:
Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 Result: AARG, REM Max Timing: Min Timing: <-AARG / BARG
3+526+2 = 531 clks 3+494+2 = 499 clks DM: 12
PM: 3+207+1 = 211
DS00617B-page 191
AN617
FXD2323U CLRF CLRF CLRF UDIV2323L RETLW 0x00 REMB0 REMB1 REMB2
;********************************************************************************************** ;********************************************************************************************** END
DS00617B-page 192
AN617
E.5
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 24/16 Bit Division Macros macro 9+6*17+16+16+6*17+16+16+6*17+16+8 = 403 clks 9+6*16+15+15+6*16+15+15+6*16+15+3 = 375 clks DM: 7 BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB SADD46LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK46LA REMB1, F BARGB0,W
SDIV2416L ; ; ;
PM: 7+2*40+22+8 = 117 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPS2416A
RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO
SADD46LA
ADDWF MOVF
DS00617B-page 193
AN617
BTFSC INCFSZ ADDWF SOK46LA RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD46L8 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS2416B RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD46LB ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPS2416A AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB SADD46L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK46L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD46LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK46LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPS2416B AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD46L16
SOK46L8
SOK46LB
DS00617B-page 194
AN617
SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD46L16 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPS2416C RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD46LC ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF SOK46L endm UDIV2416L ; ; ; macro 16+6*22+21+21+6*22+21+21+6*22+21+8 = 525 clks 16+6*21+20+20+6*21+20+20+6*21+20+3 = 497 clks DM: 8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK46L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB2,LSB SADD46LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK46LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPS2416C AARGB2,LSB SOK46L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
SOK46L16
SOK46LC
PM: 14+31+27+31+27+31+8 = 169 CLRF RLF TEMP AARGB0,W
DS00617B-page 195
AN617
RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF RLF MOVLW MOVWF LOOPU2416A RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD46LA ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS REMB1, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
_C 1 TEMP, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB0,LSB UADD46LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK46LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB0, F LOOPCOUNT, F LOOPU2416A AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB0,LSB UADD46L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C
UOK46LA
DS00617B-page 196
AN617
MOVLW SUBWF GOTO UADD46L8 ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU2416B RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD46LB ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF 1 TEMP, F UOK46L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB1,LSB UADD46LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK46LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB1, F LOOPCOUNT, F LOOPU2416B AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB1,LSB UADD46L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK46L8
UOK46LB
DS00617B-page 197
AN617
CLRW BTFSS MOVLW SUBWF GOTO UADD46L16 ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF MOVLW MOVWF LOOPU2416C RLF RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF CLRW BTFSS MOVLW SUBWF GOTO UADD46LC ADDWF MOVF BTFSC INCFSZ ADDWF CLRW BTFSC MOVLW ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK46L _C 1 TEMP, F UOK46L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,W AARGB2,LSB UADD46LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F UOK46LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C 1 TEMP, F AARGB2, F LOOPCOUNT, F LOOPU2416C AARGB2,LSB UOK46L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK46L16
UOK46LC
DS00617B-page 198
AN617
endm UDIV2315L ; ; ; macro 9+6*17+16+16+6*17+16+16+6*17+16+8 = 403 clks 9+6*16+15+15+6*16+15+15+6*16+15+3 = 375 clks DM: 7 BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD35LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK35LA REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPU2315A AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD35L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK35L8 REMB1, F BARGB0,W _C BARGB0,W REMB0, F
PM: 7+2*40+22+8 = 117 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF MOVLW MOVWF
LOOPU2315A
RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO
UADD35LA
ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO
UOK35LA
UADD35L8
ADDWF MOVF BTFSC INCFSZ ADDWF
DS00617B-page 199
AN617
UOK35L8 RLF MOVLW MOVWF LOOPU2315B RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD35LB ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD35L16 ADDWF MOVF BTFSC INCFSZ ADDWF RLF MOVLW MOVWF LOOPU2315C RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ AARGB1, F 7 LOOPCOUNT AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD35LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK35LB REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F LOOPCOUNT, F LOOPU2315B AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD35L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK35L16 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F 7 LOOPCOUNT AARGB2,W REMB1, F REMB0, F BARGB1,W AARGB2,LSB UADD35LC REMB1, F BARGB0,W _C BARGB0,W
UOK35LB
UOK35L16
DS00617B-page 200
AN617
SUBWF GOTO UADD35LC ADDWF MOVF BTFSC INCFSZ ADDWF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK35L endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FXD2416S 24/16 Bit Signed Fixed Point Divide 24/16 -> 24.16 Input: 24 bit fixed point dividend in AARGB0, AARGB1,AARGB2 16 bit fixed point divisor in BARGB0, BARGB1 CALL FXD2416S REMB0, F UOK35LC REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB2, F LOOPCOUNT, F LOOPU2315C AARGB2,LSB UOK35L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
UOK35LC
Use:
Output: 24 bit fixed point quotient in AARGB0, AARGB1,AARGB2 16 bit fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: <-AARG / BARG = = = = 433 clks 451 clks 454 clks 444 clks 9 clks 405 423 426 416 clks clks clks clks A A A A A A A A A > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
25+403+5 29+403+19 32+403+19 36+403+5
Min Timing:
25+375+5 29+375+19 32+375+19 36+375+5
= = = =
B B B B
> < > <
0 0 0 0
PM: 36+117+18+48 = 219 CLRF CLRF CLRF MOVF IORWF IORWF BTFSC RETLW MOVF XORWF MOVWF SIGN REMB0 REMB1 AARGB0,W AARGB1,W AARGB2,W _Z 0x00 AARGB0,W BARGB0,W TEMP
DM: 10
DS00617B-page 201
AN617
BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF BTFSC INCF CA2416S BTFSS GOTO COMF COMF COMF INCF BTFSC INCF BTFSC INCF C2416SX MOVF IORWF MOVWF BTFSC GOTO SDIV2416L BTFSC GOTO C2416SOK BTFSS RETLW COMF COMF COMF INCF BTFSC INCF BTFSC INCF COMF COMF INCF BTFSC INCF RETLW TEMPB3,LSB C2416SX4 SIGN,MSB 0x00 AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, _Z AARGB0, REMB1, REMB0, REMB1, _Z REMB0, 0x00 F F F F F F F F F F ; test exception flag TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA2416S BARGB1, BARGB0, BARGB1, _Z BARGB0, F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG
AARGB0,MSB C2416SX AARGB2, AARGB1, AARGB0, AARGB2, _Z AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C2416SX1 F F F F F F
C2416S
C2416SX1
BTFSS GOTO BTFSC GOTO MOVF MOVWF MOVF MOVWF
BARGB0,MSB C2416SX3 AARGB0,MSB C2416SX2 AARGB1,W REMB0 AARGB2,W REMB1
; test BARG exception ; test AARG exception
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BCF RLF RLF MOVF MOVWF CLRF CLRF GOTO CLRF INCF CLRF CLRF RETLW COMF COMF COMF INCF GOTO INCF BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO CLRF CLRF INCF BTFSC INCF BTFSC INCF BTFSS GOTO BSF RETLW REMB0,MSB AARGB1,F AARGB0,F AARGB0,W AARGB2 AARGB0 AARGB1 C2416SOK AARGB2 AARGB2,F AARGB1 AARGB0 0x00 AARGB0,F AARGB1,F AARGB2,F TEMPB3,F C2416S REMB1,F _Z REMB0,F BARGB1,W REMB1,W _Z C2416SOK BARGB0,W REMB0,W _Z C2416SOK REMB0 REMB1 AARGB2,F _Z AARGB1,F _Z AARGB0,F AARGB0,MSB C2416SOK FPFLAGS,NAN 0xFF
C2416SX2
C2416SX3
C2416SX4
; overflow
; overflow
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD2416U 24/16 Bit Unsigned Fixed Point Divide 24/16 -> 24.16 Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2 16 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD2416U
Use:
Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2 16 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: Max Timing: <-AARG / BARG
2+525+2 = 529 clks 2+497+2 = 501 clks DM: 8 REMB0
PM: 2+169+1 = 172 CLRF
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CLRF UDIV2416L RETLW 0x00 REMB1
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD2315U 23/15 Bit Unsigned Fixed Point Divide 23/15 -> 23.15 Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2 15 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD2315U
Use:
Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2 15 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: Min Timing: <-AARG / BARG
;********************************************************************************************** ;********************************************************************************************** END
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E.6
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

;********************************************************************************************** ;********************************************************************************************** ; 16/16 Bit Division Macros macro 13+14*18+17+8 = 290 clks 13+14*16+15+3 = 255 clks DM: 7 RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF MOVLW MOVWF LOOPS1616 RLF RLF RLF MOVF BTFSS GOTO AARGB0,W REMB1, F REMB0, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F AARGB0, F D15 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD66L
SDIV1616L ; ; ;
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SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD66L ADDWF MOVF BTFSC INCFSZ ADDWF RLF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF SOK66L endm UDIV1616L ; ; ; ; macro nonrestore = 17 clks REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK66LL REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F AARGB0, F LOOPCOUNT, F LOOPS1616 AARGB1,LSB SOK66L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
SOK66LL
restore = 23 clks, Max Timing: Min Timing: PM: 24 MOVLW MOVWF
2+15*23+22 = 369 clks 2+15*17+16 = 273 clks DM: 7 D16 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C UOK66LL BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C AARGB1, F
LOOPU1616
RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF BCF
UOK66LL
RLF
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RLF DECFSZ GOTO endm UDIV1515L ; ; ; macro 13+14*18+17+8 = 290 clks 13+14*17+16+3 = 270 clks DM: 7 RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF MOVLW MOVWF LOOPU1515 RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD55L ADDWF MOVF BTFSC INCFSZ ADDWF RLF RLF DECFSZ GOTO BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK55L AARGB0,W REMB1, F REMB0, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F AARGB0, F D15 LOOPCOUNT AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD55L REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK55LL REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F AARGB0, F LOOPCOUNT, F LOOPU1515 AARGB1,LSB UOK55L BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F LOOPCOUNT, F LOOPU1616
UOK55LL
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endm SDIV1616 ; ; ; macro Max Timing: Min Timing: 7+10+6*14+14+7*14+8 = 221 clks 7+10+6*13+13+7*13+3 = 202 clks DM: 6
PM: 7+10+6*18+18+7*18+8 = 277 variable i MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF RLF RLF MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RLF variable i = 2 while i < 8 RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO AARGB0,W REMB1, F REMB0, F BARGB1,W
BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F
AARGB0,LSB SADD66#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK66#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F
SADD66#v(i)
ADDWF MOVF BTFSC INCFSZ ADDWF RLF
SOK66#v(i)
variable i = i + 1 endw RLF RLF RLF AARGB1,W REMB1, F REMB0, F
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MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD668 ADDWF MOVF BTFSC INCFSZ ADDWF RLF variable i = 9 while i < 16 RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO SADD66#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF RLF AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB1,LSB SADD66#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK66#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F BARGB1,W AARGB0,LSB SADD668 REMB1, F BARGB0,W _C BARGB0,W REMB0, F SOK668 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F
SOK668
SOK66#v(i)
variable i = i + 1 endw BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF SOK66 endm UDIV1616 ; macro restore = 20 clks, nonrestore = 14 clks AARGB1,LSB SOK66 BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
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; ; ; Max Timing: 16*20 = 320 clks Min Timing: 16*14 = 224 clks PM: 16*20 = 320 variable variable i = 0 while i < 16 RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF BCF UOK66#v(i) RLF RLF AARGB0,W REMB1, F REMB0, F BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C UOK66#v(i) BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F _C AARGB1, F AARGB0, F DM: 6 i
variable i = i + 1 endw endm UDIV1515 ; ; ; macro Max Timing: Min Timing: PM: 7+10+6*14+14+7*14+8 = 221 clks 7+10+6*13+13+7*13+3 = 202 clks DM: 6
7+10+6*18+18+7*18+8 = 277 variable i MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF RLF RLF MOVF BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,W
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ADDWF MOVF BTFSC INCFSZ ADDWF RLF variable i = 2 while i < 8 RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD55#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF RLF AARGB0,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD55#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK55#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0, F REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB0
UOK55#v(i)
variable i = i + 1 endw RLF RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD558 ADDWF MOVF BTFSC INCFSZ ADDWF RLF variable i = 9 while i < 16 RLF AARGB1,W AARGB1,W REMB1, F REMB0, F BARGB1,W AARGB0,LSB UADD558 REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK558 REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F
UOK558
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RLF RLF MOVF BTFSS GOTO SUBWF MOVF BTFSS INCFSZ SUBWF GOTO UADD55#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF RLF REMB1, F REMB0, F BARGB1,W AARGB1,LSB UADD55#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F UOK55#v(i) REMB1, F BARGB0,W _C BARGB0,W REMB0, F AARGB1, F
UOK55#v(i)
variable i = i + 1 endw BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF UOK55 endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 16/16 Bit Signed Fixed Point Divide 16/16 -> 16.16 Input: 16 bit fixed point dividend in AARGB0, AARGB1 16 bit fixed point divisor in BARGB0, BARGB1 CALL FXD1616S AARGB1,LSB UOK55 BARGB1,W REMB1, F BARGB0,W _C BARGB0,W REMB0, F
Use:
Output: 16 bit fixed point quotient in AARGB0, AARGB1 16 bit fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: <-AARG / BARG = = = = 319 clks 334 clks 334 clks 327 clks 8 clks 284 299 299 292 clks clks clks clks DM: 10 A A A A A A A A A > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
24+290+5 28+290+16 28+290+16 32+290+5
Min Timing:
24+255+5 28+255+16 28+255+16 32+255+5
= = = =
B B B B
> < > <
0 0 0 0
PM: 32+42+15+39 = 128
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FXD1616S CLRF CLRF CLRF MOVF IORWF BTFSC RETLW MOVF XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF BTFSC INCF CA1616S BTFSS GOTO COMF COMF INCF BTFSC INCF C1616SX MOVF IORWF MOVWF BTFSC GOTO SDIV1616L BTFSC GOTO C1616SOK BTFSS RETLW COMF COMF INCF BTFSC INCF COMF COMF INCF BTFSC INCF RETLW C1616SX1 BTFSS GOTO BTFSC GOTO TEMPB3,LSB C1616SX4 SIGN,MSB 0x00 AARGB1, AARGB0, AARGB1, _Z AARGB0, REMB1, REMB0, REMB1, _Z REMB0, 0x00 BARGB0,MSB C1616SX3 AARGB0,MSB C1616SX2 ; test BARG exception ; test AARG exception F F F F F F F F ; test exception flag SIGN REMB0 REMB1 AARGB0,W AARGB1,W _Z 0x00 AARGB0,W BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA1616S BARGB1, BARGB0, BARGB1, _Z BARGB0, F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG ; clear partial remainder
AARGB0,MSB C1616SX AARGB1, AARGB0, AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C1616SX1 F F F F
C1616S
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MOVF MOVWF MOVF MOVWF CLRF CLRF GOTO CLRF CLRF INCF RETLW COMF COMF INCF GOTO INCF BTFSC INCF MOVF SUBWF BTFSS GOTO MOVF SUBWF BTFSS GOTO CLRF CLRF INCF BTFSC INCF BTFSS GOTO BSF RETLW AARGB0,W REMB0 AARGB1,W REMB1 AARGB0 AARGB1 C1616SOK AARGB0 AARGB1 AARGB1,F 0x00 AARGB0,F AARGB1,F TEMPB3,F C1616S REMB1,F _Z REMB0,F BARGB1,W REMB1,W _Z C1616SOK BARGB0,W REMB0,W _Z C1616SOK REMB0 REMB1 AARGB1,F _Z AARGB0,F AARGB0,MSB C1616SOK FPFLAGS,NAN 0xFF ; quotient = 0, remainder = AARG
C1616SX2
C1616SX3
; numerator = 0x7FFF + 1
C1616SX4
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD1616U 16/16 Bit Unsigned Fixed Point Divide 16/16 -> 16.16 Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 16 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD1616U
Use:
Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 16 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: Min Timing: PM: 2+24+1 = 27 CLRF CLRF UDIV1616L RETLW 0x00 <-AARG / BARG
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;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD1515U 15/15 Bit Unsigned Fixed Point Divide 15/15 -> 15.15 Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1 15 bit unsigned fixed point divisor in BARGB0, BARGB1 CALL FXD1515U
Use:
Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1 15 bit unsigned fixed point remainder in REMB0, REMB1 Result: AARG, REM Max Timing: Min Timing: PM: 2+42+1 = 45 CLRF CLRF UDIV1515L RETLW 0x00 <-AARG / BARG
;********************************************************************************************** ;**********************************************************************************************
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E.7
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Output: quotient AARG/BARG followed by remainder in REM All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed divide application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine FXD1608S FXD1608U FXD1607U FXD1507U Clocks 203 294 174 166 Function 16 bit/8 bit -> 16.08 signed fixed point divide 16 bit/8 bit -> 16.08 unsigned fixed point divide 16 bit/7 bit -> 16.07 unsigned fixed point divide 15 bit/7 bit -> 15.07 unsigned fixed point divide
;********************************************************************************************** ;********************************************************************************************** ; 16/08 Bit Division Macros
SDIV1608L ; ; ;
macro 3+5+2+5*11+10+10+6*11+10+2 = 163 clks 3+5+2+5*11+10+10+6*11+10+2 = 163 clks DM: 5 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF MOVLW MOVWF BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 6 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB
LOOPS1608A
RLF RLF MOVF BTFSC SUBWF BTFSS
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ADDWF RLF DECFSZ GOTO RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF MOVLW MOVWF LOOPS1608B RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO BTFSS ADDWF endm UDIV1608L ; ; ; macro REMB0, F AARGB0, F LOOPCOUNT, F LOOPS1608A AARGB1,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F LOOPCOUNT, F LOOPS1608B AARGB1,LSB REMB0, F
Max Timing: 2+7*12+11+3+7*24+23 = 291 clks Min Timing: 2+7*11+10+3+7*17+16 = 227 clks PM: 39 MOVLW MOVWF 8 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W REMB0, F _C UOK68A REMB0, F _C AARGB0, F LOOPCOUNT, F LOOPU1608A TEMP 8 LOOPCOUNT DM: 7
LOOPU1608A
RLF RLF MOVF SUBWF BTFSC GOTO ADDWF BCF RLF DECFSZ GOTO CLRF MOVLW MOVWF
UOK68A
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LOOPU1608B RLF RLF RLF MOVF SUBWF CLRF CLRW BTFSS INCFSZ SUBWF BTFSC GOTO MOVF ADDWF CLRF CLRW BTFSC INCFSZ ADDWF BCF RLF DECFSZ GOTO endm UDIV1607L ; ; ; macro 7+6*11+10+10+6*11+10+2 = 171 clks 7+6*11+10+10+6*11+10+2 = 171 clks DM: 5 RLF RLF MOVF SUBWF RLF MOVLW MOVWF LOOPU1607A RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO RLF RLF MOVF BTFSC SUBWF AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F LOOPCOUNT, F LOOPU1607A AARGB1,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB1,W REMB0, F TEMP, F BARGB0,W REMB0, F AARGB5 _C AARGB5,W TEMP, F _C UOK68B BARGB0,W REMB0, F AARGB5 _C AARGB5,W TEMP, F _C AARGB1, F LOOPCOUNT, F LOOPU1608B
UOK68B
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BTFSS ADDWF RLF MOVLW MOVWF LOOPU1607B RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO BTFSS ADDWF endm UDIV1507L ; ; ; macro 3+5+2+5*11+10+10+6*11+10+2 = 163 clks 3+5+2+5*11+10+10+6*11+10+2 = 163 clks DM: 5 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF MOVLW MOVWF LOOPU1507A RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO RLF RLF MOVF BTFSC SUBWF BTFSS BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 6 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F LOOPCOUNT, F LOOPU1507A AARGB1,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB AARGB0,LSB REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F LOOPCOUNT, F LOOPU1607B AARGB1,LSB REMB0, F
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AN617
ADDWF RLF MOVLW MOVWF LOOPU1507B RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO BTFSS ADDWF endm SDIV1608 ; ; ; macro Max Timing: Min Timing: PM: 122 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF variable i = 2 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 3+5+14*8+2 = 122 clks 3+5+14*8+2 = 122 clks DM: 4 REMB0, F AARGB1, F 7 LOOPCOUNT AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F LOOPCOUNT, F LOOPU1507B AARGB1,LSB REMB0, F
variable i = i + 1 endw RLF RLF MOVF BTFSC SUBWF AARGB1,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F
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BTFSS ADDWF RLF variable i = 9 while i < 16 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F AARGB0,LSB REMB0, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm UDIV1608 ; ; ; ; macro restore = 9/21 clks, nonrestore = 8/14 clks AARGB1,LSB REMB0, F
Max Timing: 8*9+1+8*21 = 241 clks Min Timing: 8*8+1+8*14 = 177 clks PM: 241 variable i = 0 while i < 8 RLF RLF MOVF SUBWF BTFSC GOTO ADDWF BCF RLF AARGB0,W REMB0, F BARGB0,W REMB0, F _C UOK68#v(i) REMB0, F _C AARGB0, F DM: 6
UOK68#v(i)
variable i = i + 1 endw CLRF variable i = 8 while i < 16 RLF RLF RLF MOVF AARGB1,W REMB0, F TEMP, F BARGB0,W TEMP
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AN617
SUBWF CLRF CLRW BTFSS INCFSZ SUBWF BTFSC GOTO MOVF ADDWF CLRF CLRW BTFSC INCFSZ ADDWF BCF RLF REMB0, F AARGB5 _C AARGB5,W TEMP, F _C UOK68#v(i) BARGB0,W REMB0, F AARGB5 _C AARGB5,W TEMP, F _C AARGB1, F
UOK68#v(i)
variable i = i + 1 endw endm UDIV1607 ; ; ; macro Max Timing: Min Timing: PM: 127 RLF RLF MOVF SUBWF RLF variable i = 1 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 5+15*8+2 = 127 clks 5+15*8+2 = 127 clks DM: 4
variable i = i + 1 endw RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF AARGB1,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F
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RLF variable i = 9 while i < 16 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm UDIV1507 ; ; ; macro Max Timing: Min Timing: PM: 122 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF variable i = 2 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 3+5+14*8+2 = 122 clks 3+5+14*8+2 = 122 clks DM: 4 AARGB1,LSB REMB0, F
variable i = i + 1 endw RLF RLF MOVF BTFSC AARGB1,W REMB0, F BARGB0,W AARGB0,LSB
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SUBWF BTFSS ADDWF RLF variable i = 9 while i < 16 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF AARGB1,W REMB0, F BARGB0,W AARGB1,LSB REMB0, F AARGB1,LSB REMB0, F AARGB1, F REMB0, F AARGB0,LSB REMB0, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FXD1608S 16/8 Bit Signed Fixed Point Divide 16/8 -> 16.08 Input: 16 bit signed fixed point dividend in AARGB0, AARGB1 8 bit signed fixed point divisor in BARGB0 CALL FXD1608S AARGB1,LSB REMB0, F
Use:
Output: 16 bit signed fixed point quotient in AARGB0, AARGB1 8 bit signed fixed point remainder in REMB0 Result: AARG, REM Max Timing: <-AARG / BARG A A A A A A A A A DM: 8 SIGN REMB0 AARGB0,W AARGB1,W _Z 0x00 AARGB0,W BARGB0,W TEMP > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
23+163+5 = 191 clks 24+163+13 = 200 clks 27+163+13 = 203 clks 28+163+5 = 196 clks 7 clks 23+163+5 = 191 clks 24+163+13 = 200 clks 27+163+13 = 203 clks 28+163+5 = 196 clks
Min Timing:
B B B B
> < > <
0 0 0 0
PM: 28+42+12+34 = 116 CLRF CLRF MOVF IORWF BTFSC RETLW MOVF XORWF MOVWF
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BTFSC COMF CLRF BTFSS GOTO COMF INCF CA1608S BTFSS GOTO COMF COMF INCF BTFSC INCF C1608SX MOVF IORWF MOVWF BTFSC GOTO SDIV1608 BTFSC GOTO BTFSS RETLW COMF COMF INCF BTFSC INCF COMF INCF RETLW C1608SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF BCF RLF RLF MOVF MOVWF CLRF GOTO CLRF INCF CLRF RETLW COMF COMF INCF GOTO TEMPB3,LSB C1608SX4 SIGN,MSB 0x00 AARGB1, AARGB0, AARGB1, _Z AARGB0, REMB0, F REMB0, F 0x00 BARGB0,MSB C1608SX3 AARGB0,MSB C1608SX2 AARGB1,W REMB0 REMB0,MSB AARGB1,F AARGB0,F AARGB0,W AARGB1 AARGB0 C1608SOK AARGB1 AARGB1,F AARGB0 0x00 AARGB0,F AARGB1,F TEMPB3,F C1608S ; test BARG exception ; test AARG exception F F F F ; test exception flag TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA1608S BARGB0, F BARGB0, F AARGB0,MSB C1608SX AARGB1, AARGB0, AARGB1, _Z AARGB0, AARGB0,W BARGB0,W TEMP TEMP,MSB C1608SX1 F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG
C1608S
C1608SOK
C1608SX2
C1608SX3
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C1608SX4 INCF MOVF SUBWF BTFSS GOTO CLRF INCF BTFSC INCF BTFSS GOTO BSF RETLW REMB0,F BARGB0,W REMB0,W _Z C1608SOK REMB0 AARGB1,F _Z AARGB0,F AARGB0,MSB C1608SOK FPFLAGS,NAN 0xFF ; increment remainder and test for ; overflow
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD1608U 16/8 Bit Unsigned Fixed Point Divide 16/8 -> 16.08 Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 8 bit unsigned fixed point divisor in BARGB0 CALL FXD1608U
Use:
Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 8 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+39+1 = 41 CLRF UDIV1608L RETLW 0x00 <-AARG / BARG
1+291+2 = 294 clks 1+227+2 = 230 clks DM: 7 REMB0
Use:
Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 7 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+39+1 = 41 CLRF UDIV1607L <-AARG / BARG
1+171+2 = 174 clks 1+171+2 = 174 clks DM: 5 REMB0
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RETLW 0x00
Use:
Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1 7 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+42+1 = 44 CLRF UDIV1507L RETLW 0x00 <-AARG / BARG
1+163+2 = 166 clks 1+163+2 = 166 clks DM: 5 REMB0
;********************************************************************************************** ;********************************************************************************************** END
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E.8
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Output: quotient AARG/BARG in AARG followed by remainder in REM All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed divide application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine FXD0808S FXD0808U FXD0807U FXD0707U Clocks 109 100 88 80 Function 8 bit/8 bit -> 08.08 signed fixed point divide 8 bit/8 bit -> 08.08 unsigned fixed point divide 8 bit/7 bit -> 08.07 unsigned fixed point divide 7 bit/7 bit -> 07.07 unsigned fixed point divide
;********************************************************************************************** ;********************************************************************************************** ; 08/08 Bit Division Macros
SDIV0808L ; ; ;
macro 3+5+2+5*11+10+2 = 77 clks 3+5+2+5*11+10+2 = 77 clks DM: 4 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF MOVLW MOVWF BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 6 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB
LOOPS0808A
RLF RLF MOVF BTFSC SUBWF BTFSS
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ADDWF RLF DECFSZ GOTO BTFSS ADDWF endm UDIV0808L ; ; ; macro REMB0, F AARGB0, F LOOPCOUNT, F LOOPS0808A AARGB0,LSB REMB0, F
Max Timing: 2+7*12+11 = 97 clks Min Timing: 2+7*11+10 = 89 clks PM: 13 MOVLW MOVWF 8 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W REMB0, F _C UOK88A REMB0, F _C AARGB0, F LOOPCOUNT, F LOOPU0808A DM: 4
LOOPU0808A
RLF RLF MOVF SUBWF BTFSC GOTO ADDWF BCF RLF DECFSZ GOTO endm
UOK88A
UDIV0807L ; ; ;
macro 7+6*11+10+2 = 85 clks 7+6*11+10+2 = 85 clks DM: 4 RLF RLF MOVF SUBWF RLF MOVLW MOVWF AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 7 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F LOOPCOUNT, F
LOOPU0807
RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ
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GOTO BTFSS ADDWF endm UDIV0707L ; ; ; macro 3+5+2+5*11+10+2 = 77 clks 3+5+2+5*11+10+2 = 77 clks DM: 4 MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF MOVLW MOVWF LOOPU0707 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF DECFSZ GOTO BTFSS ADDWF endm SDIV0808 ; ; ; macro Max Timing: Min Timing: PM: 58 variable i MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 3+5+6*8+2 = 58 clks 3+5+6*8+2 = 58 clks DM: 3 BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 6 LOOPCOUNT AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F LOOPCOUNT, F LOOPU0707 AARGB0,LSB REMB0, F LOOPU0807 AARGB0,LSB REMB0, F
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i = 2 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF i= i + 1 endw BTFSS ADDWF endm UDIV0808 ; ; ; ; macro restore = 9 clks, nonrestore = 8 clks AARGB0,LSB REMB0, F AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F
Max Timing: 8*9 = 72 clks Min Timing: 8*8 = 64 clks PM: 72 variable i = 0 while i < 8 RLF RLF MOVF SUBWF BTFSC GOTO ADDWF BCF RLF i= i + 1 endw endm AARGB0,W REMB0, F BARGB0,W REMB0, F _C UOK88#v(i) REMB0, F _C AARGB0, F i DM: 3
UOK88#v(i)
UDIV0807 ; ; ;
macro Max Timing: Min Timing: PM: 63 variable i 5+7*8+2 = 63 clks 5+7*8+2 = 63 clks DM: 3
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RLF RLF MOVF SUBWF RLF i = 1 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF i= i + 1 endw BTFSS ADDWF endm UDIV0707 ; ; ; macro Max Timing: Min Timing: PM: 58 variable i MOVF SUBWF RLF RLF RLF MOVF ADDWF RLF i = 2 while i < 8 RLF RLF MOVF BTFSC SUBWF BTFSS ADDWF RLF i= i + 1 endw AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F BARGB0,W REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F 3+5+6*8+2 = 58 clks 3+5+6*8+2 = 58 clks DM: 3 AARGB0,LSB REMB0, F AARGB0,W REMB0, F BARGB0,W AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,W REMB0, F AARGB0, F
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BTFSS ADDWF endm ;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FXD0808S 8/8 Bit Signed Fixed Point Divide 8/8 -> 08.08 Input: 8 bit signed fixed point dividend in AARGB0 8 bit signed fixed point divisor in BARGB0 CALL FXD0808S AARGB0,LSB REMB0, F
Use:
Output: 8 bit signed fixed point quotient in AARGB0 8 bit signed fixed point remainder in REMB0 Result: AARG, REM Max Timing: <-AARG / BARG A A A A A A A A A DM: 7 SIGN REMB0 AARGB0,W _Z 0x00 BARGB0,W TEMP TEMP,MSB SIGN,F TEMPB3 BARGB0,MSB CA0808S BARGB0, F BARGB0, F AARGB0,MSB C0808SX AARGB0, F AARGB0, F AARGB0,W BARGB0,W TEMP TEMP,MSB C0808SX1 ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG > > < < = > > < < 0, 0, 0, 0, 0 0, 0, 0, 0, B B B B > < > < 0 0 0 0
21+77+5 = 103 clks 22+77+10 = 109 clks 22+77+10 = 109 clks 23+77+5 = 105 clks 6 clks 21+77+5 = 103 clks 22+77+10 = 109 clks 22+77+10 = 109 clks 23+77+5 = 105 clks
Min Timing:
B B B B
> < > <
0 0 0 0
PM: 23+22+9+25 = 79 CLRF CLRF MOVF BTFSC RETLW XORWF MOVWF BTFSC COMF CLRF BTFSS GOTO COMF INCF
CA0808S
BTFSS GOTO COMF INCF
C0808SX
MOVF IORWF MOVWF BTFSC GOTO SDIV0808L
C0808S
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BTFSC GOTO C0808SOK BTFSS RETLW COMF INCF COMF INCF RETLW C0808SX1 BTFSS GOTO BTFSC GOTO MOVF MOVWF CLRF GOTO CLRF INCF RETLW COMF INCF GOTO INCF MOVF SUBWF BTFSS GOTO CLRF INCF BTFSS GOTO BSF RETLW TEMPB3,LSB C0808SX4 SIGN,MSB 0x00 AARGB0, F AARGB0, F REMB0, F REMB0, F 0x00 BARGB0,MSB C0808SX3 AARGB0,MSB C0808SX2 AARGB0,W REMB0 AARGB0 C0808SOK AARGB0 AARGB0,F 0x00 AARGB0,F TEMPB3,F C0808S REMB0,F BARGB0,W REMB0,W _Z C0808SOK REMB0 AARGB0,F AARGB0,MSB C0808SOK FPFLAGS,NAN 0xFF ; test BARG exception ; test AARG exception ; quotient = 0, remainder = AARG ; test exception flag
C0808SX2
C0808SX3
; numerator = 0x7F + 1
C0808SX4
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; 8/8 Bit Unsigned Fixed Point Divide 8/8 -> 08.08 Input: 8 bit unsigned fixed point dividend in AARGB0 8 bit unsigned fixed point divisor in BARGB0 CALL FXD0808U
Use:
Output: 8 bit unsigned fixed point quotient in AARGB0 8 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+13+1 = 15 <-AARG / BARG
1+97+2 = 100 clks 1+89+2 = 92 clks DM: 4
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FXD0808U CLRF UDIV0808L RETLW 0x00 REMB0
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD0807U 8/7 Bit Unsigned Fixed Point Divide 8/7 -> 08.07 Input: 8 bit unsigned fixed point dividend in AARGB0 7 bit unsigned fixed point divisor in BARGB0 CALL FXD0807U
Use:
Output: 8 bit unsigned fixed point quotient in AARGB0 7 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+19+1 = 21 CLRF UDIV0807L RETLW 0x00 <-AARG / BARG
1+85+2 = 88 clks 1+85+2 = 88 clks DM: 4 REMB0
;********************************************************************************************** ;********************************************************************************************** ; ; ; ; ; ; ; ; ; ; FXD0707U 7/7 Bit Unsigned Fixed Point Divide 7/7 -> 07.07 Input: 7 bit unsigned fixed point dividend in AARGB0 7 bit unsigned fixed point divisor in BARGB0 CALL FXD0707U
Use:
Output: 7 bit unsigned fixed point quotient in AARGB0 7 bit unsigned fixed point remainder in REMB0 Result: AARG, REM Max Timing: Min Timing: PM: 1+22+1 = 44 CLRF UDIV0707L RETLW 0x00 <-AARG / BARG
1+77+2 = 80 clks 1+77+2 = 80 clks DM: 4 REMB0
;********************************************************************************************** ;**********************************************************************************************
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NOTES:
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APPENDIX F: PIC17CXXX MULTIPLY ROUTINES

; ; RCS Header $Id: fxm.a17 2.2 1996/06/11 21:42:11 F.J.Testa Exp $ $Revision: 2.2 $
; PIC17 FIXED POINT MULTIPLY ROUTINES ; ; Input: fixed point arguments in AARG and BARG ; ; Output: product AARG*BARG in AARG ; ; All timings are worst case cycle counts ; ; Routine Clocks Function ; ; ; FXM0808S 11 08x08 -> 16 bit signed fixed point multiply ; ; FXM0808U 6 08x08 -> 16 bit unsigned fixed point multiply ; ; FXM1608S 21 16x08 -> 24 bit signed fixed point multiply ; ; FXM1608U 12 16x08 -> 24 bit unsigned fixed point multiply ; ; FXM1616S 39 16x16 -> 32 bit signed fixed point multiply ; ; FXM1616U 26 16x16 -> 32 bit unsigned fixed point multiply ; ; FXM2416S 56 24x16 -> 40 bit signed fixed point multiply ; ; FXM2416U 40 24x16 -> 40 bit unsigned fixed point multiply ; ; FXM2424S 81 24x24 -> 48 bit signed fixed point multiply ; ; FXM2424U 65 24x24 -> 48 bit unsigned fixed point multiply ; ; FXM3216S 73 32x16 -> 48 bit signed fixed point multiply ; ; FXM3216U 54 32x16 -> 48 bit unsigned fixed point multiply ; ; FXM3224S 108 32x24 -> 56 bit signed fixed point multiply ; ; FXM3224U 90 32x24 -> 56 bit unsigned fixed point multiply ; ; FXM3232S 145 32x32 -> 64 bit signed fixed point multiply ; ; FXM3232U 125 32x32 -> 64 bit unsigned fixed point multiply ; ;********************************************************************************************** ;********************************************************************************************** ; ; 8x8 Bit Signed Fixed Point Multiply 08 x 08 -> 16 ; ; Input: 8 bit signed fixed point multiplicand in AARGB0 ; 8 bit signed fixed point multiplier in BARGB0 ; ; Use: CALL FXM0808S ; ; Output: 16 bit signed fixed point product in AARGB0, AARGB1 ; ; Result: AARG <-- AARG * BARG ;
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; Max Timing: ; ; Min Timing: ; ; PM: 10 ; FXM0808S MOVFP MULWF BTFSC SUBWF MOVFP BTFSC SUBWF MOVPF MOVPF RETLW 11 clks 11 clks DM: 3 AARGB0,WREG BARGB0 BARGB0,MSB PRODH,F BARGB0,WREG AARGB0,MSB PRODH,F PRODH,AARGB0 PRODL,AARGB1 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 8x8 Bit Unsigned Fixed Point Multiply 08 x 08 -> 16 ; ; Input: 8 bit unsigned fixed point multiplicand in AARGB0 ; 8 bit unsigned fixed point multiplier in BARGB0 ; ; Use: CALL FXM0808U ; ; Output: 16 bit unsigned fixed point product in AARGB0, AARGB1 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 6 clks ; ; Min Timing: 6 clks ; ; PM: 5 DM: 3 ; FXM0808U MOVFP BARGB0,WREG MULWF AARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,AARGB1 RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; ; 16x8 Bit Signed Fixed Point Multiply 16 x 08 -> 24 ; ; Input: 16 bit signed fixed point multiplicand in AARGB0 ; 8 bit signed fixed point multiplier in BARGB0 ; ; Use: CALL FXM1608S ; ; Output: 24 bit signed fixed point product in AARGB0, AARGB1 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 21 clks ; ; Min Timing: 18 clks ; ; PM: 20 DM: 4 ; FXM1608S MOVFP BARGB0,WREG MULWF AARGB1 MOVPF AARGB1,TEMP
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MOVPF MOVPF MULWF BTFSC SUBWF BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB SIGN1608OK CLRF MOVFP ADDWF MOVFP ADDWFC RETLW PRODH,AARGB1 PRODL,AARGB2 AARGB0 AARGB0,MSB PRODH,F BARGB0,MSB SIGN1608OK TEMP,WREG AARGB1,F AARGB0,WREG PRODH,F AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 16x8 Bit Unsigned Fixed Point Multiply 16 x 08 -> 24 ; ; Input: 16 bit unsigned fixed point multiplicand in AARGB0 ; 8 bit unsigned fixed point multiplier in BARGB0 ; ; Use: CALL FXM1608U ; ; Output: 24 bit unsigned fixed point product in AARGB0, AARGB1, AARGB2 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 12 clks ; ; Min Timing: 12 clks ; ; PM: 11 DM: 4 ; FXM1608U MOVFP BARGB0,WREG MULWF AARGB1 MOVPF PRODH,AARGB1 MOVPF PRODL,AARGB2 MULWF AARGB0 MOVPF PRODH,AARGB0 MOVPF PRODL,WREG ADDWF AARGB1,F CLRF WREG,F ADDWFC AARGB0,F RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 16x16 Bit Signed Fixed Point Multiply 16 x 16 -> 32 ; ; Input: 16 bit signed fixed point multiplicand in AARGB0, AARGB1 ; 16 bit signed fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM1616S ; ; Output: 32 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3 ;
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; Result: AARG <-- AARG * BARG ; ; Max Timing: 39 clks ; ; Min Timing: 31 clks ; ; PM: 38 DM: 8 ; FXM1616S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB TSIGN1616A BTFSS RETLW MOVFP SUBWF MOVFP SUBWFB RETLW AARGB1,WREG BARGB1 PRODH,AARGB2 PRODL,AARGB3 AARGB0,WREG BARGB0 PRODH,AARGB0 PRODL,AARGB1 BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F BARGB0,MSB TSIGN1616A TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00 BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 16x16 Bit Unsigned Fixed Point Multiply 16 x 16 -> 32 ; ; Input: 16 bit unsigned fixed point multiplicand in AARGB0, AARGB1 ; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM1616U ; ; Output: 32 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3
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; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 26 clks ; ; Min Timing: 26 clks ; ; PM: 25 DM: 7 ; ; FXM1616U MOVPF AARGB1,TEMPB1 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC RETLW AARGB1,WREG BARGB1 PRODH,AARGB2 PRODL,AARGB3 AARGB0,WREG BARGB0 PRODH,AARGB0 PRODL,AARGB1 BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 24x16 Bit Signed Fixed Point Multiply 24 x 16 -> 40 ; ; Input: 24 bit signed fixed point multiplicand in AARGB0, AARGB1, AARGB2 ; 16 bit signed fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM2416S ; ; Output: 40 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 56 clks ; ; Min Timing: 46 clks ; ; PM: 55 DM: 10 ; FXM2416S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2
DS00617B-page 241
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MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB TSIGN2416A BTFSS RETLW MOVFP SUBWF MOVFP SUBWFB RETLW AARGB2,WREG BARGB1 PRODH,AARGB3 PRODL,AARGB4 AARGB1,WREG BARGB0 PRODH,AARGB1 PRODL,AARGB2 BARGB1 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F BARGB0,MSB TSIGN2416A TEMPB2,WREG AARGB2,F TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00 BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 24x16 Bit Unsigned Fixed Point Multiply 24 x 16 -> 40 ; ; Input: 24 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2
DS00617B-page 242
AN617
; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM2416U ; ; Output: 40 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 40 clks ; ; Min Timing: 40 clks ; ; PM: 39 DM: 8 ; ; FXM2416U MOVPF AARGB2,TEMPB2 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC RETLW AARGB2,WREG BARGB1 PRODH,AARGB3 PRODL,AARGB4 AARGB1,WREG BARGB0 PRODH,AARGB1 PRODL,AARGB2 BARGB1 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 24x24 Bit Signed Fixed Point Multiply 24 x 24 -> 48
DS00617B-page 243
AN617
; ; Input: 24 bit signed fixed point multiplicand in AARGB0, AARGB1, AARGB2 ; 24 bit signed fixed point multiplier in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXM2424S ; ; Output: 48 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 81 clks ; ; Min Timing: 69 clks ; ; PM: 80 DM: 12 ; FXM2424S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF AARGB2,WREG BARGB2 PRODH,AARGB4 PRODL,AARGB5 AARGB1,WREG BARGB1 PRODH,AARGB2 PRODL,AARGB3 BARGB2 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB2,WREG BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB1 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG
DS00617B-page 244
AN617
ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB TSIGN2424A BTFSS RETLW MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RETLW AARGB3,F PRODH,WREG AARGB2,F AARGB0,W AARGB1,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TEMPB0,WREG BARGB0 PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F BARGB0,MSB TSIGN2424A TEMPB2,WREG AARGB2,F TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00 BARGB2,WREG AARGB2,F BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 24x24 Bit Unsigned Fixed Point Multiply 24 x 24 -> 48 ; ; Input: 24 bit unsigned fixed point multiplicand in AARGB0, AARGB1, AARGB2 ; 24 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXM2424U ; ; Output: 48 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 65 clks ; ; Min Timing: 65 clks ; ; PM: 64 DM: 12 ; ; FXM2424U MOVPF AARGB0,TEMPB0
DS00617B-page 245
AN617
MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF AARGB1,TEMPB1 AARGB2,TEMPB2 AARGB2,WREG BARGB2 PRODH,AARGB4 PRODL,AARGB5 AARGB1,WREG BARGB1 PRODH,AARGB2 PRODL,AARGB3 BARGB2 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB2,WREG BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB1 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,W AARGB1,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TEMPB0,WREG BARGB0
DS00617B-page 246
AN617
MOVPF ADDWF MOVPF ADDWFC RETLW PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32x16 Bit Signed Fixed Point Multiply 32 x 16 -> 48 ; ; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 16 bit signed fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM3216S ; ; Output: 48 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 73 clks ; ; Min Timing: 61 clks ; ; PM: 72 DM: 12 ; FXM3216S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF AARGB3,WREG BARGB1 PRODH,AARGB4 PRODL,AARGB5 AARGB2,WREG BARGB0 PRODH,AARGB2 PRODL,AARGB3 BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB3,WREG BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,WREG BARGB1 PRODL,WREG AARGB3,F PRODH,WREG
DS00617B-page 247
AN617
ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB TSIGN3216A BTFSS RETLW MOVFP SUBWF MOVFP SUBWFB RETLW AARGB2,F AARGB1,WREG BARGB0 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F BARGB0,MSB TSIGN3216A TEMPB3,WREG AARGB3,F TEMPB2,WREG AARGB2,F TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00 BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32x16 Bit Unsigned Fixed Point Multiply 32 x 16 -> 48 ; ; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 16 bit unsigned fixed point multiplier in BARGB0, BARGB1 ; ; Use: CALL FXM3216U ; ; Output: 48 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 54 clks ; ; Min Timing: 54 clks ; ; PM: 53 DM: 9
DS00617B-page 248
AN617
; ; FXM3216U MOVPF MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC RETLW AARGB3,TEMPB3 AARGB3,WREG BARGB1 PRODH,AARGB4 PRODL,AARGB5 AARGB2,WREG BARGB0 PRODH,AARGB2 PRODL,AARGB3 BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB3,WREG BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,WREG BARGB1 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB1,WREG BARGB0 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ;
DS00617B-page 249
AN617
; 32x24 Bit Signed Fixed Point Multiply 32 x 24 -> 56 ; ; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 24 bit signed fixed point multiplier in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXM3224S ; ; Output: 56 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 108 clks ; ; Min Timing: 94 clks ; ; PM: 107 DM: 15 ; FXM3224S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC AARGB3,WREG BARGB2 PRODH,AARGB5 PRODL,SIGN AARGB2,WREG BARGB1 PRODH,AARGB3 PRODL,AARGB4 BARGB2 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F WREG,F AARGB3,F TEMPB3,WREG BARGB1 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F WREG,F AARGB3,F AARGB1,WREG BARGB2 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F AARGB1,WREG BARGB1 AARGB2,W AARGB2,F PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F
DS00617B-page 250
AN617
MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB TSIGN3224A BTFSS RETLW TEMPB3,WREG BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F AARGB1,W AARGB2,F AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F TEMPB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,F SIGN,AARGB6 BARGB0,MSB TSIGN3224A TEMPB3,WREG AARGB3,F TEMPB2,WREG AARGB2,F TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00
DS00617B-page 251
AN617
MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RETLW BARGB2,WREG AARGB2,F BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32x24 Bit Unsigned Fixed Point Multiply 32 x 24 -> 56 ; ; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 24 bit unsigned fixed point multiplier in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXM3224U ; ; Output: 56 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 90 clks ; ; Min Timing: 90 clks ; ; PM: 89 DM: 15 ; ; FXM3224U MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF AARGB3,WREG BARGB2 PRODH,AARGB5 PRODL,SIGN AARGB2,WREG BARGB1 PRODH,AARGB3 PRODL,AARGB4 BARGB2 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F WREG,F AARGB3,F TEMPB3,WREG BARGB1 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F WREG,F AARGB3,F AARGB1,WREG BARGB2
DS00617B-page 252
AN617
MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F AARGB1,WREG BARGB1 AARGB2,W AARGB2,F PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F TEMPB3,WREG BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F AARGB1,W AARGB2,F AARGB1,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB1 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F AARGB0,WREG BARGB0 AARGB0,W AARGB0,F PRODL,WREG AARGB1,F PRODH,WREG AARGB0,F TEMPB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,F SIGN,AARGB6
DS00617B-page 253
AN617
RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; ; 32x32 Bit Signed Fixed Point Multiply 32 x 32 -> 64 ; ; Input: 32 bit signed fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 32 bit signed fixed point multiplier in BARGB0, BARGB1, ; BARGB2, BARGB3 ; ; Use: CALL FXM3232S ; ; Output: 64 bit signed fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 145 clks ; ; Min Timing: 129 clks ; ; PM: 144 DM: 18 ; FXM3232S MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF AARGB3,WREG BARGB3 PRODL,TBLPTRL PRODH,TBLPTRH AARGB2,WREG BARGB2 PRODL,AARGB5 PRODH,AARGB4 BARGB3 PRODL,WREG TBLPTRH,F PRODH,WREG AARGB5,F WREG,F AARGB4,F TEMPB3,WREG BARGB2 PRODL,WREG TBLPTRH,F PRODH,WREG AARGB5,F WREG,F AARGB4,F AARGB1,WREG BARGB3 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F AARGB1,WREG BARGB2 AARGB3,W
DS00617B-page 254
AN617
ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF MOVPF ADDWF CLRF ADDWFC MOVFP AARGB3,F PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F TEMPB3,WREG BARGB1 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F AARGB2,W AARGB3,F AARGB2,F TEMPB2,WREG BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB1,WREG BARGB1 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB1 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F TEMPB0,WREG BARGB3 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,F TEMPB0,WREG BARGB0 PRODH,AARGB0 PRODL,WREG AARGB1,F WREG,F AARGB0,F TEMPB3,WREG
DS00617B-page 255
AN617
MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MOVFP BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB TSIGN3232A BTFSS RETLW MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB RETLW BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,F AARGB0,F TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TBLPTRL,AARGB7 TBLPTRH,AARGB6 BARGB0,MSB TSIGN3232A TEMPB3,WREG AARGB3,F TEMPB2,WREG AARGB2,F TEMPB1,WREG AARGB1,F TEMPB0,WREG AARGB0,F TEMPB0,MSB 0x00 BARGB3,WREG AARGB3,F BARGB2,WREG AARGB2,F BARGB1,WREG AARGB1,F BARGB0,WREG AARGB0,F 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32x32 Bit Unsigned Fixed Point Multiply 32 x 32 -> 64 ; ; Input: 32 bit unsigned fixed point multiplicand in AARGB0, AARGB1, ; AARGB2, AARGB3 ; 32 bit unsigned fixed point multiplier in BARGB0, BARGB1, ; BARGB2, BARGB3
DS00617B-page 256
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; ; Use: CALL FXM3232U ; ; Output: 64 bit unsigned fixed point product in AARGB0, AARGB1, ; AARGB2, AARGB3, AARGB4, AARGB5, AARGB6, AARGB7 ; ; Result: AARG <-- AARG * BARG ; ; Max Timing: 125 clks ; ; Min Timing: 125 clks ; ; PM: 124 DM: 18 ; ; FXM3232U MOVPF AARGB0,TEMPB0 MOVPF AARGB1,TEMPB1 MOVPF AARGB2,TEMPB2 MOVPF AARGB3,TEMPB3 MOVFP MULWF MOVPF MOVPF MOVFP MULWF MOVPF MOVPF MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF AARGB3,WREG BARGB3 PRODL,TBLPTRL PRODH,TBLPTRH AARGB2,WREG BARGB2 PRODL,AARGB5 PRODH,AARGB4 BARGB3 PRODL,WREG TBLPTRH,F PRODH,WREG AARGB5,F WREG,F AARGB4,F TEMPB3,WREG BARGB2 PRODL,WREG TBLPTRH,F PRODH,WREG AARGB5,F WREG,F AARGB4,F AARGB1,WREG BARGB3 PRODL,WREG AARGB5,F PRODH,WREG AARGB4,F AARGB1,WREG BARGB2 AARGB3,W AARGB3,F PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F TEMPB3,WREG BARGB1 PRODL,WREG AARGB5,F
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MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF CLRF ADDWFC MOVPF ADDWF MOVPF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF MOVPF ADDWF CLRF ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC ADDWFC PRODH,WREG AARGB4,F AARGB2,W AARGB3,F AARGB2,F TEMPB2,WREG BARGB1 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F TEMPB1,WREG BARGB1 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB2 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F AARGB0,WREG BARGB1 AARGB1,W AARGB1,F PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F TEMPB0,WREG BARGB3 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,F TEMPB0,WREG BARGB0 PRODH,AARGB0 PRODL,WREG AARGB1,F WREG,F AARGB0,F TEMPB3,WREG BARGB0 PRODL,WREG AARGB4,F PRODH,WREG AARGB3,F WREG,F AARGB2,F AARGB1,F AARGB0,F
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MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC ADDWFC MOVFP MULWF MOVPF ADDWF MOVPF ADDWFC CLRF ADDWFC MOVFP MOVFP RETLW TEMPB2,WREG BARGB0 PRODL,WREG AARGB3,F PRODH,WREG AARGB2,F WREG,F AARGB1,F AARGB0,F TEMPB1,WREG BARGB0 PRODL,WREG AARGB2,F PRODH,WREG AARGB1,F WREG,F AARGB0,F TBLPTRL,AARGB7 TBLPTRH,AARGB6 0x00
;********************************************************************************************** ;**********************************************************************************************
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NOTES:
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APPENDIX G:PIC17CXXX DIVIDE ROUTINES

Table of Contents for Appendix G G.1 PIC17CXXX Fixed Point Divide Routines A.................................................................................................. 261 G.2 PIC17CXXX Fixed Point Divide Routines B.................................................................................................. 306 G.3 PIC17CXXX Fixed Point Divide Routines C ................................................................................................. 347
G.1
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
PIC17CXXX Fixed Point Divide Routines A

RCS Header $Id: fxda.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $ $Revision: 2.4 $ PIC17 FIXED POINT DIVIDE ROUTINES A Input: fixed point arguments in AARG and BARG
Output: quotient AARG/BARG followed by remainder in REM All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed divide application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine Clocks Function
FXD3232S FXD3232U FXD3231U FXD3131U
630 683 588 579
32 bit/32 bit -> 32.32 signed fixed point divide 32 bit/32 bit -> 32.32 unsigned fixed point divide 32 bit/31 bit -> 32.31 unsigned fixed point divide 31 bit/31 bit -> 31.31 unsigned fixed point divide
529 584 489 481
;********************************************************************************************** ;********************************************************************************************** ; ; 32/32 Bit Division Macros ; SDIV3232 macro ; ; Max Timing: 9+14+30*18+10 = 573 clks ; ; Min Timing: 9+14+30*17+3 = 536 clks ; ; PM: 9+14+30*24+10 = 753 DM: 12 ; variable i MOVFP BARGB3,WREG
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SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D2 while i < D8 RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO SADD22#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB0,LSB SADD22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
SOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB0,LSB
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GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO SADD228 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF SADD228 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK228 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
SOK228
SOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB1,LSB SADD2216 REMB3, F BARGB2,WREG REMB2, F
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MOVFP SUBWFB MOVFP SUBWFB GOTO SADD2216 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK2216 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
SOK2216
SOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB2,LSB SADD2224 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG
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SUBWFB GOTO SADD2224 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF REMB0, F SOK2224 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB3, F
SOK2224
SOK22#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC SOK22 endm AARGB3,LSB SOK22 BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV3232 macro ; ; restore = 25/30 clks,
nonrestore = 17/20 clks
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; ; ; ; ; ; ; Max Timing: 16*25+1+16*30 = 881 clks Min Timing: 16*17+1+16*20 = 593 clks PM: 16*25+1+16*30 = 881 variable variable i = D0 while i < D8 RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC BCF UOK22#v(i) RLCF AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK22#v(i) BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F i DM: 13
variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK22#v(i) BARGB3,WREG REMB3, F BARGB2,WREG
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ADDWFC MOVFP ADDWFC MOVFP ADDWFC BCF UOK22#v(i) RLCF REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB1, F
variable i = i + 1 endw CLRF TEMP, F
variable i = D16 while i < D24 RLCF RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC BCF UOK22#v(i) RLCF AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG TEMP, F _C UOK22#v(i) BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB2, F
variable i = i + 1 endw variable i = D24 while i < D32 RLCF RLCF RLCF RLCF RLCF RLCF MOVFP AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG
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SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC BCF UOK22#v(i) RLCF REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK22#v(i) BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB3, F
variable i = i + 1 endw endm NDIV3232 ; ; ; ; ; ; macro Max Timing: 16+31*21+10 = 677 clks
Min Timing: 16+31*20+3 = 639 clks PM: 16+31*29+10 = 925 variable i RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB RLCF AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F DM: 13
variable i = D1 while i < D8 RLCF RLCF RLCF RLCF AARGB0,W REMB3, F REMB2, F REMB1, F
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RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD22#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF REMB0, F TEMP, F BARGB3,WREG AARGB0,LSB NADD22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB0, F
NOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD228 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB0,LSB NADD228 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK228 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK228
variable i = D9
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while i < D16 RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD22#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB1,LSB NADD22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD2216 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB1,LSB NADD2216 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2216 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F
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ADDWFC NOK2216 RLCF TEMP, F AARGB2, F
variable i = D17 while i < D24 RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD22#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB2,LSB NADD22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB2, F
NOK22#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD2224 ADDWF MOVFP AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB2,LSB NADD2224 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2224 REMB3, F BARGB2,WREG
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ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC NOK2224 RLCF REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB3, F
variable i = D25 while i < D32 RLCF RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD22#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F TEMP, F BARGB3,WREG AARGB3,LSB NADD22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK22#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB3, F
NOK22#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC NOK22 endm AARGB3,LSB NOK22 BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV3231
macro
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; ; ; ; ; ; ; Max Timing: Min Timing: 14+31*18+10 = 582 clks 14+31*17+3 = 544 clks DM: 12
PM: 14+31*24+10 = 768 variable i RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB RLCF AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D1 while i < D8 RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO UADD21#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB0,LSB UADD21#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK21#v(i) REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK21#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB0,LSB
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GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO UADD218 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF UADD218 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK218 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK218
UOK21#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB AARGB2,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB1,LSB UADD2116 REMB3, F BARGB2,WREG REMB2, F
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MOVFP SUBWFB MOVFP SUBWFB GOTO UADD2116 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK2116 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK2116
UOK21#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB2,LSB UADD2124 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG
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SUBWFB GOTO UADD2124 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF REMB0, F UOK2124 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB3, F
UOK2124
UOK21#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC UOK21 endm AARGB3,LSB UOK21 BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV3131 macro ; ; Max Timing:
9+14+30*18+10 = 573 clks
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; ; ; ; ; Min Timing: 9+14+30*17+3 = 536 clks DM: 12
PM: 9+14+30*24+10 = 753 variable i MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF
BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK11#v(i)
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RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO UADD118 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB1,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG AARGB0,LSB UADD118 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK118 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK118
UOK11#v(i)
variable i = i + 1 endw RLCF RLCF RLCF AARGB2,W REMB3, F REMB2, F
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RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO UADD1116 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF REMB1, F REMB0, F BARGB3,WREG AARGB1,LSB UADD1116 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK1116 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK1116
UOK11#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP AARGB3,W REMB3, F REMB2, F REMB1, F REMB0, F BARGB3,WREG
DS00617B-page 279
AN617
BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB MOVFP SUBWFB GOTO UADD1124 ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB2,LSB UADD1124 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK1124 REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB3, F
UOK1124
UOK11#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC AARGB3,LSB UOK11 BARGB3,WREG REMB3, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
DS00617B-page 280
AN617
UOK11 endm
;********************************************************************************************** ;********************************************************************************************** ; ; 32/24 Bit Division Macros ; SDIV3224 macro ; ; Max Timing: 7+11+30*15+8 = 476 clks ; ; Min Timing: 7+11+30*14+3 = 441 clks ; ; PM: 7+11+30*19+8 = 596 DM: 10 ; variable i MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D2 while i < D8 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO SADD24#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB SADD24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
SOK24#v(i)
DS00617B-page 281
AN617
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO SADD248 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB SADD248 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK248 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
SOK248
SOK24#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB1,LSB SADD2416 REMB2, F BARGB1,WREG REMB1, F
DS00617B-page 282
AN617
MOVFP SUBWFB GOTO SADD2416 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB0,WREG REMB0, F SOK2416 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
SOK2416
SOK24#v(i)
SOK2424
variable i = D25
DS00617B-page 283
AN617
while i < D32 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO SADD24#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB3,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB3,LSB SADD24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB3, F
SOK24#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC SOK24 endm AARGB3,LSB SOK24 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV3224 macro ; ; restore = 20/25 clks, nonrestore = 14/17 clks ; ; Max Timing: 16*20+1+16*25 = 721 clks ; ; Min Timing: 16*14+1+16*17 = 497 clks ; ; PM: 16*20+1+16*25 = 721 DM: 11 ; variable i variable i = D0 while i < D8 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F
DS00617B-page 284
AN617
MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC BCF UOK24#v(i) RLCF BARGB0,WREG REMB0, F _C UOK24#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F
variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC BCF UOK24#v(i) RLCF AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK24#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB1, F
variable i = D16 while i < D24 RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F
DS00617B-page 285
AN617
SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC BCF UOK24#v(i) RLCF TEMP, F _C UOK24#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB2, F
variable i = i + 1 endw variable i = D24 while i < D32 RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC BCF UOK24#v(i) RLCF AARGB3,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK24#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB3, F
variable i = i + 1 endw endm NDIV3224 macro ; ; Max Timing: 13+31*18+8 = 579 clks ; ; Min Timing: 13+31*17+3 = 543 clks ; ; PM: 13+31*24+8 = 765 DM: 11 ; variable i
DS00617B-page 286
AN617
RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB RLCF AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
variable i = D1 while i < D8 RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD24#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB0,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB0,LSB NADD24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB0, F
NOK24#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO AARGB1,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB0,LSB NADD248 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK248
DS00617B-page 287
AN617
NADD248 ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK248
NOK24#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD2416 ADDWF MOVFP ADDWFC MOVFP AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB1,LSB NADD2416 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2416 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG
DS00617B-page 288
AN617
ADDWFC CLRF ADDWFC NOK2416 RLCF REMB0, F WREG, F TEMP, F AARGB2, F
NOK24#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD2424 ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC AARGB3,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB2,LSB NADD2424 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2424 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F
DS00617B-page 289
AN617
NOK2424 RLCF AARGB3, F variable i = D25 while i < D32 RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD24#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB3,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB3,LSB NADD24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK24#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB3, F
NOK24#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC NOK24 endm AARGB3,LSB NOK24 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV3223 macro ; ; Max Timing: 11+31*15+8 = 484 clks ; ; Min Timing: 11+31*14+3 = 448 clks ; ; PM: 11+31*19+8 = 608 ; variable i RLCF RLCF RLCF RLCF MOVFP SUBWF AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F
DM: 10
DS00617B-page 290
AN617
MOVFP SUBWFB MOVFP SUBWFB RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D1 while i < D8 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD23#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB UADD23#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK23#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK23#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD238 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB UADD238 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK238 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK238
variable i = D9 while i < D16 RLCF RLCF RLCF RLCF AARGB1,W REMB2, F REMB1, F REMB0, F
DS00617B-page 291
AN617
MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD23#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB2,WREG AARGB1,LSB UADD23#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK23#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK23#v(i)
UOK2316
variable i = D17 while i < D24 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD23#v(i) ADDWF MOVFP ADDWFC AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB2,LSB UADD23#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK23#v(i) REMB2, F BARGB1,WREG REMB1, F
DS00617B-page 292
AN617
MOVFP ADDWFC UOK23#v(i) RLCF BARGB0,WREG REMB0, F AARGB2, F
UOK2324
UOK23#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP AARGB3,LSB UOK23 BARGB2,WREG REMB2, F BARGB1,WREG
DS00617B-page 293
AN617
ADDWFC MOVFP ADDWFC UOK23 endm REMB1, F BARGB0,WREG REMB0, F
UDIV3123 macro ; ; Max Timing: 7+11+30*15+8 = 476 clks ; ; Min Timing: 7+11+30*14+3 = 441 clks ; ; PM: 7+11+30*19+8 = 596 DM: 10 ; variable i MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK13#v(i)
variable i = i + 1
DS00617B-page 294
AN617
endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD138 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB UADD138 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK138 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK138
UOK13#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB1,LSB UADD1316 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
DS00617B-page 295
AN617
GOTO UADD1316 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF UOK1316 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK1316
UOK13#v(i)
UOK1324
variable i = D25 while i < D32
DS00617B-page 296
AN617
RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD13#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB3,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB3,LSB UADD13#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK13#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB3, F
UOK13#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC UOK13 endm AARGB3,LSB UOK13 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
;********************************************************************************************** ;********************************************************************************************** ; ; 32/32 Bit Signed Fixed Point Divide 32/32 -> 32.32 ; ; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 ; ; Use: CALL FXD3232S ; ; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 ; 32 bit fixed point remainder in REMB0, REMB1, REMB2, REMB3 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 27+573+5 = 605 clks A > 0, B > 0 ; 34+573+23 = 630 clks A > 0, B < 0 ; 34+573+23 = 630 clks A < 0, B > 0 ; 41+573+5 = 619 clks A < 0, B < 0 ; 12 clks A = 0 ; ; Min Timing: 27+536+5 = 568 clks A > 0, B > 0 ; 34+536+23 = 593 clks A > 0, B < 0 ; 31+536+23 = 593 clks A < 0, B > 0 ; 41+536+5 = 582 clks A < 0, B < 0 ;
DS00617B-page 297
AN617
; PM: 41+753+22+54 = 870 ; FXD3232S CLRF CLRF CLRF CLRF CLRF MOVPF IORWF IORWF IORWF BTFSC RETLW MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF COMF INCF ADDWFC ADDWFC ADDWFC CA3232S BTFSS GOTO COMF COMF COMF COMF INCF ADDWFC ADDWFC ADDWFC C3232SX MOVPF IORWF BTFSC GOTO SDIV3232 BTFSC GOTO C3232SOK BTFSS RETLW COMF COMF COMF COMF CLRF INCF ADDWFC ADDWFC TEMPB3,LSB C3232SX4 SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, WREG, F AARGB3, AARGB2, AARGB1, F F F F F F F ; test exception flag DM: 14 SIGN,F REMB0,F REMB1,F REMB2,F REMB3,F AARGB0,WREG AARGB1,W AARGB2,W AARGB3,W _Z 0x00 AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA3232S BARGB3, BARGB2, BARGB1, BARGB0, BARGB3, BARGB2, BARGB1, BARGB0, F F F F F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG
AARGB0,MSB C3232SX AARGB3, AARGB2, AARGB1, AARGB0, AARGB3, AARGB2, AARGB1, AARGB0, F F F F F F F F
AARGB0,WREG BARGB0,W WREG,MSB C3232SX1
C3232S
DS00617B-page 298
AN617
ADDWFC COMF COMF COMF COMF INCF ADDWFC ADDWFC ADDWFC RETLW C3232SX1 BTFSS GOTO BTFSC GOTO MOVPF MOVPF MOVPF MOVPF CLRF CLRF CLRF CLRF GOTO CLRF CLRF CLRF CLRF INCF RETLW COMF COMF COMF COMF INCF GOTO INCF CLRF ADDWFC ADDWFC ADDWFC MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO CLRF CLRF CLRF CLRF INCF ADDWFC ADDWFC ADDWFC BTFSS AARGB0, F REMB3, REMB2, REMB1, REMB0, REMB3, REMB2, REMB1, REMB0, 0x00 BARGB0,MSB C3232SX3 AARGB0,MSB C3232SX2 AARGB0,REMB0 AARGB1,REMB1 AARGB2,REMB2 AARGB3,REMB3 AARGB0,F AARGB1,F AARGB2,F AARGB3,F C3232SOK AARGB0,F AARGB1,F AARGB2,F AARGB3,F AARGB3,F 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3232S REMB3,F WREG,F REMB2,F REMB1,F REMB0,F BARGB3,WREG REMB3 C3232SOK BARGB2,WREG REMB2 C3232SOK BARGB1,WREG REMB1 C3232SOK BARGB0,WREG REMB0 C3232SOK REMB0,F REMB1,F REMB2,F REMB3,W AARGB3,F AARGB2,F AARGB1,F AARGB0,F AARGB0,MSB ; test BARG exception ; test AARG exception ; quotient = 0, remainder = AARG F F F F F F F F
C3232SX2
C3232SX3
C3232SX4
DS00617B-page 299
AN617
GOTO BSF RETLW C3232SOK FPFLAGS,NAN 0xFF
;********************************************************************************************** ;********************************************************************************************** ; ; 32/32 Bit Unsigned Fixed Point Divide 32/32 -> 32.32 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 32 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 ; ; Use: CALL FXD3232U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1AARGB2,AARGB3 ; 32 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 4+677+2 = 683 clks ; ; Min Timing: 4+639+2 = 645 clks ; ; PM: 4+925+1 = 930 DM: 13 ; FXD3232U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F NDIV3232 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32/31 Bit Unsigned Fixed Point Divide 32/31 -> 32.31 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 ; ; Use: CALL FXD3231U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 ; 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 4+582+2 = 588 clks ; ; Min Timing: 4+544+2 = 550 clks ; ; PM: 4+768+1 = 773 DM: 12 ; FXD3231U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F UDIV3231 RETLW 0x00
DS00617B-page 300
AN617
;********************************************************************************************** ;********************************************************************************************** ; ; 31/31 Bit Unsigned Fixed Point Divide 31/31 -> 31.31 ; ; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 31 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2, BARGB3 ; ; Use: CALL FXD3131U ; ; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 ; 31 bit unsigned fixed point remainder in REMB0, REMB1, REMB2, REMB3 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 4+573+2 = 579 clks ; ; Min Timing: 4+536+2 = 542 clks ; ; PM: 4+753+1 = 758 DM: 12 ; FXD3131U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F CLRF REMB3, F UDIV3131 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32/24 Bit Signed Fixed Point Divide 32/24 -> 32.24 ; ; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD3224S ; ; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 ; 24 bit fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 25+476+5 = 506 clks A > 0, B > 0 ; 30+476+21 = 527 clks A > 0, B < 0 ; 32+476+21 = 529 clks A < 0, B > 0 ; 37+476+5 = 518 clks A < 0, B < 0 ; 11 clks A = 0 ; ; Min Timing: 25+441+3 = 469 clks A > 0, B > 0 ; 30+441+19 = 490 clks A > 0, B < 0 ; 32+441+19 = 492 clks A < 0, B > 0 ; 37+441+3 = 481 clks A < 0, B < 0 ; ; PM: 37+596+20+51 = 704 DM: 12 ; FXD3224S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F CLRF REMB2,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W
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IORWF BTFSC RETLW MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF INCF ADDWFC ADDWFC CA3224S BTFSS GOTO COMF COMF COMF COMF INCF ADDWFC ADDWFC ADDWFC C3224SX MOVPF IORWF BTFSC GOTO SDIV3224 BTFSC GOTO C3224SOK BTFSS RETLW COMF COMF COMF COMF CLRF INCF ADDWFC ADDWFC ADDWFC COMF COMF COMF INCF ADDWFC ADDWFC RETLW TEMPB3,LSB C3224SX4 SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, WREG, F AARGB3, AARGB2, AARGB1, AARGB0, REMB2, REMB1, REMB0, REMB2, REMB1, REMB0, 0x00 F F F F F F F F F F F F F F ; test exception flag AARGB3,W _Z 0x00 AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA3224S BARGB2, BARGB1, BARGB0, BARGB2, BARGB1, BARGB0, F F F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG
C3224S
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C3224SX1 BTFSS GOTO BTFSC GOTO MOVPF MOVPF MOVPF BCF RLCF RLCF MOVFP CLRF CLRF CLRF GOTO CLRF INCF CLRF CLRF CLRF RETLW COMF COMF COMF COMF INCF GOTO INCF CLRF ADDWFC ADDWFC MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO CLRF CLRF CLRF INCF ADDWFC ADDWFC ADDWFC BTFSS GOTO BSF RETLW BARGB0,MSB C3224SX3 AARGB0,MSB C3224SX2 AARGB1,REMB0 AARGB2,REMB1 AARGB3,REMB2 REMB0,MSB AARGB1,F AARGB0,F AARGB0,AARGB3 AARGB0,F AARGB1,F AARGB2,F C3224SOK AARGB3,F AARGB3,F AARGB2,F AARGB1,F AARGB0,F 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3224S REMB2,F WREG,F REMB1,F REMB0,F BARGB2,WREG REMB2 C3224SOK BARGB1,WREG REMB1 C3224SOK BARGB0,WREG REMB0 C3224SOK REMB0,F REMB1,F REMB2,W AARGB3,F AARGB2,F AARGB1,F AARGB0,F AARGB0,MSB C3224SOK FPFLAGS,NAN 0xFF ; test BARG exception ; test AARG exception
C3224SX2
C3224SX3
C3224SX4
; overflow
; if remainder overflow, clear
; remainder, increment quotient and ; test for overflow exception
;********************************************************************************************** ;********************************************************************************************** ; ; 32/24 Bit Unsigned Fixed Point Divide 32/24 -> 32.24 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2, AARGB3 ; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD3224U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2, AARGB3
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; 24 bit unsigned ; ; Result: AARG, REM <-; ; Max Timing: 3+579+2 ; ; Min Timing: 3+543+2 ; ; PM: 3+765+1 = 769 ; FXD3224U CLRF CLRF CLRF NDIV3224 RETLW 0x00 fixed point remainder in REMB0, REMB1, REMB2 AARG / BARG = 584 clks = 548 clks DM: 11 REMB0, F REMB1, F REMB2, F
;********************************************************************************************** ;********************************************************************************************** ; ; 32/23 Bit Unsigned Fixed Point Divide 32/23 -> 32.23 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2, AARGB3 ; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD3223U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2, AARGB3 ; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 3+484+2 = 489 clks ; ; Min Timing: 3+448+2 = 453 clks ; ; PM: 3+608+1 = 612 DM: 10 ; FXD3223U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F UDIV3223 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 31/23 Bit Unsigned Fixed Point Divide 31/23 -> 31.23 ; ; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2, AARGB3 ; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD3123U ; ; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1,AARGB2, AARGB3 ; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 3+476+2 = 481 clks ; ; Min Timing: 3+441+2 = 446 clks
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; ; PM: 3+596+1 = 600 ; FXD3123U CLRF CLRF CLRF UDIV3123 RETLW 0x00 DM: 10 REMB0, F REMB1, F REMB2, F
;********************************************************************************************** ;**********************************************************************************************
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G.2
; ;
PIC17CXXX Fixed Point Divide Routines B

RCS Header $Id: fxdb.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $ $Revision: 2.4 $
; PIC17 FIXED POINT DIVIDE ROUTINES B ; ; Input: fixed point arguments in AARG and BARG ; ; Output: quotient AARG/BARG followed by remainder in REM ; ; All timings are worst case cycle counts ; ; It is useful to note that the additional unsigned routines requiring a non-power of two ; argument can be called in a signed divide application where it is known that the ; respective argument is nonnegative, thereby offering some improvement in ; performance. ; ; Routine Clocks Function ; ; FXD2416S 328 24 bit/16 bit -> 24.16 signed fixed point divide ; ; FXD2416U 365 24 bit/16 bit -> 24.16 unsigned fixed point divide ; ; FXD2415U 294 24 bit/15 bit -> 24.15 unsigned fixed point divide ; ; FXD2315U 287 23 bit/15 bit -> 23.15 unsigned fixed point divide ; ; ; FXD1616S 227 16 bit/16 bit -> 16.16 signed fixed point divide ; ; FXD1616U 244 16 bit/16 bit -> 16.16 unsigned fixed point divide ; ; FXD1615U 197 16 bit/15 bit -> 16.15 unsigned fixed point divide ; ; FXD1515U 191 15 bit/15 bit -> 15.15 unsigned fixed point divide ; ; ; FXD1608S 159 16 bit/08 bit -> 16.08 signed fixed point divide ; ; FXD1608U 196 16 bit/08 bit -> 16.08 unsigned fixed point divide ; ; FXD1607U 130 16 bit/07 bit -> 16.07 unsigned fixed point divide ; ; FXD1507U 125 15 bit/07 bit -> 15.07 unsigned fixed point divide ; ; ; FXD0808S 88 08 bit/08 bit -> 08.08 signed fixed point divide ; ; FXD0808U 75 08 bit/08 bit -> 08.08 unsigned fixed point divide ; ; FXD0807U 66 08 bit/07 bit -> 08.07 unsigned fixed point divide ; ; FXD0707U 61 07 bit/07 bit -> 07.07 unsigned fixed point divide ; ;********************************************************************************************** ;********************************************************************************************** ; ; 24/16 Bit Division Macros ; SDIV2416 macro ; ; Max Timing: 5+8+22*12+6 = 283 clks ; ; Min Timing: 5+8+22*11+3 = 258 clks
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; ; ; PM: 5+8+22*14+6 = 327 variable i MOVFP SUBWF MOVFP SUBWFB RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F DM: 8
variable i = D2 while i < D8 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO SADD46#v(i) ADDWF MOVFP ADDWFC RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB SADD46#v(i) REMB1, F BARGB0,WREG REMB0, F SOK46#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB0, F
SOK46#v(i)
variable i = i + 1 endw RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO SADD468 ADDWF MOVFP ADDWFC RLCF AARGB1,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB SADD468 REMB1, F BARGB0,WREG REMB0, F SOK468 REMB1, F BARGB0,WREG REMB0, F AARGB1, F
SOK468
variable i = D9 while i < D16
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RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO SADD46#v(i) ADDWF MOVFP ADDWFC RLCF AARGB1,W REMB1, F REMB0, F BARGB1,WREG AARGB1,LSB SADD46#v(i) REMB1, F BARGB0,WREG REMB0, F SOK46#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB1, F
SOK46#v(i)
SOK4616
SOK46#v(i)
variable i = i + 1 endw BTFSC GOTO AARGB2,LSB SOK46
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MOVFP ADDWF MOVFP ADDWFC SOK46 endm BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV2416 macro ; ; restore = 15/20 clks, nonrestore = 11/14 clks ; ; Max Timing: 16*15+1+8*20 = 401 clks ; ; Min Timing: 16*11+1+8*14 = 289 clks ; ; PM: 16*15+1+8*20 = 401 DM: 8 ; variable i variable i = D0 while i < D8 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC BCF UOK46#v(i) RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK46#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F
variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC BCF UOK46#v(i) RLCF AARGB1,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK46#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB1, F
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variable i = D16 while i < D24 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC CLRF ADDWFC BCF UOK46#v(i) RLCF AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK46#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB2, F
endm NDIV2416 macro ; ; Max Timing: 10+23*15+6 = 361 clks ; ; Min Timing: 10+23*14+3 = 335 clks ; ; PM: 10+23*19+6 = 450 DM: 8 ; variable i RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
variable i = D1 while i < D8 RLCF AARGB0,W
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RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD46#v(i) ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB0,LSB NADD46#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK46#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB0, F
NOK46#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD468 ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB0,LSB NADD468 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK468 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK468
variable i = D9 while i < D16 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD46#v(i) ADDWF AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB1,LSB NADD46#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK46#v(i) REMB1, F
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MOVFP ADDWFC CLRF ADDWFC NOK46#v(i) RLCF BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK4616
variable i = D17 while i < D24 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD46#v(i) ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB2,LSB NADD46#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK46#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB2, F
NOK46#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP AARGB2,LSB NOK46 BARGB1,WREG
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ADDWF MOVFP ADDWFC NOK46 endm REMB1, F BARGB0,WREG REMB0, F
UDIV2415 macro ; ; Max Timing: 8+23*12+6 = 290 clks ; ; Min Timing: 8+23*11+3 = 264 clks ; ; PM: 8+23*14+6 = 336 ; variable i RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
DM: 8
variable i = D1 while i < D8 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD45#v(i) ADDWF MOVFP ADDWFC RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB UADD45#v(i) REMB1, F BARGB0,WREG REMB0, F UOK45#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK45#v(i)
variable i = i + 1 endw RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD458 ADDWF MOVFP ADDWFC AARGB1,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB UADD458 REMB1, F BARGB0,WREG REMB0, F UOK458 REMB1, F BARGB0,WREG REMB0, F
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UOK458 RLCF AARGB1, F
UOK45#v(i)
variable i = i + 1 endw RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD4516 ADDWF MOVFP ADDWFC RLCF AARGB2,W REMB1, F REMB0, F BARGB1,WREG AARGB1,LSB UADD4516 REMB1, F BARGB0,WREG REMB0, F UOK4516 REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK4516
UOK45#v(i)
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variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC UOK45 endm AARGB2,LSB UOK45 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV2315 macro ; ; Max Timing: 5+8+22*12+6 = 283 clks ; ; Min Timing: 5+8+22*11+3 = 258 clks ; ; PM: 5+8+22*14+6 = 327 DM: 8 ; variable i MOVFP SUBWF MOVFP SUBWFB RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK35#v(i)
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RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD358 ADDWF MOVFP ADDWFC RLCF AARGB1,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB UADD358 REMB1, F BARGB0,WREG REMB0, F UOK358 REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK358
UOK35#v(i)
UOK3516
variable i = D17 while i < D24 RLCF RLCF AARGB2,W REMB1, F
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RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD35#v(i) ADDWF MOVFP ADDWFC RLCF REMB0, F BARGB1,WREG AARGB2,LSB UADD35#v(i) REMB1, F BARGB0,WREG REMB0, F UOK35#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK35#v(i)
BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC UOK35 endm
AARGB2,LSB UOK35 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
;********************************************************************************************** ;********************************************************************************************** ; ; 16/16 Bit Division Macros ; SDIV1616 macro ; ; Max Timing: 5+8+14*12+6 = 187 clks ; ; Min Timing: 5+8+14*11+6 = 173 clks ; ; PM: 5+8+14*14+6 = 215 DM: 6 ; variable i MOVFP SUBWF MOVFP SUBWFB RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC RLCF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D2 while i < D8 RLCF RLCF AARGB0,W REMB1, F
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RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO SADD66#v(i) ADDWF MOVFP ADDWFC RLCF REMB0, F BARGB1,WREG AARGB0,LSB SADD66#v(i) REMB1, F BARGB0,WREG REMB0, F SOK66#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB0, F
SOK66#v(i)
SOK668
SOK66#v(i)
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BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC SOK66 endm UDIV1616 macro ; ; restore = 15 clks, nonrestore = 11 clks ; ; Max Timing: 8*15+8*15 = 240 clks ; ; Min Timing: 8*11+8*11 = 176 clks ; ; PM: 8*15+8*15 = 240 DM: 6 ; variable i variable i = D0 while i < D8 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC BCF RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK66#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F AARGB1,LSB SOK66 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UOK66#v(i)
variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC AARGB1,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK66#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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UOK66#v(i) BCF RLCF _C AARGB1, F
variable i = i + 1 endw endm NDIV1616 macro ; ; Max Timing: 9+15*15+6 = 240 clks ; ; Min Timing: 9+15*14+6 = 225 clks ; ; PM: 9+15*19+6 = 300 DM: 7 ; variable i RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB RLCF AARGB0,W REMB1, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
NOK66#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO AARGB1,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB0,LSB NADD668
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SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD668 ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK668 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB1, F
NOK668
NOK66#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC NOK66 endm UDIV1615 macro ; ; Max Timing: 7+15*12+6 = 193 clks ; ; Min Timing: 7+15*11+6 = 178 clks ; ; PM: 7+15*14+6 = 213 DM: 6 ; variable i RLCF AARGB0,W AARGB1,LSB NOK66 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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RLCF MOVFP SUBWF MOVFP SUBWFB RLCF REMB1, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK65#v(i)
UOK658
variable i = D9 while i < D16 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF AARGB1,W REMB1, F REMB0, F BARGB1,WREG AARGB1,LSB UADD65#v(i) REMB1, F
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MOVFP SUBWFB GOTO UADD65#v(i) ADDWF MOVFP ADDWFC RLCF BARGB0,WREG REMB0, F UOK65#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK65#v(i)
variable i = D2 while i < D8 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO AARGB0,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB UADD55#v(i) REMB1, F BARGB0,WREG REMB0, F UOK55#v(i)
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UADD55#v(i) ADDWF MOVFP ADDWFC RLCF REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK55#v(i)
UOK558
UOK55#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC UOK55 AARGB1,LSB UOK55 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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endm ;_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ; ; Extra 16 Bit Divide Macros ; DIV1616 macro ; ; Timing: restore = 16 clks, nonrestore = 13 clks 16*16 = 256 clks ; variable i variable i = D0 while i < D16 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSS GOTO BSF GOTO RS1616_#v( i ) MOVFP ADDWF MOVFP ADDWFC BCF AARGB1, F AARGB0, F REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C RS1616_#v( i ) AARGB1,LSB OK1616_#v( i ) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1,LSB
OK1616_#v(i) variable i = i + 1 endw endm DIVMAC ; ; ; macro Timing: restore = 19 clks, variable i variable i = D0 while i < D16 RLCF RLCF RLCF RLCF MOVFP SUBWF BTFSS GOTO MOVFP SUBWF AARGB1, F AARGB0, F REMB1, F REMB0, F BARGB0,WREG REMB0,W _Z notz#v( i ) BARGB1,WREG REMB1,W nonrestore = 14 clks 16*19 = 304 clks
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notz#v( i ) BTFSS GOTO MOVFP SUBWF MOVFP SUBWFB BSF GOTO nosub#v(i) ok#v(i) variable i = i + 1 endw endm BCF _C nosub#v( i ) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1,LSB ok#v(i) AARGB1,LSB
;********************************************************************************************** ;********************************************************************************************** ; ; 16/08 Bit Division Macros ; SDIV1608 macro ; ; Max Timing: 3+5+14*8+2 = 122 clks ; ; Min Timing: 3+5+14*8+2 = 122 clks ; ; PM: 3+5+14*8+2 = 122 DM: 4 ; variable i MOVFP SUBWF RLCF RLCF RLCF MOVFP ADDWF RLCF BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D2 while i < D8 RLCF RLCF MOVFP BTFSC SUBWF BTFSS ADDWF RLCF AARGB0,W REMB0, F BARGB0,WREG AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB0, F
variable i = i + 1 endw RLCF AARGB1,W
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RLCF MOVFP BTFSC SUBWF BTFSS ADDWF RLCF REMB0, F BARGB0,WREG AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm UDIV1608 macro ; ; restore = 9/15 clks, nonrestore = 8/11 clks ; ; Max Timing: 8*9+1+8*15 = 193 clks max ; ; Min Timing: 8*8+1+8*11 = 153 clks min ; ; PM: 8*9+1+8*15 = 193 DM: 4 ; variable i variable i = D0 while i < D8 RLCF RLCF MOVFP SUBWF BTFSC GOTO ADDWF BCF RLCF AARGB0,W REMB0, F BARGB0,WREG REMB0, F _C UOK68#v(i) REMB0, F _C AARGB0, F AARGB1,LSB REMB0, F
UOK68#v(i)
variable i = D8
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while i < D16 RLCF RLCF RLCF MOVFP SUBWF CLRF SUBWFB BTFSC GOTO MOVFP ADDWF CLRF ADDWFC BCF RLCF AARGB1,W REMB0, F TEMP, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK68#v(i) BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB1, F
UOK68#v(i)
variable i = i + 1 endw endm NDIV1608 macro ; ; Max Timing: 7+15*12+3 = 190 clks ; ; Min Timing: 7+15*11+3 = 175 clks ; ; PM: 7+15*14+3 = 220 DM: 5 ; variable i RLCF RLCF MOVFP SUBWF CLRF SUBWFB RLCF AARGB0,W REMB0, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
variable i = D1 while i < D8 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF CLRF SUBWFB GOTO NADD68#v(i) ADDWF CLRF ADDWFC RLCF AARGB0,W REMB0, F TEMP, F BARGB0,WREG AARGB0,LSB NADD68#v(i) REMB0, F WREG, F TEMP, F NOK68#v(i) REMB0, F WREG, F TEMP, F AARGB0, F
NOK68#v(i)
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variable i = i + 1 endw RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF CLRF SUBWFB GOTO NADD688 ADDWF CLRF ADDWFC RLCF AARGB1,W REMB0, F TEMP, F BARGB0,WREG AARGB0,LSB NADD688 REMB0, F WREG, F TEMP, F NOK688 REMB0, F WREG, F TEMP, F AARGB1, F
NOK688
variable i = D9 while i < D16 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF CLRF SUBWFB GOTO NADD68#v(i) ADDWF CLRF ADDWFC RLCF AARGB1,W REMB0, F TEMP, F BARGB0,WREG AARGB1,LSB NADD68#v(i) REMB0, F WREG, F TEMP, F NOK68#v(i) REMB0, F WREG, F TEMP, F AARGB1, F
NOK68#v(i)
variable i = i + 1 endw BTFSS MOVFP ADDWF endm AARGB1,LSB BARGB0,WREG REMB0, F
UDIV1607 macro ; ; Max Timing: 5+15*8+2 = 127 clks ; ; Min Timing: 5+15*8+2 = 127 clks ; ; PM: 5+15*8+2 = 127 DM: 4 ; variable i
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RLCF RLCF MOVFP SUBWF RLCF AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
variable i = i + 1 endw RLCF RLCF MOVFP BTFSC SUBWF BTFSS ADDWF RLCF AARGB1,W REMB0, F BARGB0,WREG AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm UDIV1507 macro ; ; Max Timing: 3+5+14*8+2 = 122 clks ; ; Min Timing: 3+5+14*8+2 = 122 clks ; ; PM: 3+5+14*8+2 = 122 DM: 4 ; variable i AARGB1,LSB REMB0, F
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AN617
MOVFP SUBWF RLCF RLCF RLCF MOVFP ADDWF RLCF BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
variable i = i + 1 endw RLCF RLCF MOVFP BTFSC SUBWF BTFSS ADDWF RLCF AARGB1,W REMB0, F BARGB0,WREG AARGB0,LSB REMB0, F AARGB0,LSB REMB0, F AARGB1, F
variable i = i + 1 endw BTFSS ADDWF endm AARGB1,LSB REMB0, F
;**********************************************************************************************
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;********************************************************************************************** ; ; 08/08 Bit Division Macros ; SDIV0808 macro ; ; Max Timing: 3+5+6*8+2 = 58 clks ; ; Min Timing: 3+5+6*8+2 = 58 clks ; ; PM: 3+5+6*8+2 = 58 DM: 3 ; variable i MOVFP SUBWF RLCF RLCF RLCF MOVFP ADDWF RLCF BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
UDIV0808 macro ; ; restore = 9 clks, nonrestore = 8 clks ; ; Max Timing: 8*9 = 72 clks max ; ; Min Timing: 8*8 = 64 clks min ; ; PM: 8*9 = 72 DM: 3 ; variable i variable i = D0 while i < D8 RLCF RLCF AARGB0,W REMB0, F
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AN617
MOVFP SUBWF BTFSC GOTO ADDWF BCF RLCF BARGB0,WREG REMB0, F _C UOK88#v(i) REMB0, F _C AARGB0, F
UOK88#v(i)
UDIV0807 macro ; ; Max Timing: 5+7*8+2 = 63 clks ; ; Min Timing: 5+7*8+2 = 63 clks ; ; PM: 5+7*8+2 = 63 DM: 3 ; variable i RLCF RLCF MOVFP SUBWF RLCF AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
UDIV0707 macro ; ; Max Timing: 3+5+6*8+2 = 58 clks ; ; Min Timing: 3+5+6*8+2 = 58 clks ; ; PM: 3+5+6*8+2 = 58 DM: 3 ; variable i
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AN617
MOVFP SUBWF RLCF RLCF RLCF MOVFP ADDWF RLCF BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB0, F BARGB0,WREG REMB0, F AARGB0, F
variable i = i + 1 endw BTFSS ADDWF endm ;********************************************************************************************** ;********************************************************************************************** ; ; 24/16 Bit Signed Fixed Point Divide 24/16 -> 24.16 ; ; Input: 24 bit fixed point dividend in AARGB0, AARGB1, AARGB2 ; 16 bit fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD2416S ; ; Output: 24 bit fixed point quotient in AARGB0, AARGB1, AARGB2 ; 16 bit fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 23+283+5 = 311 clks A > 0, B > 0 ; 26+283+17 = 326 clks A > 0, B < 0 ; 28+283+17 = 328 clks A < 0, B > 0 ; 31+283+5 = 319 clks A < 0, B < 0 ; 9 clks A = 0 ; ; Min Timing: 23+258+5 = 286 clks A > 0, B > 0 ; 26+258+17 = 301 clks A > 0, B < 0 ; 28+258+17 = 303 clks A < 0, B > 0 ; 31+258+5 = 294 clks A < 0, B < 0 ; ; PM: 30+327+16+41 = 414 DM: 9 ; FXD2416S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W AARGB0,LSB REMB0, F
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IORWF BTFSC RETLW MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF ADDWFC CA2416S BTFSS GOTO COMF COMF COMF INCF ADDWFC ADDWFC C2416SX MOVPF IORWF BTFSC GOTO SDIV2416 BTFSC GOTO C2416SOK BTFSS RETLW COMF COMF COMF CLRF INCF ADDWFC ADDWFC COMF COMF INCF ADDWFC RETLW C2416SX1 BTFSS GOTO BTFSC GOTO MOVPF MOVPF BCF RLCF RLCF TEMPB3,LSB C2416SX4 SIGN,MSB 0x00 AARGB2, AARGB1, AARGB0, WREG, F AARGB2, AARGB1, AARGB0, REMB1, REMB0, REMB1, REMB0, 0x00 BARGB0,MSB C2416SX3 AARGB0,MSB C2416SX2 AARGB1,REMB0 AARGB2,REMB1 REMB0,MSB AARGB1,F AARGB0,F ; test BARG exception ; test AARG exception F F F F F F F F F F ; test exception flag AARGB2,W _Z 0x00 AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA2416S BARGB1, BARGB0, BARGB1, BARGB0, F F F F ; if MSB set go & negate AARGa ; clear exception flag ; if MSB set go & negate BARG
AARGB0,MSB C2416SX AARGB2, AARGB1, AARGB0, AARGB2, AARGB1, AARGB0, F F F F F F
C2416S
; negate
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AN617
MOVFP CLRF CLRF GOTO CLRF INCF CLRF CLRF RETLW COMF COMF COMF INCF GOTO INCF CLRF ADDWFC MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO CLRF CLRF INCF ADDWFC ADDWFC BTFSS GOTO BSF RETLW AARGB0,AARGB2 AARGB0,F AARGB1,F C2416SOK AARGB2,F AARGB2,F AARGB1,F AARGB0,F 0x00 AARGB0,F AARGB1,F AARGB2,F TEMPB3,F C2416S REMB1,F WREG,F REMB0,F BARGB1,WREG REMB1 C2416SOK BARGB0,WREG REMB0 C2416SOK REMB0,W REMB1,W AARGB2,F AARGB1,F AARGB0,F AARGB0,MSB C2416SOK FPFLAGS,NAN 0xFF
C2416SX2
C2416SX3
C2416SX4
; overflow
; overflow
;********************************************************************************************** ;********************************************************************************************** ; ; 24/16 Bit Unsigned Fixed Point Divide 24/16 -> 24.16 ; ; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 16 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD2416U ; ; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 16 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+361+2 = 365 clks ; ; Min Timing: 2+335+2 = 339 clks ; ; PM: 2+450+1 = 453 DM: 8 ; FXD2416U CLRF REMB0, F CLRF REMB1, F NDIV2416 RETLW 0x00
;********************************************************************************************** ;**********************************************************************************************
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; ; 24/15 Bit Unsigned Fixed Point Divide 24/15 -> 24.15 ; ; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD2415U ; ; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+290+2 = 294 clks ; ; Min Timing: 2+264+2 = 268 clks ; ; PM: 2+336+1 = 339 DM: 8 ; FXD2415U CLRF REMB0, F CLRF REMB1, F UDIV2415 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 23/15 Bit Unsigned Fixed Point Divide 23/15 -> 23.15 ; ; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD2315U ; ; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+283+2 = 287 clks ; ; Min Timing: 2+258+2 = 262 clks ; ; PM: 2+327+1 = 330 DM: 8 ; FXD2315U CLRF REMB0, F CLRF REMB1, F UDIV2315 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 16/16 Bit Signed Fixed Point Divide 16/16 -> 16.16 ; ; Input: 16 bit fixed point dividend in AARGB0, AARGB1 ; 16 bit fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD1616S ; ; Output: 16 bit fixed point quotient in AARGB0, AARGB1 ; 16 bit fixed point remainder in REMB0, REMB1
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; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 22+187+5 = 214 clks ; 25+187+15 = 227 clks ; 25+187+15 = 227 clks ; 28+187+5 = 220 clks ; 8 clks ; ; Min Timing: 22+173+5 = 200 clks ; 25+173+15 = 213 clks ; 25+173+15 = 213 clks ; 28+173+5 = 206 clks ; ; PM: 27+215+14+34 = 290 DM: 8 ; FXD1616S CLRF SIGN,F CLRF REMB0,F CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W BTFSC _Z RETLW 0x00 MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF ADDWFC CA1616S BTFSS GOTO COMF COMF INCF ADDWFC C1616SX MOVPF IORWF BTFSC GOTO SDIV1616 BTFSC GOTO C1616SOK BTFSS RETLW COMF COMF CLRF INCF ADDWFC TEMPB3,LSB C1616SX4 SIGN,MSB 0x00 AARGB1, AARGB0, WREG, F AARGB1, AARGB0, F F F F ; test exception flag AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA1616S BARGB1, BARGB0, BARGB1, BARGB0, F F F F ; if MSB set go & negate AARGa ; clear exception flag ; if MSB set go & negate BARG
A A A A A A A A A
> > < < = > > < <
0, 0, 0, 0, 0 0, 0, 0, 0,
B B B B
> < > <
0 0 0 0
B B B B
> < > <
0 0 0 0
AARGB0,MSB C1616SX AARGB1, AARGB0, AARGB1, AARGB0, F F F F
C1616S
; negate
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COMF COMF INCF ADDWFC RETLW C1616SX1 BTFSS GOTO BTFSC GOTO MOVPF MOVPF CLRF CLRF GOTO CLRF CLRF INCF RETLW COMF COMF INCF GOTO INCF CLRF ADDWFC MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO CLRF CLRF INCF ADDWFC BTFSS GOTO BSF RETLW REMB1, REMB0, REMB1, REMB0, 0x00 BARGB0,MSB C1616SX3 AARGB0,MSB C1616SX2 AARGB0,REMB0 AARGB1,REMB1 AARGB0,F AARGB1,F C1616SOK AARGB0,F AARGB1,F AARGB1,F 0x00 AARGB0,F AARGB1,F TEMPB3,F C1616S REMB1,F WREG,F REMB0,F BARGB1,WREG REMB1 C1616SOK BARGB0,WREG REMB0 C1616SOK REMB0,F REMB1,W AARGB1,F AARGB0,F AARGB0,MSB C1616SOK FPFLAGS,NAN 0xFF ; test BARG exception ; test AARG exception ; quotient = 0, remainder = AARG F F F F
C1616SX2
C1616SX3
C1616SX4
;********************************************************************************************** ;********************************************************************************************** ; ; 16/16 Bit Unsigned Fixed Point Divide 16/16 -> 16.16 ; ; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 16 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD1616U ; ; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 16 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+240+2 = 244 clks ; ; Min Timing: 2+176+2 = 180 clks ;
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; PM: 2+240+1 = 243 ; FXD1616U CLRF CLRF UDIV1616 RETLW 0x00 DM: 6 REMB0, F REMB1, F
;********************************************************************************************** ;********************************************************************************************** ; ; 16/15 Bit Unsigned Fixed Point Divide 16/15 -> 16.15 ; ; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD1615U ; ; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+193+2 = 197 clks ; ; Min Timing: 2+178+2 = 182 clks ; ; PM: 2+213+1 = 216 DM: 6 ; FXD1615U CLRF REMB0, F CLRF REMB1, F UDIV1615 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 15/15 Bit Unsigned Fixed Point Divide 15/15 -> 15.15 ; ; Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD1515U ; ; Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+187+2 = 191 clks ; ; Min Timing: 2+173+2 = 177 clks ; ; PM: 2+215+1 = 218 DM: 6 ; FXD1515U CLRF REMB0, F CLRF REMB1, F UDIV1515 RETLW 0x00
;**********************************************************************************************
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;********************************************************************************************** ; ; 16/8 Bit Signed Fixed Point Divide 16/08 -> 16.08 ; ; Input: 16 bit fixed point dividend in AARGB0, AARGB1 ; 8 bit fixed point divisor in BARGB0 ; ; Use: CALL FXD1608S ; ; Output: 16 bit fixed point quotient in AARGB0, AARGB1 ; 8 bit fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 21+122+5 = 148 clks A > 0, B > 0 ; 22+122+13 = 157 clks A > 0, B < 0 ; 24+122+13 = 159 clks A < 0, B > 0 ; 25+122+5 = 152 clks A < 0, B < 0 ; 7 clks A = 0 ; ; Min Timing: 21+122+5 = 148 clks A > 0, B > 0 ; 22+122+13 = 157 clks A > 0, B < 0 ; 24+122+13 = 159 clks A < 0, B > 0 ; 25+122+5 = 152 clks A < 0, B < 0 ; ; PM: 25+122+12+30 = 189 DM: 6 ; FXD1608S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder MOVPF AARGB0,WREG IORWF AARGB1,W BTFSC _Z RETLW 0x00 MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF INCF CA1608S BTFSS GOTO COMF COMF INCF ADDWFC C1608SX MOVPF IORWF BTFSC GOTO SDIV1608 BTFSC GOTO C1608SOK BTFSS TEMPB3,LSB C1608SX4 SIGN,MSB ; test exception flag AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA1608S BARGB0, F BARGB0, F AARGB0,MSB C1608SX AARGB1, AARGB0, AARGB1, AARGB0, F F F F ; if MSB set go & negate AARGa ; clear exception flag ; if MSB set go & negate BARG
C1608S
; negate
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RETLW COMF COMF CLRF INCF ADDWFC COMF INCF RETLW C1608SX1 BTFSS GOTO BTFSC GOTO MOVPF BCF RLCF RLCF MOVFP CLRF GOTO CLRF INCF CLRF RETLW COMF COMF INCF GOTO INCF MOVFP CPFSEQ GOTO CLRF INCF ADDWFC BTFSS GOTO BSF RETLW 0x00 AARGB1, AARGB0, WREG, F AARGB1, AARGB0, REMB0, F REMB0, F 0x00 BARGB0,MSB C1608SX3 AARGB0,MSB C1608SX2 AARGB1,REMB0 REMB0,MSB AARGB1,F AARGB0,F AARGB0,AARGB1 AARGB0,F C1608SOK AARGB1,F AARGB1,F AARGB0,F 0x00 AARGB0,F AARGB1,F TEMPB3,F C1608S REMB0,F BARGB0,WREG REMB0 C1608SOK REMB0,W AARGB1,F AARGB0,F AARGB0,MSB C1608SOK FPFLAGS,NAN 0xFF ; test BARG exception ; test AARG exception F F F F
C1608SX2
C1608SX3
C1608SX4
;********************************************************************************************** ;********************************************************************************************** ; ; 16/8 Bit Unsigned Fixed Point Divide 16/08 -> 16.08 ; ; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 8 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD1608U ; ; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 8 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+193+2 = 196 clks ; ; Min Timing: 1+153+2 = 156 clks ;
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; PM: 1+193+1 = 195 ; FXD1608U CLRF UDIV1608 RETLW 0x00 DM: 4 REMB0, F
;********************************************************************************************** ;********************************************************************************************** ; ; 16/7 Bit Unsigned Fixed Point Divide 16/07 -> 16.07 ; ; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 7 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD1607U ; ; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 7 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+127+2 = 130 clks ; ; Min Timing: 1+127+2 = 130 clks ; ; PM: 1+127+1 = 129 DM: 4 ; FXD1607U CLRF REMB0, F UDIV1607 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; 15/7 Bit Unsigned Fixed Point Divide 15/07 -> 15.07 ; ; Input: 15 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 7 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD1507U ; ; Output: 15 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 7 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+122+2 = 125 clks ; ; Min Timing: 1+122+2 = 125 clks ; ; PM: 1+122+1 = 124 DM: 4 ; FXD1507U CLRF REMB0, F UDIV1507 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 8/8 Bit Signed Fixed Point Divide 08/08 -> 08.08 ;
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; Input: 8 bit fixed point dividend in AARGB0 ; 8 bit fixed point divisor in BARGB0 ; ; Use: CALL FXD0808S ; ; Output: 8 bit fixed point quotient in AARGB0 ; 8 bit fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 19+58+5 = 82 clks A > ; 20+58+10 = 88 clks A > ; 20+58+10 = 88 clks A < ; 21+58+5 = 84 clks A < ; 6 clks A = ; ; Min Timing: 19+58+5 = 82 clks A > ; 20+58+10 = 88 clks A > ; 20+58+10 = 88 clks A < ; 21+58+5 = 84 clks A < ; ; PM: 20+58+9+23 = 110 DM: 5 ; FXD0808S CLRF SIGN,F CLRF REMB0,F ; clear MOVPF AARGB0,WREG BTFSC _Z RETLW 0x00 XORWF BTFSC COMF CLRF BTFSS GOTO COMF INCF CA0808S BTFSS GOTO COMF INCF C0808SX MOVPF IORWF BTFSC GOTO SDIV0808 BTFSC GOTO C0808SOK BTFSS RETLW COMF INCF COMF INCF TEMPB3,LSB C0808SX4 SIGN,MSB 0x00 AARGB0, F AARGB0, F REMB0, F REMB0, F ; test exception flag BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA0808S BARGB0, F BARGB0, F AARGB0,MSB C0808SX AARGB0, F AARGB0, F AARGB0,WREG BARGB0,W WREG,MSB C0808SX1 ; clear exception flag
0, 0, 0, 0, 0 0, 0, 0, 0,
B B B B
> < > <
0 0 0 0
B B B B
> < > <
0 0 0 0
partial remainder
C0808S
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RETLW C0808SX1 BTFSS GOTO BTFSC GOTO MOVPF CLRF GOTO CLRF INCF RETLW COMF INCF GOTO INCF MOVFP CPFSEQ GOTO CLRF INCF BTFSS GOTO BSF RETLW 0x00 BARGB0,MSB C0808SX3 AARGB0,MSB C0808SX2 AARGB0,REMB0 AARGB0,F C0808SOK AARGB0,F AARGB0,F 0x00 AARGB0,F TEMPB3,F C0808S REMB0,F BARGB0,WREG REMB0 C0808SOK REMB0,F AARGB0,F AARGB0,MSB C0808SOK FPFLAGS,NAN 0xFF ; test BARG exception ; test AARG exception ; quotient = 0, remainder = AARG
C0808SX2
C0808SX3
; numerator = 0x7F + 1
C0808SX4
;********************************************************************************************** ;********************************************************************************************** ; ; 8/8 Bit Unsigned Fixed Point Divide 08/08 -> 08.08 ; ; Input: 8 bit unsigned fixed point dividend in AARGB0 ; 8 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD0808U ; ; Output: 8 bit unsigned fixed point quotient in AARGB0 ; 8 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+72+2 = 75 clks ; ; Min Timing: 1+64+2 = 67 clks ; ; PM: 1+72+1 = 74 DM: 3 ; FXD0808U CLRF REMB0, F UDIV0808 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 8/7 Bit Unsigned Fixed Point Divide 08/07 -> 08.07 ; ; Input: 8 bit unsigned fixed point dividend in AARGB0 ; 7 bit unsigned fixed point divisor in BARGB0 ;
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; Use: CALL FXD0807U ; ; Output: 8 bit unsigned fixed point quotient in AARGB0 ; 7 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+63+2 = 66 clks ; ; Min Timing: 1+63+2 = 66 clks ; ; PM: 1+63+1 = 65 DM: 3 ; FXD0807U CLRF REMB0, F UDIV0807 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; 7/7 Bit Unsigned Fixed Point Divide 07/07 -> 07.07 ; ; Input: 7 bit unsigned fixed point dividend in AARGB0 ; 7 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD0707U ; ; Output: 7 bit unsigned fixed point quotient in AARGB0 ; 7 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+58+2 = 61 clks ; ; Min Timing: 1+58+2 = 61 clks ; ; PM: 1+58+1 = 60 DM: 3 ; FXD0707U CLRF REMB0, F UDIV0707 RETLW 0x00
;********************************************************************************************** ;**********************************************************************************************
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G.3
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
PIC17CXXX Fixed Point Divide Routines C

RCS Header $Id: fxdc.a17 2.4 1997/03/22 03:11:13 F.J.Testa Exp $ $Revision: 2.4 $ PIC17 FIXED POINT DIVIDE ROUTINES C Input: fixed point arguments in AARG and BARG
Output: quotient AARG/BARG followed by remainder in REM All timings are worst case cycle counts It is useful to note that the additional unsigned routines requiring a non-power of two argument can be called in a signed divide application where it is known that the respective argument is nonnegative, thereby offering some improvement in performance. Routine FXD3216S FXD3216U FXD3215U FXD3115U Clocks 429 485 390 383 Function 32 bit/16 bit -> 32.16 signed fixed point divide 32 bit/16 bit -> 32.16 unsigned fixed point divide 32 bit/15 bit -> 32.15 unsigned fixed point divide 31 bit/15 bit -> 31.15 unsigned fixed point divide
404 440 369 361
;********************************************************************************************** ;********************************************************************************************** ; ; 32/16 Bit Division Macros ; SDIV3216 macro ; ; Max Timing: 5+8+30*12+6 = 379 clks ; ; Min Timing: 5+8+30*11+6 = 349 clks ; ; PM: 5+8+30*14+6 = 439 DM: 8 ; variable i MOVFP SUBWF MOVFP SUBWFB RLCF RLCF RLCF RLCF MOVFP ADDWF BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F
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MOVFP ADDWFC RLCF BARGB0,WREG REMB0, F AARGB0, F
SOK26#v(i)
SOK268
SOK26#v(i)
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SOK2616
SOK26#v(i)
SOK2624
variable i = D25
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while i < D32 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO SADD26#v(i) ADDWF MOVFP ADDWFC RLCF AARGB3,W REMB1, F REMB0, F BARGB1,WREG AARGB3,LSB SADD26#v(i) REMB1, F BARGB0,WREG REMB0, F SOK26#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB3, F
SOK26#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC SOK26 endm UDIV3216 macro ; ; restore = 15/20 clks, nonrestore = 11/14 clks ; ; Max Timing: 16*15+1+16*20 = 561 clks ; ; Min Timing: 16*11+1+16*14 = 401 clks ; ; PM: 16*15+1+16*20 = 561 DM: 9 ; variable i variable i = D0 while i < D8 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC BCF UOK26#v(i) RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK26#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F AARGB3,LSB SOK26 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC BCF UOK26#v(i) RLCF AARGB1,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK26#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB1, F
variable i = D16 while i < D24 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC CLRF ADDWFC BCF UOK26#v(i) RLCF AARGB2,W REMB1, F REMB0, F TEMP, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK26#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB2, F
variable i = i + 1 endw variable i = D24 while i < D32
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RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC CLRF ADDWFC BCF UOK26#v(i) RLCF AARGB3,W REMB1, F REMB0, F TEMP, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK26#v(i) BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB3, F
variable i = i + 1 endw endm NDIV3216 macro ; ; Max Timing: 10+31*15+6 = 481 clks ; ; Min Timing: 10+31*14+6 = 450 clks ; ; PM: 10+31*19+6 = 605 DM: 9 ; variable i RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB CLRF SUBWFB RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
variable i = D1 while i < D8 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO AARGB0,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB0,LSB NADD26#v(i) REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK26#v(i)
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NADD26#v(i) ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB0, F
NOK26#v(i)
NOK268
NOK26#v(i)
variable i = i + 1 endw RLCF AARGB2,W
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RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD2616 ADDWF MOVFP ADDWFC CLRF ADDWFC RLCF REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB1,LSB NADD2616 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2616 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB2, F
NOK2616
NOK26#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB CLRF SUBWFB GOTO NADD2624 ADDWF AARGB3,W REMB1, F REMB0, F TEMP, F BARGB1,WREG AARGB2,LSB NADD2624 REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK2624 REMB1, F
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MOVFP ADDWFC CLRF ADDWFC NOK2624 RLCF BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB3, F
NOK26#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC NOK26 endm UDIV3215 macro ; ; Max Timing: 8+31*12+6 = 386 clks ; ; Min Timing: 8+31*11+6 = 355 clks ; ; PM: 8+31*14+6 = 448 DM: 8 ; variable i RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB RLCF AARGB0,W REMB1, F REMB0, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB3,LSB NOK26 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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UOK25#v(i)
UOK258
UOK25#v(i)
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RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD2516 ADDWF MOVFP ADDWFC RLCF AARGB2,W REMB1, F REMB0, F BARGB1,WREG AARGB1,LSB UADD2516 REMB1, F BARGB0,WREG REMB0, F UOK2516 REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK2516
UOK25#v(i)
UOK2524
variable i = D25 while i < D32 RLCF AARGB3,W
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RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO UADD25#v(i) ADDWF MOVFP ADDWFC RLCF REMB1, F REMB0, F BARGB1,WREG AARGB3,LSB UADD25#v(i) REMB1, F BARGB0,WREG REMB0, F UOK25#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB3, F
UOK25#v(i)
variable i = D2 while i < D8 RLCF RLCF RLCF MOVFP BTFSS GOTO AARGB0,W REMB1, F REMB0, F BARGB1,WREG AARGB0,LSB UADD15#v(i)
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SUBWF MOVFP SUBWFB GOTO UADD15#v(i) ADDWF MOVFP ADDWFC RLCF REMB1, F BARGB0,WREG REMB0, F UOK15#v(i) REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK15#v(i)
UOK158
UOK15#v(i)
variable i = i + 1 endw RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB AARGB2,W REMB1, F REMB0, F BARGB1,WREG AARGB1,LSB UADD1516 REMB1, F BARGB0,WREG REMB0, F
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GOTO UADD1516 ADDWF MOVFP ADDWFC RLCF UOK1516 REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK1516
UOK15#v(i)
UOK1524
variable i = D25 while i < D32 RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB GOTO AARGB3,W REMB1, F REMB0, F BARGB1,WREG AARGB3,LSB UADD15#v(i) REMB1, F BARGB0,WREG REMB0, F UOK15#v(i)
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UADD15#v(i) ADDWF MOVFP ADDWFC RLCF REMB1, F BARGB0,WREG REMB0, F AARGB3, F
UOK15#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC UOK15 endm ;********************************************************************************************** ;********************************************************************************************** ; ; 24/24 Bit Division Macros ; SDIV2424 macro ; ; Max Timing: 7+11+22*15+8 = 356 clks ; ; Min Timing: 7+11+22*14+3 = 329 clks ; ; PM: 7+11+22*19+8 = 444 DM: 9 ; variable i MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB3,LSB UOK15 BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
variable i = D2 while i < D8 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB SADD44#v(i)
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SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO SADD44#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F SOK44#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
SOK44#v(i)
SOK448
SOK44#v(i)
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SOK4416
SOK44#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC AARGB2,LSB SOK44 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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SOK44 endm
UDIV2424 macro ; ; restore = 20/25 clks, nonrestore = 14/17 clks ; ; Max Timing: 16*20+1+8*25 = 521 clks ; ; Min Timing: 16*14+1+8*17 = 361 clks ; ; PM: 16*20+1+8*25 = 521 DM: 10 ; variable i variable i = 0 while i < 8 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC BCF UOK44#v(i) RLCF AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK44#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C AARGB0, F
variable i = i + 1 endw variable i = D8 while i < D16 RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F _C UOK44#v(i) BARGB2,WREG REMB2, F BARGB1,WREG
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ADDWFC MOVFP ADDWFC BCF UOK44#v(i) RLCF REMB1, F BARGB0,WREG REMB0, F _C AARGB1, F
variable i = D16 while i < D24 RLCF RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC BCF UOK44#v(i) RLCF AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C UOK44#v(i) BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F _C AARGB2, F
endm NDIV2424 macro ; ; Max Timing: 13+23*18+8 = 435 clks ; ; Min Timing: 13+23*17+3 = 407 clks ; ; PM: 13+23*24+8 = 573 DM: 10 ; variable i RLCF RLCF RLCF RLCF MOVFP AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG
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SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB RLCF REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F TEMP,W TEMP, F AARGB0, F
NOK44#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD448 ADDWF MOVFP ADDWFC MOVFP ADDWFC AARGB1,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB0,LSB NADD448 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK448 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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CLRF ADDWFC NOK448 RLCF WREG, F TEMP, F AARGB1, F
NOK44#v(i)
variable i = i + 1 endw RLCF RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB CLRF SUBWFB GOTO NADD4416 ADDWF MOVFP ADDWFC MOVFP ADDWFC CLRF ADDWFC RLCF AARGB2,W REMB2, F REMB1, F REMB0, F TEMP, F BARGB2,WREG AARGB1,LSB NADD4416 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F NOK4416 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F WREG, F TEMP, F AARGB2, F
NOK4416
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NOK44#v(i)
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC NOK44 endm AARGB2,LSB NOK44 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV2423 macro ; ; Max Timing: 11+23*15+8 = 364 clks ; ; Min Timing: 11+23*14+3 = 336 clks ; ; PM: 11+23*19+8 = 456 ; variable i RLCF RLCF RLCF RLCF MOVFP SUBWF MOVFP AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG
DM: 9
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SUBWFB MOVFP SUBWFB RLCF REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK43#v(i)
UOK438
variable i = D9 while i < D16 RLCF RLCF RLCF RLCF MOVFP AARGB1,W REMB2, F REMB1, F REMB0, F BARGB2,WREG
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BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD43#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB1,LSB UADD43#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK43#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB1, F
UOK43#v(i)
UOK4316
variable i = D17 while i < D24 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD43#v(i) ADDWF MOVFP ADDWFC MOVFP AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB2,LSB UADD43#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK43#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG
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ADDWFC UOK43#v(i) RLCF REMB0, F AARGB2, F
variable i = i + 1 endw BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC UOK43 endm AARGB2,LSB UOK43 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
UDIV2323 macro ; ; Max Timing: 7+11+22*15+8 = 356 clks ; ; Min Timing: 7+11+22*14+3 = 329 clks ; ; PM: 7+11+22*19+8 = 444 DM: 9 ; variable i MOVFP SUBWF MOVFP SUBWFB MOVFP SUBWFB RLCF RLCF RLCF RLCF RLCF MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
variable i = D2 while i < D8 RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP AARGB0,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB0,LSB UADD33#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG
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SUBWFB GOTO UADD33#v(i) ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF REMB0, F UOK33#v(i) REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB0, F
UOK33#v(i)
UOK338
UOK33#v(i)
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RLCF RLCF RLCF RLCF MOVFP BTFSS GOTO SUBWF MOVFP SUBWFB MOVFP SUBWFB GOTO UADD3316 ADDWF MOVFP ADDWFC MOVFP ADDWFC RLCF AARGB2,W REMB2, F REMB1, F REMB0, F BARGB2,WREG AARGB1,LSB UADD3316 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F UOK3316 REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F AARGB2, F
UOK3316
UOK33#v(i)
BTFSC GOTO MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC UOK33
AARGB2,LSB UOK33 BARGB2,WREG REMB2, F BARGB1,WREG REMB1, F BARGB0,WREG REMB0, F
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AN617
endm ;********************************************************************************************** ;********************************************************************************************** ; ; 32/16 Bit Signed Fixed Point Divide 32/16 -> 32.16 ; ; Input: 32 bit signed fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 16 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD3216S ; ; Output: 32 bit signed fixed point quotient in AARGB0, AARGB1,AARGB2,AARGB3 ; 16 bit fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 24+379+5 = 408 clks A > 0, B > 0 ; 27+379+19 = 425 clks A > 0, B < 0 ; 31+379+19 = 429 clks A < 0, B > 0 ; 34+379+5 = 418 clks A < 0, B < 0 ; 10 clks A = 0 ; ; Min Timing: 24+349+5 = 378 clks A > 0, B > 0 ; 27+349+19 = 395 clks A > 0, B < 0 ; 31+349+19 = 399 clks A < 0, B > 0 ; 34+349+5 = 388 clks A < 0, B < 0 ; ; PM: 34+439+18+46 = 537 DM: 10 ; FXD3216S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F MOVPF AARGB0,WREG IORWF AARGB1,W IORWF AARGB2,W IORWF AARGB3,W BTFSC _Z RETLW 0x00 MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF INCF ADDWFC CA3216S BTFSS GOTO COMF COMF COMF COMF INCF ADDWFC ADDWFC ADDWFC AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA3216S BARGB1, BARGB0, BARGB1, BARGB0, F F F F ; if MSB set go & negate AARGa ; clear exception flag ; if MSB set go & negate BARG
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AN617
C3216SX MOVPF IORWF BTFSC GOTO SDIV3216 BTFSC GOTO C3216SOK BTFSS RETLW COMF COMF COMF COMF CLRF INCF ADDWFC ADDWFC ADDWFC COMF COMF INCF ADDWFC RETLW TEMPB3,LSB C3216SX4 SIGN,MSB 0x00 AARGB3, AARGB2, AARGB1, AARGB0, WREG, F AARGB3, AARGB2, AARGB1, AARGB0, REMB1, REMB0, REMB1, REMB0, 0x00 F F F F F F F F F F F F ; test exception flag AARGB0,WREG BARGB0,W WREG,MSB C3216SX1
C3216S
; negate
C3216SX1
C3216SX2
BTFSS GOTO BTFSC GOTO MOVPF MOVPF BCF RLCF RLCF RLCF MOVFP MOVFP CLRF CLRF GOTO CLRF INCF CLRF CLRF CLRF RETLW COMF COMF COMF COMF INCF GOTO INCF CLRF ADDWFC MOVFP CPFSEQ
BARGB0,MSB C3216SX3 AARGB0,MSB C3216SX2 AARGB2,REMB0 AARGB3,REMB1 REMB0,MSB AARGB2,F AARGB1,F AARGB0,F AARGB0,AARGB2 AARGB1,AARGB3 AARGB0,F AARGB1,F C3216SOK AARGB3,F AARGB3,F AARGB2,F AARGB1,F AARGB0,F 0x00 AARGB0,F AARGB1,F AARGB2,F AARGB3,F TEMPB3,F C3216S REMB1,F WREG,F REMB0,F BARGB1,WREG REMB1
; test BARG exception ; test AARG exception
C3216SX3
C3216SX4
; overflow
DS00617B-page 375
AN617
GOTO MOVFP CPFSEQ GOTO CLRF CLRF INCF ADDWFC ADDWFC ADDWFC BTFSS GOTO BSF RETLW C3216SOK BARGB0,WREG REMB0 C3216SOK REMB0,W REMB1,W AARGB3,F AARGB2,F AARGB1,F AARGB0,F AARGB0,MSB C3216SOK FPFLAGS,NAN 0xFF ; overflow
;********************************************************************************************** ;********************************************************************************************** ; ; 32/16 Bit Unsigned Fixed Point Divide 32/16 -> 32.16 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 16 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD3216U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1AARGB2,AARGB3 ; 16 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+481+2 = 485 clks ; ; Min Timing: 2+450+2 = 459 clks ; ; PM: 2+605+1 = 608 DM: 9 ; FXD3216U CLRF REMB0, F CLRF REMB1, F NDIV3216 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 32/15 Bit Unsigned Fixed Point Divide 32/15 -> 32.15 ; ; Input: 32 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD3215U ; ; Output: 32 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+386+2 = 390 clks ; ; Min Timing: 2+355+2 = 359 clks ; ; PM: 2+448+1 = 451 DM: 8 ;
DS00617B-page 376
AN617
FXD3215U CLRF CLRF UDIV3215 RETLW 0x00 REMB0, F REMB1, F
;********************************************************************************************** ;********************************************************************************************** ; ; 31/15 Bit Unsigned Fixed Point Divide 31/15 -> 31.15 ; ; Input: 31 bit unsigned fixed point dividend in AARGB0, AARGB1,AARGB2,AARGB3 ; 15 bit unsigned fixed point divisor in BARGB0, BARGB1 ; ; Use: CALL FXD3115U ; ; Output: 31 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 15 bit unsigned fixed point remainder in REMB0, REMB1 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 2+379+2 = 383 clks ; ; Min Timing: 2+349+2 = 353 clks ; ; PM: 2+439+1 = 442 DM: 8 ; FXD3115U CLRF REMB0, F CLRF REMB1, F UDIV3115 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 24/24 Bit Signed Fixed Point Divide 24/24 -> 24.24 ; ; Input: 24 bit signed fixed point dividend in AARGB0, AARGB1, AARGB2 ; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD2424S ; ; Output: 24 bit signed fixed point quotient in AARGB0, AARGB1, AARGB2 ; 24 bit fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 24+356+5 = 385 clks A > 0, B > 0 ; 29+356+19 = 404 clks A > 0, B < 0 ; 29+356+19 = 404 clks A < 0, B > 0 ; 34+356+5 = 395 clks A < 0, B < 0 ; 10 clks A = 0 ; ; Min Timing: 24+329+5 = 358 clks A > 0, B > 0 ; 29+329+19 = 377 clks A > 0, B < 0 ; 29+329+19 = 377 clks A < 0, B > 0 ; 34+329+5 = 368 clks A < 0, B < 0 ; ; PM: 34+444+18+44 = 540 DM: 11 ; FXD2424S CLRF SIGN,F CLRF REMB0,F ; clear partial remainder CLRF REMB1,F
DS00617B-page 377
AN617
CLRF MOVPF IORWF IORWF BTFSC RETLW MOVPF XORWF BTFSC COMF CLRF BTFSS GOTO COMF COMF COMF INCF ADDWFC ADDWFC CA2424S BTFSS GOTO COMF COMF COMF INCF ADDWFC ADDWFC C2424SX MOVPF IORWF BTFSC GOTO SDIV2424 BTFSC GOTO C2424SOK BTFSS RETLW COMF COMF COMF CLRF INCF ADDWFC ADDWFC COMF COMF COMF INCF ADDWFC ADDWFC RETLW C2424SX1 BTFSS GOTO TEMPB3,LSB C2424SX4 SIGN,MSB 0x00 AARGB2, AARGB1, AARGB0, WREG, F AARGB2, AARGB1, AARGB0, REMB2, REMB1, REMB0, REMB2, REMB1, REMB0, 0x00 BARGB0,MSB C2424SX3 ; test BARG exception F F F F F F F F F F F F ; test exception flag REMB2,F AARGB0,WREG AARGB1,W AARGB2,W _Z 0x00 AARGB0,WREG BARGB0,W WREG,MSB SIGN,F TEMPB3,W BARGB0,MSB CA2424S BARGB2, BARGB1, BARGB0, BARGB2, BARGB1, BARGB0, F F F F F F ; if MSB set, negate AARG ; clear exception flag ; if MSB set, negate BARG
AARGB0,MSB C2424SX AARGB2, AARGB1, AARGB0, AARGB2, AARGB1, AARGB0, F F F F F F
C2424S
DS00617B-page 378
AN617
BTFSC GOTO MOVPF MOVPF MOVPF CLRF CLRF CLRF GOTO CLRF CLRF CLRF INCF RETLW COMF COMF COMF INCF GOTO INCF CLRF ADDWFC ADDWFC MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO MOVFP CPFSEQ GOTO CLRF CLRF CLRF INCF ADDWFC ADDWFC BTFSS GOTO BSF RETLW AARGB0,MSB C2424SX2 AARGB0,REMB0 AARGB1,REMB1 AARGB2,REMB2 AARGB0,F AARGB1,F AARGB2,F C2424SOK AARGB0,F AARGB1,F AARGB2,F AARGB2,F 0x00 AARGB0,F AARGB1,F AARGB2,F TEMPB3,F C2424S REMB2,F WREG,F REMB1,F REMB0,F BARGB2,WREG REMB2 C2424SOK BARGB1,WREG REMB1 C2424SOK BARGB0,WREG REMB0 C2424SOK REMB0,F REMB1,F REMB2,W AARGB2,F AARGB1,F AARGB0,F AARGB0,MSB C2424SOK FPFLAGS,NAN 0xFF ; test AARG exception ; quotient = 0, remainder = AARG
C2424SX2
C2424SX3
C2424SX4
;********************************************************************************************** ;********************************************************************************************** ; ; 24/24 Bit Unsigned Fixed Point Divide 24/24 -> 24.24 ; ; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 24 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD2424U ; ; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 24 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 3+435+2 = 440 clks ; ; Min Timing: 3+407+2 = 412 clks ;
DS00617B-page 379
AN617
; PM: 3+573+1 = 577 ; FXD2424U CLRF CLRF CLRF NDIV2424 RETLW 0x00 DM: 10 REMB0, F REMB1, F REMB2, F
;********************************************************************************************** ;********************************************************************************************** ; ; 24/23 Bit Unsigned Fixed Point Divide 24/23 -> 24.23 ; ; Input: 24 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD2423U ; ; Output: 24 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 3+364+2 = 369 clks ; ; Min Timing: 3+336+2 = 341 clks ; ; PM: 3+456+1 = 460 DM: 9 ; FXD2423U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F UDIV2423 RETLW 0x00
;********************************************************************************************** ;********************************************************************************************** ; ; 23/23 Bit Unsigned Fixed Point Divide 23/23 -> 23.23 ; ; Input: 23 bit unsigned fixed point dividend in AARGB0, AARGB1, AARGB2 ; 23 bit unsigned fixed point divisor in BARGB0, BARGB1, BARGB2 ; ; Use: CALL FXD2323U ; ; Output: 23 bit unsigned fixed point quotient in AARGB0, AARGB1, AARGB2 ; 23 bit unsigned fixed point remainder in REMB0, REMB1, REMB2 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 3+356+2 = 361 clks ; ; Min Timing: 3+329+2 = 334 clks ; ; PM: 3+444+1 = 448 DM: 9 ; FXD2323U CLRF REMB0, F CLRF REMB1, F CLRF REMB2, F UDIV2323
DS00617B-page 380
AN617
RETLW 0x00
;********************************************************************************************** ;**********************************************************************************************
DS00617B-page 381
Note the following details of the code protection feature on PICmicro MCUs. The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.
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01/18/02

Fixed Point Routines - 00617b

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Fixed Point Routines - 00617b

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AN617

FIXED POINT ARITHMETIC

1996 Microchip Technology Inc.

FIXED POINT LIBRARY ROUTINE SUMMARY TABLE

8/8 16/8 16/16 24/16 24/24 32/16 32/24 32/32

8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32

8/8 16/8 16/16 24/16 24/24 32/16 32/24 32/32

8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32

Note: U - unsigned math operation, S - signed math operation

1996 Microchip Technology Inc.

DATA RAM REQUIREMENTS

BARG MSB BARG exponent

TWO BYTE ADDITION/SUBTRACTION ROUTINES

MOVF SUBWF MOVF BTFSS INCFSZ SUBWF

1996 Microchip Technology Inc.

8x8 16x8 16x16 24x16 24x24 32x16 32x24 32x32

FXM1616U(0x0458,0x822C) = FXM1616U(1112,33324) = 0x02356F20 = 37056288

1996 Microchip Technology Inc.

PIC17CXXX FIXED POINT MULTIPLY PERFORMANCE DATA

1996 Microchip Technology Inc.

PIC16C5X/PIC16CXXX FIXED POINT MULTIPLY PERFORMANCE DATA

1996 Microchip Technology Inc.

AARG = BARG QUOTIENT + REMAINDER,

FXD1608S(0xC116,0x60) = 0xFF59, 0xB6 FXD1616U(0x9543,0x4AA1) = 0x0002, 0x0001

1996 Microchip Technology Inc.

PIC17CXXX FIXED POINT DIVIDE PERFORMANCE DATA

1996 Microchip Technology Inc.

PIC16C5X/PIC16CXXX FIXED POINT DIVIDE PERFORMANCE DATA

1996 Microchip Technology Inc.

Fractional conversion algorithm[3]:

Integer conversion algorithm[3]:

while k <= n d(k) = F(k) 2 F(k+1) = fractional part of F(k) 2 k = k + 1 endw

1996 Microchip Technology Inc.

i=0 clear high order partial product

i=0 clear high order partial product

No add multiplicand to high order partial product

negate multiplier and multiplicand save sign of result

right shift partial product i=i+1

add multiplicand to high order partial product

Return and indicate no error

Return and indicate no error

1996 Microchip Technology Inc.

Compute, add aligned byte products of AARG * BARG

Compute, add aligned byte products of AARG * BARG

Return and indicate no error

subtract BARG from most signicant bytes of product

Yes BARG < 0?

subtract AARG from most signicant bytes of product

Return and indicate no error

1996 Microchip Technology Inc.

i=0 clear remainder partial quotient = dividend

compute sign of quotient

subtract divisor from partial remainder

Yes result > 0?

No partial quotient LSb = 1

No negate dividend restore partial quotient, LSb = 0

Yes result > 0? i=0 clear remainder partial quotient = dividend

restore partial quotient, LSb = 0

restore partial quotient, LSb = 0

Return and indicate no error

1996 Microchip Technology Inc.

1996 Microchip Technology Inc.

macro 2+15+625+24+2+726+25+2+727+26+2+628+27+8 = 822 clks 2+76+5+1+76+5+1+76+5+2+66+5+6 = 192 clks DM: 17

PM: 68+6+722+823+824+725+9 = 788

PM: 69+6+821+822+823+824 = 795

PM: 68+6+722+823+824+725+9 = 788