Code No: R05220202 Set No.

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II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
LINEAR AND DIGITAL IC APPLICATONS
( Common to Electrical & Electronic Engineering and Instrumentation &
Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) What is an Op-amp? Why it is called so?

(b) Explain the parameters that should be considered for ac and dc applications
of an Op-amp?
(c) Draw and explain the two open loop Op-amp configurations with neat circuit
diagram. [4+5+7]
2. (a) What is an instrumentation amplifier? Explain and list any three applications
of the instrumentation amplifier.
(b) Describe the application of Op-amp combines with a PN junction diode.[10+6]
3. (a) Draw the I order/II order band pass filter circuit with its frequency response
curve. Explain its working.
(b) Derive the expression for the transfer function of second order High pass filter.
[8+8]
4. (a) Draw the dc voltage versus phase difference characteristic of balanced modu-
lator phase detector of a PLL indicating all important regions.
(b) Draw the dc out put voltage of VCO versus frequency characteristic of a PLL
indicating the capture and lock range clearly.
(c) State the relationship between lock range and capture range through a math-
ematical expression. [6+6+4]
5. (a) List important specifications and characteristics of a monolithic Digital to
Analog converter IC MC1408.
(b) Explain the operation of an 8-bit tracking type Analog to Digital converter.
(c) Compare the conversion times and efficiencies of 8-bit tracking type and suc-
cessive approximation type Analog to Digital converters. [5+7+4]
6. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three
parts with the help of functional operation?
(b) List out TTL families and compare them with reference to propagation delay,
power consumption, speed-power product and low level input current? [8+8]
7. (a) Using two 74×138 decoders design a 4 to 16 decoder?
(b) Design a CMOS transistor circuit that has the functional behavior F (Z) =
(A + B̄)(B + C). [8+8]

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Code No: R05220202 Set No. 1
8. (a) Design a conversion circuit to convert a SR flip-flop to J-K flip-flop?
(b) Write short notes on parallel in serial out shift register. [8+8]

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Code No: R05220202 Set No. 2
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
LINEAR AND DIGITAL IC APPLICATONS
( Common to Electrical & Electronic Engineering and Instrumentation &
Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) What are the three factors that affect the electrical parameters of an Op-amp.
(b) Derive the expression for CMRR for the first stage differential amplifier.
[8+8]

2. (a) Write short notes on non inverting comparator.

(b) For the given (figure 2b) inverting Schmitt trigger, calculate its higher and
lower trigger levels. [8+8]

Figure 2b
3. Write a short notes on any two

(a) Derive the transfer function of second order low pass filter.
(b) Derive the transfer function of second order high pass filter.
(c) Derive the transfer function of second order band pass filter. [16]

4. (a) Design a 555 Astable multivibrator to operate at 10 KHz with 40% duty cycle.
(b) Explain in which the 555 timer can be used as Astable multivibrator. [8+8]

5. (a) Give the classification of ADCs? Explain in detail basic block diagram of
ADC.
(b) What is quantization error?
(c) Explain R-2R type DAC. [7+2+7]

6. (a) Draw the circuit of two input NAND gate with totem-pole output and do the
static analysis when output is HIGH & Output is low.
(b) Explain why two totem pole outputs can’t be tied together.
(c) With neat circuit explain the concept of open collector O/P with pull-up.
resistor. [6+6+4]

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Code No: R05220202 Set No. 2
7. (a) What is multiplexer? Draw the logic diagram of 4 to 1 line multiplexer?
(b) Design half adder using NAND gates only? [8+8]

8. (a) Design a modulo-100 counter using two 74×163 binary counters?

(b) Design an 8-bit parallel-in and serial-out shift register? Explain the operation
of the above shift register with the help of timing waveforms? [8+8]

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Code No: R05220202 Set No. 3
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
LINEAR AND DIGITAL IC APPLICATONS
( Common to Electrical & Electronic Engineering and Instrumentation &
Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Broadly classify the integrated circuits for a wide range of applications.
(b) What is a practical Op-amp? Draw its equivalent circuit.
(c) In an Op-amp, V2 = 0 (inverting terminal input). What is the voltage at V1
(non-inverting terminal input) for an output of 5V if AOL = 50000. [6+6+4]

2. (a) Explain how Op-amp used as a integrator and differentiator.

(b) With the help of a neat circuit diagram, explain the operation of instrumen-
tation amplifier of obtain the expression for its o/p voltage VO . [8+8]

3. Write a short notes on any two

(a) Derive the transfer function of second order low pass filter.
(b) Derive the transfer function of second order high pass filter.
(c) Derive the transfer function of second order band pass filter. [16]

4. (a) Explain the operation of Monostable multivibrator using 555 timer. Derive
the expression of time delay of a Monostable multivibrator using 555 timer.
(b) Design a Monostable multivibrator using 555 timer to produce a pulse width
of 100 ms. [10+6]

5. (a) Explain in detail the following characteristics of Analog to Digital converter

i. Resolution.
ii. Quantization error.
(b) An 8 bit ADC is capable of accepting an input unipolar (positive values only)
voltage 0 to 10V.
i. What is the minimum value of 1 LSB.
ii. What is the digital output code if the applied input voltage is 5.4V?[8+8]

6. List out standard TTL Characteristics and explain them briefly with necessary
diagrams. [16]

7. (a) Using two 74×138 decoders design a 4 to 16 decoder?

(b) Design a CMOS transistor circuit that has the functional behavior F (Z) =
(A + B̄)(B + C). [8+8]

8. (a) Design a 3-bit binary synchronous counter.

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Code No: R05220202 Set No. 3
(b) Explain the working of 4 bit up / down synchronous counter. [8+8]

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Code No: R05220202 Set No. 4
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
LINEAR AND DIGITAL IC APPLICATONS
( Common to Electrical & Electronic Engineering and Instrumentation &
Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Give the design procedure of a compensating network for an Op-amp which
uses ± 10V supply voltages. Assume necessary data.
(b) In the circuit of figure 1, R1 =100 Ω, RF = 4.7K Ω, CMRR=90 db. If the
amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate
the amplitude of the common-mode input voltage Vcm . [8+8]

Figure 1
2. (a) Classify the types of Op-amp based multipliers. How a multiplier can be used
to
i. Double the incoming frequency.
ii. Detect the phase angle of a signal.
(b) Design a subtractor in non inverting configuration. [8+8]

3. (a) Design a II order Butterworth Low-pass filter for a cut off frequency of 1KHz
and for a given normalized polynomial of S 2 +1.414S+1. Assume necessary
data.
(b) In the above circuit given (figure 3(b)ii) if the integrator components are
R1 =120 KΩ and C1 = 0.01µF,R3 = 6.8 KΩ R2 = 1.2KΩ, determine
i. Peak-to-peak triangular output amplitude.
ii. The frequency of triangular wave. [8+8]

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Code No: R05220202 Set No. 4

Figure 3(b)ii
4. Explain the functional block diagram of PLL emphasizing the importance of capture
range and Lock range. [16]

5. (a) Draw the block diagram for a 2-bit parallel-comparator A/D converter and
explain the operation of the system.
(b) Draw a schematic diagram of a ladder network D/A converter. Explain the
operation of the converter. [8+8]

6. (a) Explain the following terms with reference to TTL gate?

i. Logic levels.
ii. DC Noise margin.
iii. Low-state unit load.
iv. High-state fan out.
(b) List out TTL families and compare them with reference to propagation delay,
power consumption, speed-power product and low level input current? [8+8]

7. (a) Design a serial binary adder?

(b) Design a full subtractor with logic gates? [8+8]

8. (a) Explain the internal structure of 64K×1 DRAM? With the help of timing
waveforms discuss DRAM access?
(b) Design an 8-bit synchronous binary counter with serial enable control? [8+8]

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