BENEFITS OF VLSI BOUNDARY-SCAN TESTING

Chapter 1

Introduction
Advances in semiconductor technology have pushed integrated circuits (ICs) towards smaller physical dimensions, faster speeds, and more complex designs within a single device. The lack of physical access to the desired test points has turned into a serious issue. Test engineers are faced with the grueling task of continuously searching for ways to test these devices in the most efficient manner, yet having to maintain testing cost as low as possible. Boundary-scan was developed by a group of engineers to resolve the issues associated with traditional testing techniques, while maintaining or increasing the necessary fault coveraoG. 1.1 Conventional Testing Methods In the early days of ICs, the devices were relative bulky and were tested by engineers using readily available lab bench equipment. As devices grew smaller and more complex, it quickly became apparent that testing devices in large numbers would be time consuming and financially expensive without some sort of automated test equipment (ATE). In an attempt to standardize the test environment, initial ATE systems allocated test resources configured into an adapter-type box that could be connected to the device under test (dut). The edge-connected tester was a great step into ATE systems, but tester programming was the next problem. This lead to the creation of an entire research field dedicated to digital test generation. The logic simulator became the most popular solution for digital test generation. It allowed the engineer to create an abstract model of a circuit, and then apply stimulus test patterns or vectors, and the model produced the output or response vectors. If the logic simulator was capable of injecting failure mechanisms or faults into the model, then the simulator exposed the differences in how the circuit responded to the stimulus. A fault was considered "detected," if it was visible at the edge-connector pin. The challenge arose when knowledge of how the circuit worked from the design engineer(s) was not readily available. Thus, test engineers, responsible for creating the appropriate test program(s), became overwhelmed in trvina to develon a test nrooram for a comnlex desinn of circuits has increased, the capacity of existing simulators to quickly create and process accurate models has decreased [1].
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING For circuit boards, in-circuit testing (ICT), or bed-of-nails, was developed to resolve the limitations of logic simulators. ICT divides complex circuits into individual, stand-alone components, which reduces test time significantly, since tests can be stored in a library for later reference. ICT encountered problems as devices began incorporating dual-line, through-holemounted packages to utilize silicon area as much as possible. The bed-of-nails were simply arranged to target the IC pins themselves. However, ICT again faced limitations when Surface Mount Technology caused boards not to have any through-hole access to target the pins. Unless In-Circuit test access is part of the design criterion, some board-level signals may not appear on the bottom side of the board [2]. A solution is necessary to address the problems associated with the increasing lack of physical access to target pins. In addition, the initial cost of investing for an ATE system is very expensive, so testers are expected to operate for long periods before replacement. As a result, most testers have components slower than the device under test (dut) used to perform the testing. This paper addresses the benefits of Boundary-Scan as a Design-ForTest implementation for cost and test time reduction tool. Boundary-scan excels in facilitating DC parametric testing and interconnection testing of the device under test. Chapter II presents the historical background, advantages, and disadvantages of boundary-scan. The TAP controller's states and the boundaryscan instructions are explained in Chapter III. Chapter IV describes parametric tests and the purpose for each test. Chapter V discusses how boundary-scan may be implemented and potential results. Chapter VI contains conclusions and look ahead for boundary-scan testing.

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Chapter 2 IEEE 1149.1 STANDARD: "TEST ACCESS PORT AND BOUNDARY-SCAN ARCHITECTURE"
2.1 WhvTest Testing in the semiconductor industry is very Important because it can literally be the difference between success and failure in the semiconductor market. Although technology pushes towards better semiconductor devices, the ability to verify design and operation is also affected. Inevitably, increased complexity and lack of physical access to circuitry using traditional testing methods has made for expensive and time-consuming testing. Manufacturers, therefore, are forced to search for ways to reduce testing costs. A manufacturer could choose to lower their test coverage, but this may endanger their technical reputation to consumers. In such a competitive market, a manufacturer would not remain competitive poorly tested products [3].

According to estimates, the cost of finding a failure from one level of complexity to the next increases by a factor of ten using conventional methods, as shown in Table 2.1 [4]. It is crucial to

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING find innovative methods that impact all the phases of a product's life, from the design stage to the user's service. Products must be tested as quickly and efficiently as possible to ensure the product will not have a delayed market introduction. Failure to provide quality products would surely lead to lower profit margins and costumer dissatisfaction. 2.2 Design-for-Test In order to test any device, it is necessary to have the ability to control the product and to observe the output response. The device must enter into a known state, before input data can be supplied. The output is observed and compared to ensure the device performs as it was designed and manufactured. If any of these aspects cannot be obtained, then there is no way to determine, with confidence, if the product performs as it should. Design-for-test (DFT) utilizes rules and techniques in the design of a product to facilitate testing and it has become a popular approach to test cost reduction. The main objectives of DFT are to manage the product's

complexity,minimize product design and development time, and over time to reduce the cost of manufacturing the product. DFT further helps reduce costs associated with testing by simplifying test programs, since designs are structured by reusable methodologies. Other cost savings include reduction in test vector size, reduction of test time, and eliminating or limiting the need for expensive, state-ofthe- art ATE systems [5]. 2.3 Basic Boundarv-Scan Architecture In 1986, several engineers from different areas in North America and Europe came together to form an international group called the Joint Test Action Group (JTAG) for the purpose of developing a standard to resolve the issues of traditional testing techniques. In February of 1990, JTAG submitted a proposal to the IEEE Standard Boards, which was accepted and marked as IEEE Std. 1149.1 [6]. Boundary-scan provides the means to test products more efficiently, while maintaining or increasing the required fault coverage to ensure good quality.

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING

The IEEE standard requires four pins, to control and observe the device under test (DUT) [7]. First, the Test Clock (TCK) and Test Mode Select (TMS) are two input pins required to drive boundary-scan. As shown in Figure 2.1 with an asterisk, the reset pin, Test Reset (TRST), is optional, since the state machine is put into a reset state when TMS is held high for five TCK cycles. The other two pins, Test Data In (TDI) and Test Data Out (TDO) allow data to be shifted serially into and out of the 10. All four or five pins form the Test Access Port (TAP), which may only be used for boundary-scan functions and may not be shared with any other function [6]. The TAP controller, shown in Figure 2.1, is a finite state machine with a state diagram comprised of sixteen states. A transition between states occurs only on the rising edge of TCK, or if TRST pin exists, then a reset will occur if TRST is asserted. While the TAP controller is in the reset state, all test logic is reset and the device performs its normal operation. The instruction register (IR) is a serial-In/serial-out shift register. The contents of the register are stored in a parallel output latch and can only be changed by the TAP controller. In addition, the boundary-scan architecture
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING contains the boundary-scan register, a bypass register, and allows for an optional device identification (ID) register, if desired. Data from TDI can be moved to the TDO through the bypass register, which is only one bit wide, in one pulse of TCK. The ID register is a 32- blt parallel-in/serial-out shift register and contains data that identifies the manufacturer's name, part number, and version number when the TAP controller is in Capture-DR (Data Register) state. The normal operation of the circuitry is not affected when either the bypass or ID registers are in use. The device's input and output pins are connected to the core logic's input and output pins via boundary-scan cells. Figure 2.2 depicts an example of the boundary-scan cells when interconnected from a continuous shift register around the border of the device known as the boundary-scan register. This boundaryscan path is used to shift, apply, or capture test data.

During normal operation of the device, the boundary-scan cells do not interfere with the flow of data. Data input passes directly to the circuit and the corresponding response can be directly observed at the output pins. However, when the scan mode is selected, the test patterns are shifted through the TDI pin and the corresponding response may be observed at the TDO pin. Therefore, the control and observation of the target pins can be achieved despite the lack of the physical access [7].

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING 2.4 Advantages and Disadvantages of Boundarv-Scan Some manufacturers hesitate to embrace IEEE 1149.1 standard and remain skeptical about the overall benefits resulting from incorporating boundaryscan into their product's design. One reason is the initial cost of including boundary-scan impacts the product's budget with additional work and design complexity. The possibility of potential yield losses from placing active circuitry in formerly vacant silicon real estate also discourages manufacturers to include boundary-scan [1]. The extra circuitry will cause additional gate delays, which could affect device specifications. In contrast, implementing boundary-scan into a design has several benefits. Boundary-scan provides the most benefit in its implementation for a standard test access method, i.e. the TAP, by allowing access to device-internal test facilities other than those for boundaryscan. Boundary-scan in conjunction with device-internal scan effectively creates a full-scan path. In this approach, every storage element, such as latches and flip-flops, is replaced with a boundary-scan cell. A partial-scan, only a select number are replaced, is sometimes more appropriate when device area and performance cannot be a trade-off for increased fault coverage. Boundary-scan and internal scan can be implemented so that both could be used at the same time allowing for the reduction of required signals to only the four TAP signals. The boundary-scan register could therefore easily control and observe the inputs and outputs to the core logic. Another testability technique for reducing test costs and test time is Built-I Self Test (BIST). BIST uses on-chip stimulus generators and monitor responses to eliminate the need for any test pattern generation. Therefore, BIST could be used with boundary-scan and internal scan as aquick method for pass or fail testing while the scan path is used for debug and failure diagnosis. Because boundary-scan was designed for board level testing, devices can easily be isolated when multiple devices or multiple boards are connected in series or parallel chains. Again, the four TAP signals can be used to test the devices and/or boards. In addition, the life of the tester is extended because the need to access every test point is reduced to the four TAP signals, input pins, and output pins. In fact, it allows for the cost of test to be reduced in many levels, including tester complexity, tester time, and tester requirements, such as pins, memory, and pin timing. Boundary-scan allows for compatibility with other vendors, since it is an IEEE standard. Furthermore, the benefits quickly compensate for the initial costs of the learning curve and implementing boundary-scan into a design. Implementing boundary-scan into a design impacts testing from the device level to the system level to the field level.
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING

Chapter 3

THE TAP CONTROLLER STATES AND BOUNDARY-SCAN INSTRUCTIONS

The TAP controller is probably the most crucial part to boundary-scan testing. It allows the control and manipulation of all the data and instruction registers. Plus it is capable of controlling the signal pins as necessary to perform the different tests. As before, the TAP controller is a state machine with sixteen possible states and its transition diagram is shown in Figure 3.1. The state machine's transition is dependent on TMS, which must be set up before the rising edge of TCK. Mr(Test-Logic-Resey'

Figure 3.1. The TAP Controller's State Diagram. [6]

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3.1 TAP Controller's Sixteen States The TAP controller navigates through all the states in order to perform DC parametric testing, for example, using boundary-scan testing. The state diagram shown in Figure 4.1 is divided into to two columns, the data column and the instruction column. These two columns are in fact very similar in functionality, but differ in the registers it targets. The different states of the controller will be described in detail in order to understand how boundary-scan testing may be used to perform DC parametric testing. The IEEE standard defines the function of each controller state [6]. 3.1.1 Test-Logic-Reset When TMS is held high for at least five rising edges of TCK, or if TRST (optional) is asserted, the controller enters the Test-Logic-Reset no matter what the state of the controller. The instruction register is initialized to contain the optional IDCODE instruction, if implemented, or the required BYPASS instruction (both instructions are described later). The test logic is therefore disabled to allow the 10 logic to continue normal undisturbed operation. The controller remains in this state as long as TMS is held high. If TMS is low, the controller moves into Run Test/ldle at the next rising edge of TCK and the test logic remains inactive, since the current instruction is set up with the IDCODE or BYPASS instruction. 3.1.2 Run-Test/Idle The IEEE standard describes the Run-Test/ldle state as a controller state between scan operations. As long as TMS is held low, the controller will remain in this state. When certain instructions are present, this will cause activity in the selected test logic to occur. For instructions that do not cause functions to execute in this state, all selected boundary-scan cells retain their previous state. The state machine controller moves to the SELECT-DR-SCAN state when TMS is high and the rising edge of TCK is applied. 3.1.3 Select-DR-Scan The Select-DR-Scan is a temporary controller state, meaning that the controller will exit this state on the next rising edge of TCK. In this state, all the test data registers targeted by the current instruction shall retain their previous state. Also, the instruction does not change while the controller is in this state. A decision must be made, by the next rising edge of TCK, whether to enter into the data column or continue to the instruction column. While in this state, if TMS is
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING asserted low, the controller proceeds towards the Capture-DR state, but if TMS is held high the controller moves into the Select-IR-Scan state. 3.1.4 Select-IR-Scan This state is also a temporary state and all test data registers selected by the loaded instruction must retain their previous state. As with Select-DR-Scan, the instruction does not change in this state. Again, a decision must be made by the next rising edge of TCK, whether to proceed into the instruction column or enter into the Test-Logic-Reset state. If TMS is high, then the controller will move into the reset state, else the controller will continue into the Capture-IR state, if TMS is low. 3.1.5 Capture-DR During the Capture-DR state and depending on the current instruction, data may be paralle loaded (read) into test data registers selected on the rising edge of TCK. Furthermore, the selected test data register retains its previous state unchanged in the event that it does not have a parallel input. The instruction does not change while the controller is in this state. At the next rising edge of TCK, the controller will proceed into Shift-DR, if TMS is held low, othen/vise, if TMS is high, the controller will enter Exitl-DR state. 3.1.6 Shift-DR Depending on the current instruction, the test data registers are connectedbetween TDI and TDO and shift data one stage towards TDO on each rising edge of TCK, while the controller is in the Shift-DR state. Test data registers, not targeted by the current instruction, retain their previous state. During a serial shift, new data may be inserted into scan path via TDI. The output driver for the TDO pin is activated, remaining active until the falling edge of TCK in the Exitl- DR state. On the other hand, the TDO driver is held at a high impedance state (off) at all other times. Once entered into this state, the controller remains in Shift-DR while TMS is held low and enters the next state, Exitl-DR, if TMS is high, when the next rising edge of TCK occurs. It is important to note, as shown in Figure 4.1, that it is possible to return to Shift-DR by transitioning through the Exitl-DR, Pause-DR, and Exit2-DR states. A helpful feature, if, for example, the ATE does not have sufficient memory to load an entire instruction or test sequence in one burst, is that the controller can enter the Pause-DR state, while the next portion of bits is set up.

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING 3.1.7 Exitl-DR The controller, while in Exitl-DR, must choose either to enter the Pause- DR state or to enter the Update-Dr. Holding TMS high, causes the controller to move into the Update-DR state and effectively terminates the scanning process. If TMS is low, the controller enters the Pause-DR state. 3.1.8 Pause-DR The serial shifting of data through the scan path is suspended, while the controller is in Pause DR state. While TMS is held low, the controller remains in Pause-DR and enters Exit2-DR, If TMS is asserted high. This state may be used to temporarily halt operations, while the ATE reloads tester memory, for example. The instruction does not change in this state. 3.1.9 Exit2-DR Exit2-DR is another temporary controller state, where all targeted test data registers keep their previous state unchanged. Holding TMS high will cause the scanning process to terminate and moves the controller Into the Update-DR state. If TMS is held low and a rising edge of TCK is applied, the controller reenters the Shift-DR state. 3.1.10 Update-DR In the Update-DR state, data contained in the boundary-scan cells is latched (written) into the parallel output portion on the falling edge of TCK. The data contained in the parallel output of the test data register will only change in this state. In some cases, as required by the instruction, some test data registers may be supplied with a latched parallel output to avoid changing their state, while data is shifted through the scan path. When in this state and a rising edge of TCK occur, the controller proceeds into the Select-DR-Scan state, if TMS Is high, or the Run Test/ldle, if TMS is low. 3.1.11 Capture-IR On the rising edge of TCK, the shift portion of the instruction register loads a set value pattern during the Capture-IR state. In addition, design-specific data can be loaded into shift-register stages, but do not require fixed values. The instruction does not change during this state and the test data register, selected by the current instruction, retains the previous state unchanged. On the rising edge of TCK, the controller may enter the Exitl-IR, if TMS is high or may enter the ShiftIR state, if TMS is low.

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING 3.1.12 Shift-IR In this state, the shift portion of the instruction register is connected in serial between the TDI and TDO pins. Data is shifted one stage towards the TDO pin on every rising edge of TCK. The instruction does not change during this state and test data registers selected by the current instruction retain their previous state unchanged. The controller enters either the Exit1-IR state or remains In the Shift-IR, if TMS is high or low, respectively. 3.1.13 Exitl-IR Once entered, the controller will exit this state on the next rising edge of TCK, since it is a temporary controller state. If TMS is low, the controller will move into the Pause-IR state. If TMS is high, the controller will enter the Update- IR state, which terminates the scanning process. The test data register selected by the current instruction, which remains unaltered, will retain their previous state unchanged in this state. 3.1.14 Pause-IR During the Pause-IR state, the shifting of the instruction register is suspended. The instruction does not change in this state, the selected test data registers also retain their previous state, and the instruction register retains its state, as well. If TMS is held low, the controller loops back to this state, but moves into the Exit2-IR state otherwise. 3.1.15 Exit2-IR While in this temporary state, the scanning process for the instruction column is concluded and the controller enters the Update-IR, if TMS is high. If TMS is low, the controller re-enters the Shift-IR state, restarting the shifting process. Again, test data registers that were targets of the current instruction will keep their previous state and the instruction register retains its current state. 3.1.16 Update-IR In this state, the new data, already in the shift portion of the instruction register is latched onto its parallel output on the falling edge of TCK. Thus, the new instruction becomes the current one and the previous states of the test data registers selected by the previous instruction are kept. So, the controller can enter the Select-DR-Scan from this state, if TMS is high, or transitions into the Run-Test/ldle state, if TMS is low. Again, the TAP controller is a state machine with a finite number of states that allow the test engineer to control and observe the device under test through boundary-scan. With a better understanding of the TAP controller, through the description of the controller states, the instructions provided by the IEEE standard for boundary-scan testing can be
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING presented. The standard defines a number of instructions as mandatory, but also provides other optional instructions, that designers may or may not wish to implement with their design [6]. 3.2 Boundary-Scan Instructions Two types of instructions are used for boundary-scan testing. One type, defined by the IEEE standard as non-evasive, may be used during normal operation of the device's on-chip operation without interference. The instructions required by the standard, under this type, are BYPASS and SAMPLE/PRELOAD. IDCODE and USERCODE are optional normal mode instructions. The second type, known as pin-permission instructions, permits the boundary-scan logic to execute a number of functions and instructions, including those under the nonevasive mode. The instructions under this type are EXTEST, INTEST, RUNBIST, CLAMP, and HIGHZ. These are all optional instructions, except for EXTEST. 3.2.1 Normal Mode Instructions When the BYPASS instruction is executed, it targets the bypass register connecting it between TDI and TDO as shown in Figure 3.2. By creating the scan path through the bypass register, considerable time Is saved, since data from TDI to TDO has only to travel through the one-bit register. For this reason, the device can continue normal operations without being disturbed. The bypass register is also parallel loaded with a logic zero, when the TAP controller passes through the Capture-DR state, initializing the register with known data. The IEEE standard requires that a bit pattern entirely composed of logic ones in the Instruction Register must map to the BYPASS Instruction.

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING

The BYPASS Instruction. [8]

The sample part of SAMPLE/PRELOAD targets the boundary-scan register. I.e., all test data registers or boundary-scan cells, and is connected between the TDI and TDO pins. The boundary-scan register captures (reads) data from the device's input and output pins, which can be examined from TDO via serial shifting. During a preload, selected test data registers can be set up with data prior to executing an instruction, if so desired. During this instruction, the device's logic is not disconnect from the IC pins, so normal operation can continue without interference. Figure 3.3 shows how the boundary-scan architecture is configured for the SAMPLE/PRELOAD instruction. TDO

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BENEFITS OF VLSI BOUNDARY-SCAN TESTING

Figure 3.3. The SAMPLE/PRELOAD Instruction. [8]

The optional instructions, IDCODE and USERCODE allow the device to continue in normal operation, while it targets the Device Identification Register. The IEEE standard defines the device identification register as a 32-bit shift register, which contains Information regarding the IC manufacturer, device type, and version code. A scan process can be initiated to serially shift the data out TDO, after the TAP controller enters the Test-Logic-Reset state or a power-up of the device. The USERCODE causes the device identification register to capture user-defined information about the IC. Similar to the Bypass instruction configuration of the boundary-scan architecture in Figure 3.2, these instructions target the device identification register, instead of the bypass register. 3.2.2 Test Mode Instructions The EXTEST instruction is the only test mode instruction required by the IEEE standard. This instruction permits the observation of the interconnections between the boundary-scan cells and some other access point whether it is another device or the ATE. The device is placed into an external boundary-test mode and the boundary-scan register is connected between TDI and TDO
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING as shown in Figure 3.4, when EXTEST is executed. During this instruction, the inputs of the device can be readily captured (Capture-DR) and the boundaryscan register can control the signal outputs. Once the test data registers contain the data, it can be examined by shifting (Shift DR) via the scan path and the TDO pin, but new data can be serially shifted from TDI in preparation of the next test, if necessary. The new data will become effective when the controller passes through the Update-DR state.

Figure. The EXTEST Instruction. [8] Unlike the previous instruction, the INTEST instruction is optional placing the device in an internal boundary-test mode. The boundary-scan register is selected and connected between the TDI and TDO pins as presented by Figure 3.5. The boundary-scan register is also connected to the outputs of the IC logic. The test pattern is applied when the controller during the Update-DR state and captures data during the Capture-DR state, which is then shifted out TDO during the Shift-DR state. However, it is also possible to observe the output response via the parallel output of the boundary-scan ceil at the device's output signal pin

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The INTEST Instruction. [8] As shown in Figure 3.6, the RUNBIST instruction is optional and executes any IC self-test logic providing a quick method of determining if the device is operational. The instruction selects the user-defined test data register and connects it between TDI and TDO. The actual self-test is executed when the controller is in the Run-Test/ldle state and the output data is capture by the targeted test data register during the Capture-DR state. As with other instructions, the results can be shifted out TDO for examination.

The RUNBIST Instruction. [8] CLAMP is an optional instruction that connects the bypass register between the TDI and TDO pins, in order to shorten the scan path. In Figure 3.7, the configuration of the boundary-scan by the CLAMP instruction is depicted. The output and bi-directional pins are placed under the
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING control of the boundaryscan register, but the contents of the selected output test data registers can be set up with the SAMPLE/PRELOAD instruction. Therefore, this would "clamp" the value preloaded and the output test data registers would retain the value unchanged. This is particularly beneficial if two or more devices are in a boundary-scan chain. Suppose, the second device in the chain is the DUT and the output pins of the first devices are connected to the input pins of the second device. The input pins of the second device can be driven with the CLAMP instruction on the first device. In the event that is necessary to serially shift data to the second device, the data can be shifted through the bypass register, and not through the entire boundary-scan path to reach the second device.

The HIGHZ Instruction. [8] In addition to these instructions, the designer may add user-defined instructions and registers, extending the scope and architecture of boundaryscan The user-defined instruction(s) can be public or private. If the instruction(s) are considered public, then it must have proper documentation, else if it is private, no documentation, other than the bit pattern is required.

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Chapter 4
DC PARAMETRIC TESTS Before discussing the implementation of boundary-scan to perform DC parametric tests, these tests will be described. DC parametric tests are stati tests; i.e., the input signals of the device are not toggling. Such tests could include the following: Diode, Power Supply Shorts, Input Voltage, Output Voltage, Input Current Leakage, Output Current Leakage, and Leakage tests . 4.1 Diode Test (Continuitv/Pin-to-Pin) The diode test consists of two tests, continuity test and pin-to-pin test. The diode test verifies that proper contact is made to all the signal pins and that no signal pin has a low resistive short to another signal pin, power supply pin, or ground pin. The continuity test verifies that all DUT signal pins make good contact to the tester channels. This test also verifies the presence of the Electrostatic Discharge (ESD) diode connected to each input and output signal pin. 4.2 Power Suppiv Short Test The supply shorts test looks for a low resistive pathfrom the primary power supply (Vdd) pin to the secondary power supply (Vss) pin. The secondary power supply pins are connected to ground, while the primary power supply pins are connected to the power supply or power supplies. All other pins are left open or disconnected, and the current is measure from the voltage supplies and compared to a determined limit. Only the devices with Vdd to Vss short(s), or near shorts will fail, if the limit is properly chosen [10]. 4.3 Input Voltage Test (VIHA/IL) The VIH/VIL test is performed to verify that the DUT properly responds to various input voltage levels defined by the data specifications under steady state conditions. In this case, the DUT is driven by another device. It is important that the DUT is able to process the proper logic, or risk having unreliable operation. First, VIL is the maximum voltage that the DUT is guaranteed to process as logic zero and VIH is the minimum voltage that DUT is guaranteed to process as logic one. 4.4 Output Voltace Test (VOHA/OL) The output voltage is tested to ensure the voltage level is below the VOL level or above the VOH level. Forcing a specified current load and measuring the voltage drive level of the output pin for the specified logic level performs VOH/VOL test. The test specification defines the maximum current (lOL) that the output pin can handle while having a voltage equal or below VOL.
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING Essentially, VOL test measures how well a DUT output pin conducts current when it Is logic zero. On the other hand, VOH test forces an lOH current and the voltage is measured. This test also verifies the resistance of the output pin. It is important to point out that the DUT must be preconditioned to ensure that the output pins are at logic one [10]. 4.5 Input Current Leakaoe Test (IIH/IIL) The Input Leakage test, or IIH/IIL test, ensures that the DUT can be driven to logic low and logic high without consuming more current that the specified amount by the data specifications. The IIH/IIL test is usually tested in parallel by performing the IIH test on the even pins while the IIL test is performed on the odd pins. The process is reserved in order to test all the input pins for current 30 leakage. The IIL and IIH test measures the resistance from an input pin to Vdd and Vss, respectively. By measuring the resistance of the input pins, the amount of current drawn by the DUT can be verified so that it does not exceed the specifications. This test also serves as a good method of detecting any process defects [9]. 4.6 Output Current Leakage Test (lOH/IOL) Any output pin of the DUT can potentially drive one or more devices. Therefore, the purpose of this test is to ensure that the DUT provides sufficient output current at a specified output voltage. The output current tests measure the current amount on the output pin of the DUT when the output pin is at a specified logic level. The DUT must have the ability to sink enough current while providing the minimum voltage to the other device(s) [9]. 4.7 Leakage Test The leakage test verifies the bi-directional pins are in input mode and have current leakage within an acceptable level. In order to minimize power consumption and prevent unreliable operation, the DUT must not require an excessive amount of current to drive a pin to a high voltage level. This test is also normally performed in parallel by applying the specified VIL or VIH level and measuring the current flow into the pin [9]. Boundary-scan testing extends the usefulness of the ICT by providing a solution to overcome the inherent limitations of In-circuit testing. The detection of open and shorts, which may have been caused by solder problems or bent pins during manufacturing, between devices and boards are easily found with the use

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Chapter 5
BENEFIT OF BOUNDARY-SCAN IN DC PARAMETRIC TESTING The implementation of the boundary-scan architecture can vary between vendors and devices. Although the greatest advantage Is at the board level, boundary-scan can be exploited and used in device level testing. Most dc parametric tests may be accomplished using the required and optional instructions provided by the boundary-scan standard. However, the optional instructions available may be useful in conducting certain dc parametric tests. As previously mentioned, designers may opt to define private or public instructions to further facilitate boundary-scan based tests, if desired. In order to simplify the discussion, only the dc parametric tests in which boundary-scan can be used to facilitate testing will be addressed. The steps to conduct boundary scan testing for Input and Output Voltage and Input Current testing will be explained. The benefits of boundary-scan will also be presented as it applies to the individual dc parametric tests. 5.1 Boundarv-Scan VIH/VIL Testing The flowchart for conducting a boundary-scan VIH/VIL test is shown in Figure 5.1. The device is set into test mode when the TAP controller enters the Test-Logic-Reset state. As with any type of testing, the DUT is placed into a safe state as to prevent any bus conflicts. The second step is to load the instruction register with SAMPLE/PRELOAD and set all bi-directional pins into input mode. The fourth step, after the EXTEST Instruction is loaded into the instruction register, is to parallel apply the first test pattern, for example, VIH. At this point, the TAP controller is moved into the Capture-DR state, so that the response may be read. Once the response Is captured at each boundary-scan cell, the data is serially scanned (shifted) for examination via the TDO pin. The next test pattern, VIL, Is parallel applied to the input pins and the response is again captured. Finally, the data is scanned out for examination and the TAP controller is transitioned to the Test-Logic-Reset state, ready to execute another test.

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Using boundary-scan to perform input voltage testing offers some benefits over other test methodology, such as an "AND-tree" configuration. The AND-tree structure is designed to allow verification of input switching threshold levels via serially attaching each Input with AND gates as seen in Figure 5.2. This configuration may, in fact, use other logic gates to provide design variations, but they are usually still referred to as an AND-tree. A single output only pin is chosen and dedicated as the observation pin for the AND-tree. The primary function of the andtree configuration is to verify VIH and VIL voltage levels during testing under steady state conditions. The AND-tree allows the transients from the switching I/O output buffer cells to
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING settle before the measurement is taken, since the VIH/VIL test Is normally performed as a functional test. Although this approach does reduce test time, each input pin must still be tested individually to ensure that there are no stuck-at faults. This may cause a substantial amount of test time, since the time to test every pin will increase as the number of signal pins on the device increases. On the other hand, boundary-scan, which is unaffected by the number of signal pins, allows all the input pins to be tested at the same time, therefore, providing an advantage over the AND-tree structure. 5.2 Boundary-Scan VOHA/OL Testing VOH/VOL testing is similar to VIH/VIL with a few exceptions. The TAP controller Is placed into the reset state and the DUT is put Into a safe state. The SAMPLE/PRELOAD instruction Is loaded into the instruction register. During this stage, all bi-directional pins are put into output mode, instead of input mode. The third step is to load EXTEST into the Instruction register. Unlike the input voltage test, the VOH test pattern is serially scanned into the boundary-scan register. The test pattern is applied when the TAP controller transitions through the Update-IR state. The response Is then read at every output pin via the ATE. Next, the VOL test pattern is serially scanned into the boundary-scan register. After the test pattern is applied, the response is then captured via the ATE. The TAP controller is finally transitioned to the Test-Logic- Reset state. Again, boundary-scan testing is beneficial in reducing test time in performing the Output Voltage test, because the number of test patterns required in testing the DUT is also reduced. Other test methodologies must execute a number of test patterns In order to precondition the device to set the output pins to the proper voltage levels. However, a test pattern is serially scanned into the boundary-scan register and the output response is observed at the outputs to determine If the DUT is functioning properly. Another advantage that could exist and may be explored is the possibility of testing the Input and Output Voltages of the DUT at the same time using boundary-scan. 5.3 Boundarv-Scan IIH/IIL Testing The TAP controller is initialized Into reset state placing the device into test mode and the device is placed into a safe state. For the input current leakage test, the bi-directional pins are set to input mode via the Sample/Preload instruction. The particular test pattern, say IIH/IIL test pattern, is parallel applied to the input pins. That is, the ATE forces the proper VIH voltage level on the even input pins, while forcing the proper VIL voltage level on the odd input pins.
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BENEFITS OF VLSI BOUNDARY-SCAN TESTING Consequently, any pin-to-pin leakage will be detected. The IIH/IIL currents are measured at each input pin via the ATE. The process is reversed, forcing the VIL on the even Input pins and VIH on the odd Input pins, and the input current is measured with the ATE. The TAP controller is returned to the reset state; thus, concluding the IIH/IIL test. For devices lacking boundary-scan, the Input Current Leakage test is normally divided In two tests in order to reduce test time. One tests input only pins and the other tests the bi-directional pins. The input only pins are easily tested for leakage without the need for test patterns to precondition the pins to input mode as is the case with bi-directional pins. In contrast, boundary-scan allows for all the input only pins and bi-directional pins, set to input mode, to be tested at the same time. Again, AND-tree and other methods may not be able to and sometimes cannot provide the means to test all desired pins at the same time. 5.4 Boundarv-Scan Benefits on PCI2050A For this discussion, the observation of the boundary-scan benefits was attempted using a peripheral component interconnect (PCI) device from Texas Instruments, Inc. The PCI2050A PCI-to-PCI Bridge provides a connection between two PCI buses and can be used to overcome the electrical loading limits of 10 devices per PCI bus [12]. Boundary-scan is one of the features offered on the PCI2050A. This device was chosen because it was desired to examine the benefits of boundary-scan in test time reduction. Up until now, nearly 55% of the total test time was spent on performing parametric testing and the remaining time is used to do functional testing. Nearly 70% of the time required performing parametric tests accounts for the Input Voltage and Current Leakage tests. Another observation, sometimes, up to 66% percent of the time was spent on the execution of functional patterns to precondition the device for the Input voltage and current leakage tests. On the other hand, the test time, when boundary-scan is used, was reduced significantly. The time required performing parametric tests account for nearly 15% of the total time as opposed to nearly 55% before. As mentioned before, boundary-scan reduces the number of test vectors and eliminates the need for functional test patterns to conduct Input Voltage and Current Leakage tests. A future work possibility is to explore the benefits of performing Input Voltage and Current Leakage test together in order to further reduce test time.

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CONCLUSIONS
In addition to its device level advantages, boundary-scan is of greater impact on VLSI testing at the board and system level and devices can still be tested via the TAP pins. A single serial scan chain or parallel scan chains can be used as desired to test multiple devices on a board or system. In fact, the implementations of dc parametric tests through boundary-scan are still applicable at the board and system level. A partial scan-chain can still be created on a board or system, in the event of having devices with and without boundary-scan. Other benefits of boundary-scan are derived from the fact that is an industry standard for testing. Therefore, the test patterns used for design verification, simulation, and tests are reusable. The benefit of boundary-scan is further extended when used in conjunction of other testing methodologies, such as BIST. Thus, boundary-scan provides the means for greater control and observation of the device. Whether it is a design of chip, board, or system, it is driven by costs, which could be calculated by the design time, device materials, fabrication costs, and personnel. Along with these costs, there exists the costs of testing, such as the ATE and software, but others factors may not be easily calculated, such as test time, debug time, and repairs. Designs with boundary-scan implemented benefit from having reduced testing hardware and software requirements, while still maintaining or improving test coverage of the device. Despite the overhead of implementing boundary-scan, such as design time, silicon real estate, and extra pins, the reductions of testing costs quickly make up for these costs and increase the overall profit of the device. Considering all the advantages and trade-offs, boundary-scan should be given serious consideration.

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REFERENCES
[1] Parker, Kenneth P. The Boundary-Scan Handbook, Kluwer Academic Publishers, Boston, 1992, pp. 1-47. [2] Scheiber, Stephen F. Building A Successful Board-Test Strategy, Butterworth-Heinemann, Newton, New Jersey, 1995, pp. 55-63. [3] Hurst, Stanley L. VLSI Testing digital and mixed analogue/digital techniques. The Institution of Electrical Engineers, London, 1998, p. 484. [4] Texas Instruments, Inc. "JTAG (IEEE 1149.1/P1149.4) Tutorial: Introductory," Website: http://www.ti.com/sc/docs/itag/seminar1.pdf [5] Crouch, Alfred L. Design-for-Test for Digital ICs and Embedded Core Systems, Prentice Hall PTR, Englewood Cliffs, New Jersey, 1999, p. 7. [6] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1993, IEEE Standards Board, New York, June 1993. [7] Lala, Parag K. Digital Circuit Testing with Testability, Academic Press, San Diego, 1997, p. 133. [8] Texas Instruments, Inc. Boundary-Scan Logic, Website: http://www.ti.com/sc/docs/genearal/logic/lit/bsl.pdf [9] Burns, Mark and Roberts, Gordon W. Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, New York, 2001, pp. 45-83. [10] Texas Instruments, Inc. ASIC Product Engineering Training Manual, Dallas, Texas, 2001.

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