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ABSTRACT

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx FPGA. FPGAs are the lowest power Devices available, making these FPGAs the perfect interface devices for many of today’s popular microcontrollers.

An interface to the 8051 microcontroller has been implemented in a XILINX FPGA. This design consists of a state machine that interprets the 8051 bus cycles to read and write data to a set of registers called a register file. A high-level block diagram is shown in Figure 1. Communication between the 8051 microcontroller and the application logic is accomplished through a register file. The 8051 microcontroller writes data to the register file to configure and control the application logic. The application logic writes status information and service requests to the microcontroller through the register file. Data transfer is also done through registers. Flags can be designed that denote when registers are empty and/or full depending on the application. The number of registers and their bit definitions are defined in general terms and should be customized for the application. Here in this project we r interfacing 8051 Microcontroller with XILINX FPGA. By interfacing this Microcontroller with FPGA we can able to increase the circuit abilities without complexity And the one of the best advantage is its Hardware Re configurability.

We can modify as well as upgrade the circuit behaviour by depending on the application.

CHAPTER 1

meaning that the CPU can work on only 8 bits of data at a time. A microcontroller has a CPU in addition to a fixed amount of RAM. but today it has largely been superseded by a vast range of enhanced devices with 8051-compatible processor cores that are manufactured by more than 20 independent manufacturers including Atmel. Infineon Technologies and Maxim Integrated Products. Flash and NV-RAM. 8051 is available in different memory types such as UV-EPROM. 1. I/O ports and a timer embedded all on a single chip. single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems. BASIC IDEA : Microprocessors and microcontrollers are widely used in embedded systems products.INTROUCTION AIM The main aim of this work is to design an 8051 Microcontroller interfacing and verifying its functional behavior with the help of its simulation results. RAM and number of I/O ports in microcontrollers makes them ideal for many applications in which cost and space are critical. It was popular in the 1980s and early 1990s. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. The fixed amount of on-chip ROM. 8051 is an 8-bit processor. ROM. Microcontroller is a programmable device. The Intel 8051 is Harvard architecture.3 OBJECTIVES INTERFACING : OF 8051 MICROCONTROLLER  To facilitate the interface between the controller and the MEMORY  Providing the interface between the controller and the ALU  Designing of program counter  Designing of instruction register .

.1. Design aspects of controller interfacing.4 Thesis organization : 8051 controller. Simulation This project report has been organized into different sections such as results and Implementation of controller. .

CHAPTER 2 .

such as displaying or receiving information through LEDs or remote controlled devices. RAM – 128 Bytes (Data memory) ii. 2.2 FEATURES of 8051 : The main features of 8051 microcontroller are: i. . Serial Port – Using UART makes it simpler to interface for serial communication.8051-MICROCONTROLLER 2. ROM – 4Kbytes (ROM signify the on – chip program space) iii. The most commonly used set of microcontrollers belong to 8051 Family.1 INTRODUCTION : A microcontroller is an economical computer-on-a-chip built for dealing with specific tasks. Through 8051. 8051 Microcontrollers continue to remain a preferred choice for a vast community of hobbyists and professionals. the world became witness to the most revolutionary set of microcontrollers.

3 History of 8051 and Key Developments : Intel Corporation fabricated the 8 – bit microcontroller which was referred as MCS-51 in 1981. Bus. This has added advantage that if the program is written then it can be used for any version of 8051 despite of manufacturer. sleeker and more efficient. 2 Timers. 8 – bit ALU (Arithmetic Logic Unit) viii. Harvard Memory Architecture – It has 16 bit Address bus (each of RAM and ROM) and 8 bit Data This microcontroller is also called as “System on a chip” because it has all the features on a single chip. 2. the quality of technology surpassed the expectation of the greatest minds. This microcontroller was also referred as “system on a chip” because it has 128 bytes of RAM. 1 Serial port. vi.iv. Intel permitted other manufacturers to fabricate different versions of 8051 but with the limitation that code compatibility should be maintained. Most manufacturers have put 4Kbytes of ROM even though the quantity of ROM can be exceeded up to 64 K bytes. In case the data is larger than 8 bits then it has to be broken into parts so that the CPU can process conveniently. 4Kbytes of ROM. v. ix. The CPU can work for only 8bits of data at a time because 8051 is an 8-bit processor. 8051 can execute 1 million one-cycle instructions per second with a clock frequency of 12MHz. Two 16 bit Timer/ Counter Input/output Pins – 4 Ports of 8 bits each on a single chip. and four ports on a single chip. As years passed by. 6 Interrupt Sources vii. with gadgets becoming smaller. Microcontrollers were seen as the .

iii. iv. The disadvantage of adding external ROM is that 2 ports (out of the 4 ports) are used. ii. Hence. vi. In addition to the standard features of 8051. An external ROM that can be as large as 64 K bytes should be programmed and added to this chip for execution. The other two members of the 8051 family are: i. only 2 ports are left for I/O operations which can also be added externally if required for execution. v.4 8051 Family : Intel fabricated the original 8051 which is known as MCS-51. ii. Comparison of 8051 family members: . The programs written for projects using 8051 microcontroller can be used to run on the projects using 8052 microcontroller as 8051 is a subset of 8052. Ease-of-use Market availability Less power usage Smaller processing power More integrated features like RF and USB Smaller form factors 2. 8052 – This microcontroller has 256 bytes of RAM and 3 timers. this microcontroller has an added 128 bytes of RAM and timer.answer to the requirements raised in advanced electronics. This is the reason why manufacturers have now focused their production around the following main developmental aspects: i. It has 8K bytes of on chip program ROM. 8031 – This microcontroller has all the features of 8051 except for it to be ROM-less.

Flash and NVRAM. The flash memory can erase the contents within seconds which is best for fast growth.5 Various 8051 microcontrollers : 8051 microcontrollers use two different kinds of memory such as UV. 8751 – This microcontroller is the UV-EPROM version of 8051. Hence 8051 will not be seen in the part number even though it is the most popular member of the 8051 family. entire . Due to this limitation.EPROM. ii.Features RAM(bytes) ROM Timers Serial port I/O pins Interrupt sources 8051 128 4K 2 1 32 6 8052 256 8K 3 1 32 8 8031 128 0K 2 1 32 6 Comparison of 8051 family members 2. i. To build up a microcontroller based system using AT89C51. AT89C51 from Atmel Corporation – Atmel fabricated the flash ROM version of 8051 which is popularly known as AT89C51 (‘C’ in the part number indicates CMOS). This chip has only 4K bytes of UV-EPROM. Note that in Flash memory. it is essential to have ROM burner that supports flash memory. The disadvantage of using this memory is the waiting time of around 20 minutes to erase the contents in order to program it again. It is required to have access to the PROM burner and the UV-EPROM eraser to erase the contents inside the chip before it is programmed again. manufacturers fabricated flash and NV-RAM versions of 8051. 8751 is replaced by AT89C51 to eradicate the waiting time required to erase the contents and hence expedite the development time. Therefore.

The same instructions used for lower half of Internal RAM can be used to access SFR’s. Loading R0 and R1 the memory location from 0x80 to 0xFF can easily accessed. The contents are erased by the ROM burner. External Data Memory – Located at address 0. iv. Program Memory – This is read only memory which is located at address 0. The Instruction MOVX (Move External) should be used to access the external data memory. 2. ii. With the help of 16 bit Special Function Register DPTR. The bytes from 0x20 to 0x2F are bitaddressable.contents must be erased to program it again.6 Memory Architecture : The 4 discrete types of memory in 8051 are: I. iv. The SFR’s are bit addressable too. The manufacturers use OTP microcontroller for mass production because the price per unit is very cheap.7 Programming environment and programmer : . The memory locations from 0x00 to 0x7F are accessed directly. Internal RAM – This memory is located from address 0 to 0xff. Special Function Registers (SFR) – Located from address 0x80 to 0xFF of the memory location. iii.Programmable (OTP) versions of the 8051 – This version of microcontroller is cheaper and available from various manufacturers. One .Time . this memory can also save the tables of constants. Atmel is working on a newer version of AT89C51 that can be programmed using the serial COM port of IBM PC in order to get rid of the ROM burner. 2.

programmers used machine language for coding. A machine language is a program that consists of 0s and 1s which was very dreary for the humans .Formerly.

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Usually. C++. and P3 each have 8 pins and can be used for either input or output. PO. EA. . assembly language was developed in order to speed up the programming and make it error-free. the program needs to be translated into machine language using C compiler. 8051 provides the programmer with the ability to read. XTAL2. write and modify each port to customize applications as much as possible. Forth. For example. Assembly and C language is widely used for 8051 programs as compared to the other high level languages. XTAL1. thus providing programmers with a unique and powerful feature. RST. These high level languages make use of a Compiler to translate into machine code. ALE/PROG and PSEN. C. The 8051 provides a total of four ports for I/O operations. of which 32 pins are set aside for the four ports. 8051 has 40 pins. GND. Pascal. P1. when a program is written in C. Assembly language is a low level language which uses an assembler to translate the program into machine code. P2.program any computer. 8051 allows you to manipulate one or all of the bits of a port. The high level programming languages such as BASIC. and Java are available to code the program for 8051. In due course of time. The remaining pins are designated as Vrt.

CHAPTER 3 BLOCK DIAGRAM .

1 Working of modules .1.1 block diagram of the project Totally this block diagram comprises of four components: ALU  INSTRUCTION REGISTER  PROGRAM COUNTER  MEMORY 3.The block diagram of the project is shown in the Figure 3. Figure 3.

FLOW CHART FOR IMPLEMENTATION OF ALU . An execlk is given as input for synchronization and the output is available at positive edge of the execlk.1 Function of ALU : The ALU performs both arithmetic and logical operations and as well as control of transfer instructions.3. It takes data and acc as inputs to generate output according to the opcode. It performs arithmetic and logic instructions directly and control of transfer instructions are performed with the help of control and logic decoder.1.

S tart E n tearc c .o p c o d e g iv e x e c lk e P o s itiv e e d g e o fe x e c lk O p c o =“0 0 0”0 de A cc 1 = A c c + d a ta A cc 1 = .d a ta .

If Reset =0. When reset is high and load accumulator signal is set high.3. the output of the ALU is loaded in to the accumulator at the negative edge of the exe clk. the output of accumulator is cleared to zero.1.2 Function of accumulator: The result of an ALU operation is always stored in accumulator at some specified time based on the control logic instruction and also the exe clk. This output is again fed to ALU as input. FLOW CHART FOR IMPLEMENTATION OF ACCUMULATOR .

execlk Nega tive edge of execl k Rst =’0’ Y N stop Y N ldacc= ’1’ Y N stop acc=’0’ acc=ac c1 stop stop .Start Input acc1. ldacc.rst .

Remains in high impedance state when Wr=0.1. Wr Addr InOut Data 3.3. Description Bi-directional bus that carries all the data from & to the Memory or Instruction register or Accumulator. executes it and increments the content of PC. The CPU fetches an instruction from memory.1.6 Function of instruction register: . Thus in the next instruction cycle. 3.5 Function of program counter : The program counter (PC) contains the address of the next instruction.1. Carries the address of the Memory location to be Read or Written upon. The instructions are executed sequentially unless an instruction changes the content of program counter. it will fetch the next instruction of the program pointed out by the program counter.Remains in high impedance state when Rd=0.4 Function of memory: Inputs Rd Description Enables the output buffer of the Memory registers and makes the data available on the Data line when Rd=1. Enables the input buffer of the Memory registers and makes the data available on the Data line when Wr=1.

Now the result is available at acc1 at positive edge of execlk. The MSB’s of this loaded data are the Opcode of the Instruction and the remaining bits [are the address of a memory location to fetch the subsequent data. This is called the instruction load. the instruction from the memory is put on the data bus. When LdIr signal is high. After an instruction is fetched the program counter is incremented. After some instance. then during this clock cycle. 3. The outputs of the instruction register and the program counter are connected to a mux. In this cycle the msb’s of the instruction are separated and put in the opcode register and are loaded to control unit as well as ALU. Now when the fetch signal goes low the mux selects the output from the instruction register and it points to the location of the operand. The operand is taken in by the ALU and operates on it. The instruction is now available at the data bus. Now the operand is available at the ALU.Instruction register is a register which gets loaded with data from the memory. The rest of the bits are sent out as Irout. 2 Function of the project Let us consider an instance when some information is stored in the memory. Now when the system is switched on. the result at the Acc1 register is placed on the data bus. Rd and Wr has to be 0 & 1 respectively. while the output from the program counter is selected during the positive edge of fetch cycle. At next instance the instruction is loaded into the instruction register. In order to fetch an instruction. Now the operand present in the location is placed on the data bus. the output of the instruction register is selected. This cycle is called the instruction fetch cycle. If the data has to be stored into the memory. As . CPU is initialized. During the negative edge of the fetch signal. as a result the program goes to the location in the memory that is pointed out by the program counter. which is sent and loaded into the accumulator for any further operations. It points to the next location. the data bus contents get loaded into the Instruction register. During the negative edge of execlk.

3. 3.a result the accumulator is connected to the memory and the value in the accumulator is sent back to a location in the memory through a module named Buffer.3 Pin diagram of the 8051 : 3.1 Pin out Description : Pins 1-8: Port 1 Each of these pins can be configured as an input or an output .

miniature ceramics resonators can also be used for frequency stability. port data multiplexing is performed by . each of these pins can serve as general input or output. In case external memory is used. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. A quartz crystal which specifies operating frequency is usually connected to these pins. After receiving signal from the ALE pin. Pin 20: GND Ground. the positive voltage on this pin resets the microcontroller. As seen. Pin 17: RD Read from external RAM. By applying logic zero to this pin. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. which means that not all eight port bits are used for its addressing. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. 19: X2. the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. In other words. Pin 16: WR Write to external (additional) RAM.. all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. Instead of it. Pin 18. Pins10-17: Port 3 Similar to port 1. Pin 14: T0 Counter 0 clock input. Pin 30: ALE Prior to reading from external memory. the rest of them are not available as inputs/outputs. the higher address byte. Pin 12: INT0 Interrupt 0 input.e. addresses A8-A15 will appear on this port.Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. Pin 13: INT1 Interrupt 1 input. Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. the program starts execution from the beginning. Pin 15: T1 Counter 1 clock input. i. Even though memory with capacity of 64Kb is not used. X1 Internal oscillator input and output. Besides. Immediately after that.

but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory. P1. In other words. read and write pins for memory access. the microcontroller will use both memories. the program written to external ROM will be executed. 2 external counter inputs. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present. 2 external interrupt pins. if external memory is not used. The other ports P0. Otherwise.5 Ports : There are 4 8-bit ports: P0.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present. PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output port which can be used for a variety of interfacing tasks. it will not be executed.means of only one additional (and cheap) integrated circuit. as can be seen from fig 1. P2 and P3. serial transmit and receive pins. this port is used for both data and address transmission. these pins can be used as general inputs/outputs. By applying logic one to the EA pin. P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage. P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. Pin 32-39: Port 0 Similar to P2. 3. first internal then external (if exists). but if external memory access is required then PORT P0 acts as a multiplexed address and data bus that can be used to access external memory in conjunction with . PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port. Pin 31: EA By applying logic zero to this pin. PORT P2 acts as A8A15. Instead. but Port P3 has additional functions such as. P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40: VCC +5V power supply. It means that even there is a program written to the microcontroller.

only the first 255 locations of RAM can be accessed this way.). while the other explains HOW to do it. to accumulator 3. This is the only way of accessing all the latest versions of the microcontrollers with additional memory block (128 locations of RAM).8 Indirect Addressing modes : On indirect addressing. the address of memory location containing data to be read is specified in instruction. The address may contain a number being changed during operation (variable). One part describes WHAT should be done.1 3.7 Direct Addressing modes : On direct addressing.PORT P2. The latter part can be a data (binary number) or the address at which the data is stored.6 Addressing modes : While operating. Data to be used in the program is stored in the letter register. as can be seen from fig 1. while another half is reserved for SFRs. P0 acts as AD0-AD7. MOV A. the processor knows that indirect addressing is used and skips memory space reserved for SFRs. when the program encounters instruction including “@” sign and if the specified address is higher than 128 ( 7F hex. Means: move a number from address 33 hex. Each instruction consists of two parts. MOV A. the processor processes data as per program instructions. Simply put. Means: Store the value from the register whose address is in the . Two ways of addressing are used for all 8051 microcontrollers depending on which part of memory should be accessed: 3.33h.@R0. For example: Since the address is only one byte in size (the largest number is 255). a register containing the address of another register is specified in instruction. For example: Indirect addressing is only used for accessing RAM locations available for use (never for accessing SFRs). The first half of RAM is available for use.

R0 register into accumulator On indirect addressing. registers R0. it is possible to access only registers of internal RAM this way (128 locations when speaking of previous models or 256 locations when speaking of latest models of microcontrollers). Since only 8 bits are avilable. . R1 or Stack Pointer are used for specifying 8-bit addresses. If an extra memory chip is added then the 16-bit DPTR Register (consisting of the registers DPTRL and DPTRH) is used for specifying address. In this way it is possible to access any location in the range of 64K.

CHAPTER 4 .

Behavioral specifications can use either an algorithm or an actual hardware structure to define an elements operation. Concurrency. Thus VHDL started out as a documentation and modeling language.S. VHDL handles asynchronous as well as synchronous sequential circuit structures. While the language and simulation environment were important innovations by themselves. VHDL’s utility and popularity took a quantum leap with the commercial development of VHDL synthesis tools. These programs can create logic circuit structures directly from VHDL behavioral and descriptions.APPENDIX VHDL BASICS : 4. Each design element has both a well – Defined interface and a precise behavioral specification 3. The language has the following features: 1. 2. Design may be decomposed hierarchically. Department of defence and the IEEE sponsored the development of a highly capable hardware –description language called VHDL. and synthesize anything from a simple . simulate. The logical operation and timing behavior of a design can be simulated. you can design. 4. 5. Using VHDL. allowing The behavior of digital system design to be precisely specified and simulated.1 Introduction In the mid-1980’s. timing and clocking can all be modeled. the U.

It is only at this stage that the actual circuit delays due to wire lengths electrical loading and other factors can be calculated with a reasonable precision. their interfaces. VHDL was standardized by the IEEE in 1987 and extended in 1993. The front. a fitting tool or fitter maps the synthesized primitives or components onto available device resources. It may generate a list of gates and a net list that specifies how they should be interconnected. The purpose of simulation is to verify that the circuit works as desired.2 Design Flow : There are several steps in the VHDL based design process called design flow. and their internal details. which converts the VHDL description into a set of primitives or components that can be assembled in the target technology. without ever having to build the physical circuit. . A VHDL compiler analyzes the code for syntax errors and also checks it for compatibility with other modules on which it relies. 4. The final step is the timing verification of the fitter circuit. The next step is the actual writing of the VHDL code for modules.end begins with figuring out the basic approach and building blocks at the block diagram level. In the fitting step.combinational circuit to a complete microprocessor system on a chip. A VHDL simulator allows to define and apply inputs to the design and to observe its outputs. The backend begins with synthesis.

Fig 4. Thus a VHDL entity is simply a declaration of modules inputs and outputs while VHDL architecture is a detailed description of the modules internal structure or behavior.1 Steps in a VHDL Design Flow Hierarchy/ block diagram Coding Compilatio n Simulatio n/ Verificatio n Fitting/ Synthesis Place + Route Timing Verificatio n 4.1 .2.3.3 Program Structure : VHDL was designed with principles of structured programming. Entity declaration Architecture definition Fig 4. The key idea is to define the interface of a hardware module while hiding its internal details.

Data flow modeling In complex designs as the number of gates is very large.modeled using gate and module instantiation. 2. the module is designed by specifying the dataflow.These styles are: 1. 2. data flow modeling. Data flow style . . Behavior may be specified by Boolean equations. the designers can design more effectively by implementing the function at a level of abstraction higher than the gate level. tables of input and output values. 1. A process is a collection of sequential statements that execute in parallel with other concurrent statements and other processes.modeled using continuous assignments. or algorithms written in standard high-level computer languages or special Hardware Description Languages (HDLs).4 Design styles : A design can be modeled into three different styles or in a mixed style. At this level.4. 3. VHDL’s key element is ‘process’. Structural style . Behavioral style Behavioral representation describes how a particular design should respond to a given set of inputs. The designer is aware of how data flows between hardware registers and how the data is processed in the design. Behavioral style – modeled using procedural constructs.

Standard language 2. Multiple mechanisms to support design hierarchy 5.5 Advantages of VHDL VHDL offers several advantages to the designer. 4. Structural modeling A VHDL architecture that uses components is called a structural description or structural design because it defines the precise interconnection structure os signals and entities that realize the entity. Powerful and versatile description language 4. Readily available tools 3. They are: 1.Dataflow modeling provides a powerful way to implement a design. 3. The most basic of VHDL’s structural design is the component statement. Versatile design reconfiguration support 6. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. Here component is the name of the previously defined entity that is to be instantiated within the architecture body. Support for multiple levels of abstraction .

CHAPTER 5 .

Create a VHDL Source formatting all inputs. to be synthesized. Any simulated code can be synthesized and configured on FPGA. It is an integral part of current design flow .SOFTWARE XILING Xilinx software is used by the VHDL designers for performing Synthesis operation. Synthesis is the transformation of VHDL code into gate level net list. . outputs and buffers if required. which provides a window to write the VHDL code. Create a New Project and find the following properties displayed. Algorithm : Start the ISE Software by clicking the XILINX ISE icon.

Check Syntax after finally editing the VHDL source for any errors. Design Simulation is done after compilation. .

CHAPTER 6 .

SOURCE CODE ----------------ACCUMULATOR library ieee.acc1. use ieee. acc: out std_logic_vector (31 downto 0).execlk: in bit).all. entity accm is port( acc1: in std_logic_vector (31 downto 0). end if. end process. architecture acc_beh of accm is begin process(rst. end acc_beh . elsif ldacc ='1' then acc<= acc1.std_logic_1164. ldacc. use ieee. end accm.rst. end if.std_logic_unsigned.execlk.all. -----load accumulator .ldacc) begin if(execlk='1' and execlk'event) then if rst ='0' then ----clock edge ------reset condition acc<= "00000000000000000000000000000000".

entity alu is port(acc: in std_logic_vector(31 downto 0). use ieee. execlk:in bit ).std_logic_1164 .all.------------------------------------------ALU library ieee. end alu.all. opcode: in std_logic_vector(3 downto 0). architecture aluarc of alu is begin process (execlk) begin if (execlk='1' and execlk'event and execlk'last_value='0') then -----clock edge case (opcode) is when "0000"=> acc1<=acc + data. use ieee.--add . data : in std_logic_vector(31 downto 0).std_logic_unsigned. acc1: out std_logic_vector(31 downto 0).

when "1001"=>--rs acc1<=data(0) & data(31 downto 1). --dec when "0100"=> acc1<=acc and data. --inc when "0011"=> acc1<=data-1. when "1100"=>--hlt acc1<=acc.--or when "0110"=> acc1<=acc xor data. .--xor when "0111"=> acc1<=not data. when "1011"=> --skip acc1<=acc.--not when "1000"=>--ls acc1<=data(30 downto 0) & data(31). --sub when "0010"=> acc1<=data+1. when "1101"=>--ldacc acc1<= data. when "1010"=>--jmp acc1<=acc.--and when "0101"=> acc1<=acc or data.when "0001"=> acc1<=acc-data.

std_logic_1164. -----------------------------------BUFFER library ieee. end aluarc. when others=> acc1<=acc.std_logic_unsigned. end if. use ieee. use ieee. data:out std_logic_vector(31 downto 0)). end case.all. end process. y:in bit.when "1110" =>----stracc acc1<=acc. entity buff is port(acc1:in std_logic_vector(31 downto 0). end buff. architecture buff1 of buff is .all.

entity ir is port(data:in std_logic_vector(31 downto 0). architecture ir of ir is begin process(ldir. irout:out std_logic_vector(27 downto 0). REGISTER----------------- use ieee.std_logic_1164. end if.rst:in bit.all. ldir. -----------Buffer action -----------------INSTRUCTION library ieee.data. end buff1. opcode:out std_logic_vector(3 downto 0)).all. end ir.begin process(y.acc1) begin if(y='1')then data<=acc1. use ieee. rst) begin if(rst='0') then irout<="0000000000000000000000000000". ---instruc reg .std_logic_unsigned. end process.

address: in std_logic_vector(27 downto 0).all.std_logic_unsigned. wr : in bit. end memy.std_logic_1164. end if.opcode<="1111". -------------------------------MEMORY library ieee. architecture memarch of memy is . use ieee. end ir. elsif(rst='1' and ldir='1') then irout<= data(27 downto 0). use ieee. entity memy is port(data: in std_logic_vector(31 downto 0). data1: out std_logic_vector(31 downto 0)). end process. rd. rst: in bit.all. opcode<= data(31 downto 28).

109=>"00000000000000000000000000001001". 102=>"00000000000000000000000000000010". 104=>"00000000000000000000000000000100". -------------------memory 101=>"00000000000000000000000000000001". begin data1<="00000000000000000000000000000000". ------instructions 100=>"00000000000000000000000000000000". memory <=( 0=>"11010000000000000000000001100101". 107=>"00000000000000000000000000000111".type t_mem is array(0 to 255)of std_logic_vector(31 downto 0).rst) --type t_mem is array(0 to 255)of std_logic_vector(31 downto 0). signal memory :t_mem. --variable memory :t_mem.wr. 106=>"00000000000000000000000000000110". 1=>"00000000000000000000000001100110". begin process(rd. 103=>"00000000000000000000000000000011". ------constants start . 108=>"00000000000000000000000000001000". 2=>"11100000000000000000000010000000". 105=>"00000000000000000000000000000101".address. 3=>"11000000000000000000000001111100".

117=> "00000000000000000000000000010001". 120=> "00000000000000000000000000010100". 115=> "00000000000000000000000000001111". end if. 125=> "00000000000000000000000000011001". 116=> "00000000000000000000000000010000". -------1 . 112=> "00000000000000000000000000001100". end loop. 119=> "00000000000000000000000000010011". --memory data constants end others=>"00000000000000000000000000000000").110=>"00000000000000000000000000001010". if(rst='0')then -------1 for x in 0 to 105 loop -. 124=>"00000000000000000000000000011000". 122=> "00000000000000000000000000010110". 121=> "00000000000000000000000000010101". 123=> "00000000000000000000000000010111". 114=> "00000000000000000000000000001110". 118=>"00000000000000000000000000010010". 113=> "00000000000000000000000000001101". 111=> "00000000000000000000000000001011".memory(150 + x) :="00000000000000000000000000000000" . memory(150 + x) <="00000000000000000000000000000000" .

end if.all. if(rd='1' and wr='0') then --------2 --------3 --data <= memory(conv_integer(address)). memory(conv_integer(address))<=data.all. pcout:in std_logic_vector(27 downto 0). end process.if(wr='1' and rd='0') then ---------2 if(conv_integer(address)>150 and conv_integer(address)<=255) then -. use ieee. -------3 -----------------------------------MUX library ieee. end memarch.std_logic_1164.memory(conv_integer(address)):=data. fetch:in bit. data1 <= memory(conv_integer(address)). addr:out std_logic_vector(27 downto 0) ). end if.std_logic_unsigned. end if. architecture mux1 of mux is . end mux. entity mux is port(irout:in std_logic_vector(27 downto 0). use ieee.

begin -- fetch1<=not fetch . . -------------------------------PROGRAM COUNTER library ieee.-- signal fetch1:bit. use ieee.addr<=pcout after 0ns when fetch='0' and fetch1='1' else -------pcout selected --irout after 0ns when fetch='1' and fetch1='0' else ------irout selected process(fetch. end if.irout.std_logic_1164.all. end mux1. end process. -.pcout) begin --if(fetch='1' and fetch1='0')then if(fetch='1')then addr<=pcout. else --elsif(fetch='0' and fetch1='1')then addr<=irout.

architecture pc2 of pc11 is signal pc3: std_logic_vector(7 downto 0):="00000000". irout: in std_logic_vector(27 downto 0).signal fetch1:std_logic. begin if (fetch = '1' and fetch'event) then --pcout<=(others=>'0').std_logic_unsigned.trigger on clock changes . begin --fetch1<= not fetch. -. entity pc11 is port ( fetch. if (incpc='1')then if(pc3 = "11111111") then pc3<="00000000". pcout : out std_logic_vector(27 downto 0)). t:= "00000000000000000000" & pc3.std_logic_arith. --.incpc) variable t:std_logic_vector(27 downto 0):="0000000000000000000000000000". end pc11. -.all.ldpc.use ieee. process(fetch.incpc: in bit.fetch1<= not fetch. use ieee.all. pcout<=t.

-begin --fetch1:=not fetch. end if. --changed to --pcout<="00000000000000000000000" & pc3.process(fetch. else if(fetch='0' and fetch'event)then if(ldpc='1')then pcout<=irout. -------------changed -. . --fetch1:=not fetch. pcout<=t.pcout<="0000000000000000000000000000".ldpc) --variable fetch1:std_logic. end process.pc3<=irout(4 downto 0). end if. else pc3<= pc3 + "00000001". t:="00000000000000000000" & pc3. end if. else pcout<=t.-. trailing-edge triggered. -. end if. end if.

entity ctr is port(fetch : in bit. end ctr. use ieee. -pcout<=""&pc1. architecture ctr1 of ctr is . rst: buffer bit).wr.-- if(fetch='0' and fetch'event)then --if(ldpc='1') then -.rd. use ieee.incpc. --pcout<="00000000000000000000000" & pc3. --end if.all. ldir. opcode:in std_logic_vector(3 downto 0).std_logic_1164.ldacc.all. --------------------------------------CONTROL library ieee.ldpc. end pc2.pcout<=irout. -end if.end if. -. -end process.y: out bit.std_logic_unsigned.

--fetch ldpc<='1' when opcode="1010" else --jmp '0' . y<='1' when opcode="1110" else --sta '0'. ldir<= not fetch.begin incpc<='0' when op code="1011" else '1' . . wr<= '1' when op code<="1110" else --sta '0' . --hlt end ctr1. ldacc<='1' when oPcode<="1101" else --ldacc '0'. rst<='0' when op-code="1100" else '1'. rd<='0' when op code ="1110" else '1' .

CHAPTER 7 .

ACCUMULATER: .

ALU : .

BUFFER : .

INSTRUCTION REGISTOR : .

MEMORY: .

MUX : .

PROGRAM COUNTER : .

CONTROL : .

CHAPTER 8 .

Advantages of 8051 microcontroller :  More speed  Less power requirement  Safe and secure  microcontrollers are used to regulate the brakes on all four wheels.  Lowest The interfacing of 8051 microcontroller is simple .  Implementation is easy .  The 8051 microcontroller interfacing is having High speed and Low programming overhead. 115200 should be achieved with small microcontrollers using short distances .  Flexibility decreases  Low speed for long distance.  Cost increases.  By using interfacing of 8051 microcontroller implementation of software and hardware is easy . or a microcontroller responsible for the cruise control . Disadvantages of 8051 microcontroller :  Complexity of the circuit board increases. or a microcontroller to regulate the car air conditioning.

CHAP TER9 .

APPLICATIONS

The 8051 has been in use in a wide number of devices, mainly because it is easy to integrate into a project or build a device around. The following are the main areas of focus: i. Energy Management: Efficient metering systems help in controlling energy usage in homes and industrial applications. These metering systems are made capable by incorporating microcontrollers.

ii.

Touch screens: A high number of microcontroller providers incorporate touch-sensing capabilities in their designs. Portable electronics such as cell phones, media players and gaming devices are examples of microcontroller-based touch screens.

iii.

Automobiles: The 8051 finds wide acceptance in providing automobile solutions. They are widely used in hybrid vehicles to manage engine variants. Additionally, functions such as cruise control and anti-brake system have been made more efficient with the use of microcontrollers.

iv.

Medical Devices: Portable medical devices such as blood pressure and glucose

monitors use microcontrollers will to display data, thus providing higher reliability in providing medical results .

Future scope
In future there is a chance to interface some more devices with this controller without degrading the speed.

C HAPTER 10

In this project. Appendix . instruction register designs using VHDL Language.CONCLUSION In this work.2i . program counter. The basic aim of our project is to model the memory.VHDL coding for the controller and their interfacing modules was done successfully. initially the investigation on the 8051controller and their interfaces is carried out and its working is identified based on which the block diagram and the specifications are developed for designing the modules using VHDL. The simulation results shows that the behavior of each and every module separately. 8051 Microcontroller is implemented in Xilinx 9.

VHDL BASICS A.1 Introduction In the mid-1980’s. Behavioral specifications can use either an algorithm or an actual hardware structure to define an elements operation. These programs can create logic circuit structures directly from VHDL behavioral and descriptions. VHDL’s utility and popularity took a quantum leap with the commercial development of VHDL synthesis tools. Concurrency. Department of defence and the IEEE sponsored the development of a highly capable hardware –description language called VHDL. 5. allowing The behavior of digital system design to be precisely specified and simulated. Each design element has both a well – Defined interface and a precise behavioral specification 3. Thus VHDL started out as a documentation and modeling language. The language has the following features: 1. Design may be decomposed hierarchically. 2. timing and clocking can all be modeled. and synthesize anything from a simple . Using VHDL. While the language and simulation environment were important innovations by themselves. you can design. VHDL handles asynchronous as well as synchronous sequential circuit structures. 4. the U.S. simulate. The logical operation and timing behavior of a design can be simulated.

It is only at this stage that the actual circuit delays due to wire lengths electrical loading and other factors can be calculated with a reasonable precision. and their internal details. The purpose of simulation is to verify that the circuit works as desired. A VHDL simulator allows to define and apply inputs to the design and to observe its outputs.2 Design Flow There are several steps in the VHDL based design process called design flow. It may generate a list of gates and a net list that specifies how they should be interconnected. without ever having to build the physical circuit. . a fitting tool or fitter maps the synthesized primitives or components onto available device resources. which converts the VHDL description into a set of primitives or components that can be assembled in the target technology. A VHDL compiler analyzes the code for syntax errors and also checks it for compatibility with other modules on which it relies.combinational circuit to a complete microprocessor system on a chip. The backend begins with synthesis. The next step is the actual writing of the VHDL code for modules. VHDL was standardized by the IEEE in 1987 and extended in 1993. their interfaces. A. The frontend begins with figuring out the basic approach and building blocks at the block diagram level. The final step is the timing verification of the fitter circuit. In the fitting step.

3 Program Structure VHDL was designed with principles of structured programming.2. The key idea is to define the interface of a hardware module while hiding its internal details. Thus a VHDL entity is simply a declaration of modules inputs and outputs while VHDL architecture is a detailed description of the modules internal structure or behavior.Fig A. Entity declaration Architecture definition Fig A.3.1 Steps in a VHDL Design Flow Hierarchy/ block diagram Coding Compilatio n Simulatio n/ Verificatio n Fitting/ Synthesis Place + Route Timing Verificatio n A.1 .

Behavioral style – modeled using procedural constructs. Structural style . Data flow style . tables of input and output values. 2. 2. . The designer is aware of how data flows between hardware registers and how the data is processed in the design.A. or algorithms written in standard high-level computer languages or special Hardware Description Languages (HDLs). A process is a collection of sequential statements that execute in parallel with other concurrent statements and other processes. 1.modeled using gate and module instantiation.4 Design styles A design can be modeled into three different styles or in a mixed style. data flow modeling. VHDL’s key element is ‘process’. 3. Behavioral style Behavioral representation describes how a particular design should respond to a given set of inputs. Behavior may be specified by Boolean equations. Data flow modeling In complex designs as the number of gates is very large.These styles are: 1.modeled using continuous assignments. the module is designed by specifying the dataflow. At this level. the designers can design more effectively by implementing the function at a level of abstraction higher than the gate level.

Support for multiple levels of abstraction . Readily available tools 3. They are: 1. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. Structural modeling A VHDL architecture that uses components is called a structural description or structural design because it defines the precise interconnection structure os signals and entities that realize the entity.Dataflow modeling provides a powerful way to implement a design. Versatile design reconfiguration support 6. Standard language 2.5 Advantages of VHDL VHDL offers several advantages to the designer. Powerful and versatile description language 4. The most basic of VHDL’s structural design is the component statement. Multiple mechanisms to support design hierarchy 5. A. 3. Here component is the name of the previously defined entity that is to be instantiated within the architecture body.

Algorithm Start the ISE Software by clicking the XILINX ISE icon. Create a VHDL Source formatting all inputs.Xilinx Xilinx software is used by the VHDL designers for performing Synthesis operation. Any simulated code can be synthesized and configured on FPGA. Create a New Project and find the following properties displayed. outputs and buffers if required. which provides a window to write the VHDL code. to be synthesized. Synthesis is the transformation of VHDL code into gate level net list. It is an integral part of current design flows. .

Check Syntax after finally editing the VHDL source for any errors. Design Simulation is done after compilation. .

Pin diagram of the 8051 Pinout Description Pins 1-8: Port 1 Each of these pins can be configured as an input or an output. Pins10-17: Port 3 Similar to port 1. Pin 14: T0 Counter 0 clock input. the program starts execution from the beginning. each of these pins can serve as general input or output. In other words. Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. Pin 12: INT0 Interrupt 0 input. Pin 13: INT1 Interrupt 1 input. all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. the positive voltage on this pin resets the microcontroller. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. By applying logic zero to this pin. Pin 15: T1 Counter 1 clock input. Besides. .

Pin 30: ALE Prior to reading from external memory. In other words. Even though memory with capacity of 64Kb is not used. the higher address byte. Pin 20: GND Ground.Pin 16: WR Write to external (additional) RAM. Instead of it. Pin 32-39: Port 0 Similar to P2. By applying logic one to the EA pin. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. A quartz crystal which specifies operating frequency is usually connected to these pins. It means that even there is a program written to the microcontroller. miniature ceramics resonators can also be used for frequency stability. P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Otherwise. if external memory is not used. the rest of them are not available as inputs/outputs. 19: X2.e. the program written to external ROM will be executed. the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. Pin 31: EA By applying logic zero to this pin. it will not be executed. P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. As seen. the microcontroller will use both memories. Immediately after that. addresses A8-A15 will appear on this port. the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. Pin 40: VCC +5V power supply. Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. this port is used for both data and address transmission. X1 Internal oscillator input and output. Ports . Instead. these pins can be used as general inputs/outputs. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. i. Pin 18. port data multiplexing is performed by means of only one additional (and cheap) integrated circuit. Pin 17: RD Read from external RAM. After receiving signal from the ALE pin. In case external memory is used. which means that not all eight port bits are used for its addressing. first internal then external (if exists).

For example: Since the address is only one byte in size (the largest number is 255).1 Addressing modes While operating. to accumulator Indirect Addressing modes On indirect addressing. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present. as can be seen from fig 1. but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory.There are 4 8-bit ports: P0. The first half of RAM is available for use. while another half is reserved for SFRs. The latter part can be a data (binary number) or the address at which the data is stored. The other ports P0.33h. Each instruction consists of two parts. read and write pins for memory access. PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output port which can be used for a variety of interfacing tasks. but if external memory access is required then PORT P0 acts as a multiplexed address and data bus that can be used to access external memory in conjunction with PORT P2. P0 acts as AD0-AD7. the processor processes data as per program instructions. P1. 2 external counter inputs. PORT P2 acts as A8A15. while the other explains HOW to do it. For example: . serial transmit and receive pins. P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage. Data to be used in the program is stored in the letter register. Means: move a number from address 33 hex. as can be seen from fig 1. but Port P3 has additional functions such as. the address of memory location containing data to be read is specified in instruction. PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present. a register containing the address of another register is specified in instruction. P2 and P3. One part describes WHAT should be done. The address may contain a number being changed during operation (variable). 2 external interrupt pins. only the first 255 locations of RAM can be accessed this way. MOV A. Two ways of addressing are used for all 8051 microcontrollers depending on which part of memory should be accessed: Direct Addressing modes On direct addressing.

Simply put.). In this way it is possible to access any location in the range of 64K. Since only 8 bits are avilable.Indirect addressing is only used for accessing RAM locations available for use (never for accessing SFRs). it is possible to access only registers of internal RAM this way (128 locations when speaking of previous models or 256 locations when speaking of latest models of microcontrollers). when the program encounters instruction including “@” sign and if the specified address is higher than 128 ( 7F hex.@R0. Means: Store the value from the register whose address is in the R0 register into accumulator On indirect addressing. registers R0. R1 or Stack Pointer are used for specifying 8-bit addresses. This is the only way of accessing all the latest versions of the microcontrollers with additional memory block (128 locations of RAM). MOV A. the processor knows that indirect addressing is used and skips memory space reserved for SFRs. . If an extra memory chip is added then the 16-bit DPTR Register (consisting of the registers DPTRL and DPTRH) is used for specifying address.