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ABSTRACT

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx FPGA. FPGAs are the lowest power Devices available, making these FPGAs the perfect interface devices for many of todays popular microcontrollers.

An interface to the 8051 microcontroller has been implemented in a XILINX FPGA. This design consists of a state machine that interprets the 8051 bus cycles to read and write data to a set of registers called a register file. A high-level block diagram is shown in Figure 1. Communication between the 8051 microcontroller and the application logic is accomplished through a register file. The 8051 microcontroller writes data to the register file to configure and control the application logic. The application logic writes status information and service requests to the microcontroller through the register file. Data transfer is also done through registers. Flags can be designed that denote when registers are empty and/or full depending on the application. The number of registers and their bit definitions are defined in general terms and should be customized for the application. Here in this project we r interfacing 8051 Microcontroller with XILINX FPGA. By interfacing this Microcontroller with FPGA we can able to increase the circuit abilities without complexity And the one of the best advantage is its Hardware Re configurability.

We can modify as well as upgrade the circuit behaviour by depending on the application.

CHAPTER 1

INTROUCTION
AIM
The main aim of this work is to design an 8051 Microcontroller interfacing and verifying its functional behavior with the help of its simulation results.

BASIC IDEA :
Microprocessors and microcontrollers are widely used in embedded systems products. Microcontroller is a programmable device. A microcontroller has a CPU in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal for many applications in which cost and space are critical. The Intel 8051 is Harvard architecture, single chip microcontroller (C) which was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s and early 1990s, but today it has largely been superseded by a vast range of enhanced devices with 8051-compatible processor cores that are manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies and Maxim Integrated Products. 8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8051 is available in different memory types such as UV-EPROM, Flash and NV-RAM.

1.3 OBJECTIVES INTERFACING :

OF

8051

MICROCONTROLLER

To facilitate the interface between the controller and the MEMORY


Providing the interface between the controller and the ALU

Designing of program counter


Designing of instruction register

1.4 Thesis organization :


8051 controller, Design aspects of controller interfacing, Simulation This project report has been organized into different sections such as results and Implementation of controller. ,

CHAPTER 2

8051-MICROCONTROLLER

2.1 INTRODUCTION :
A microcontroller is an economical computer-on-a-chip built for dealing with specific tasks, such as displaying or receiving information through LEDs or remote controlled devices. The most commonly used set of microcontrollers belong to 8051 Family. 8051 Microcontrollers continue to remain a preferred choice for a vast community of hobbyists and professionals. Through 8051, the world became witness to the most revolutionary set of microcontrollers.

2.2 FEATURES of 8051 :


The main features of 8051 microcontroller are: i. RAM 128 Bytes (Data memory) ii. ROM 4Kbytes (ROM signify the on chip program space) iii. Serial Port Using UART makes it simpler to interface for serial communication.

iv. v.

Two 16 bit Timer/ Counter Input/output Pins 4 Ports of 8 bits each on a single chip.

vi. 6 Interrupt Sources vii. 8 bit ALU (Arithmetic Logic Unit) viii. Bus. ix. 8051 can execute 1 million one-cycle instructions per second with a clock frequency of 12MHz. Harvard Memory Architecture It has 16 bit Address bus (each of RAM and ROM) and 8 bit Data

This microcontroller is also called as System on a chip because it has all the features on a single chip.

2.3 History of 8051 and Key Developments :


Intel Corporation fabricated the 8 bit microcontroller which was referred as MCS-51 in 1981. This microcontroller was also referred as system on a chip because it has 128 bytes of RAM, 4Kbytes of ROM, 2 Timers, 1 Serial port, and four ports on a single chip. The CPU can work for only 8bits of data at a time because 8051 is an 8-bit processor. In case the data is larger than 8 bits then it has to be broken into parts so that the CPU can process conveniently. Most manufacturers have put 4Kbytes of ROM even though the quantity of ROM can be exceeded up to 64 K bytes.

Intel permitted other manufacturers to fabricate different versions of 8051 but with the limitation that code compatibility should be maintained. This has added advantage that if the program is written then it can be used for any version of 8051 despite of manufacturer.

As years passed by, the quality of technology surpassed the expectation of the greatest minds, with gadgets becoming smaller, sleeker and more efficient. Microcontrollers were seen as the

answer to the requirements raised in advanced electronics. This is the reason why manufacturers have now focused their production around the following main developmental aspects: i. ii. iii. iv. v. vi. Ease-of-use Market availability Less power usage Smaller processing power More integrated features like RF and USB Smaller form factors

2.4 8051 Family :


Intel fabricated the original 8051 which is known as MCS-51. The other two members of the 8051 family are: i. 8052 This microcontroller has 256 bytes of RAM and 3 timers. In addition to the standard

features of 8051, this microcontroller has an added 128 bytes of RAM and timer. It has 8K bytes of on chip program ROM. The programs written for projects using 8051 microcontroller can be used to run on the projects using 8052 microcontroller as 8051 is a subset of 8052.

ii.

8031 This microcontroller has all the features of 8051 except for it to be ROM-less. An

external ROM that can be as large as 64 K bytes should be programmed and added to this chip for execution. The disadvantage of adding external ROM is that 2 ports (out of the 4 ports) are used. Hence, only 2 ports are left for I/O operations which can also be added externally if required for execution. Comparison of 8051 family members:

Features RAM(bytes) ROM Timers Serial port I/O pins Interrupt sources

8051 128 4K 2 1 32 6

8052 256 8K 3 1 32 8

8031 128 0K 2 1 32 6

Comparison of 8051 family members

2.5 Various 8051 microcontrollers :


8051 microcontrollers use two different kinds of memory such as UV- EPROM, Flash and NVRAM. Hence 8051 will not be seen in the part number even though it is the most popular member of the 8051 family. i. 8751 This microcontroller is the UV-EPROM version of 8051. This chip has only 4K bytes of UV-EPROM. It is required to have access to the PROM burner and the UV-EPROM eraser to erase the contents inside the chip before it is programmed again. The disadvantage of using this memory is the waiting time of around 20 minutes to erase the contents in order to program it again. Due to this limitation, manufacturers fabricated flash and NV-RAM versions of 8051.

ii. AT89C51 from Atmel Corporation Atmel fabricated the flash ROM version of 8051 which is popularly known as AT89C51 (C in the part number indicates CMOS). The flash memory can erase the contents within seconds which is best for fast growth. Therefore, 8751 is replaced by AT89C51 to eradicate the waiting time required to erase the contents and hence expedite the development time. To build up a microcontroller based system using AT89C51, it is essential to have ROM burner that supports flash memory. Note that in Flash memory, entire

contents must be erased to program it again. The contents are erased by the ROM burner. Atmel is working on a newer version of AT89C51 that can be programmed using the serial COM port of IBM PC in order to get rid of the ROM burner.

iv. One - Time - Programmable (OTP) versions of the 8051 This version of microcontroller is cheaper and available from various manufacturers. The manufacturers use OTP microcontroller for mass production because the price per unit is very cheap.

2.6 Memory Architecture :


The 4 discrete types of memory in 8051 are:
I.

Internal RAM This memory is located from address 0 to 0xff. The memory locations from 0x00 to 0x7F are accessed directly. The bytes from 0x20 to 0x2F are bitaddressable. Loading R0 and R1 the memory location from 0x80 to 0xFF can easily accessed.

ii. Special Function Registers (SFR) Located from address 0x80 to 0xFF of the memory location. The same instructions used for lower half of Internal RAM can be used to access SFRs. The SFRs are bit addressable too. iii. Program Memory This is read only memory which is located at address 0. With the help of 16 bit Special Function Register DPTR, this memory can also save the tables of constants. iv. External Data Memory Located at address 0. The Instruction MOVX (Move

External) should be used to access the external data memory.

2.7 Programming environment and programmer :

Formerly, programmers used machine language for coding. A machine language is a program that consists of 0s and 1s which was very dreary for the humans

program any computer. In due course of time, assembly language was developed in order to speed up the programming and make it error-free. Assembly language is a low level language which uses an assembler to translate the program into machine code. The high level programming languages such as BASIC, Pascal, Forth, C, C++, and Java are available to code the program for 8051. These high level languages make use of a Compiler to translate into machine code. For example, when a program is written in C, the program needs to be translated into machine language using C compiler. Usually, Assembly and C language is widely used for 8051 programs as compared to the other high level languages.

The 8051 provides a total of four ports for I/O operations. 8051 has 40 pins, of which 32 pins are set aside for the four ports. PO, P1, P2, and P3 each have 8 pins and can be used for either input or output. The remaining pins are designated as Vrt, GND, XTAL1, XTAL2, RST, EA, ALE/PROG and PSEN.

8051 allows you to manipulate one or all of the bits of a port, thus providing programmers with a unique and powerful feature. 8051 provides the programmer with the ability to read, write and modify each port to customize applications as much as possible.

CHAPTER 3

BLOCK DIAGRAM

The block diagram of the project is shown in the Figure 3.1.

Figure 3.1 block diagram of the project

Totally this block diagram comprises of four components: ALU INSTRUCTION REGISTER PROGRAM COUNTER MEMORY

3.1 Working of modules

3.1.1 Function of ALU :


The ALU performs both arithmetic and logical operations and as well as control of transfer instructions. It takes data and acc as inputs to generate output according to the opcode. An execlk is given as input for synchronization and the output is available at positive edge of the execlk. It performs arithmetic and logic instructions directly and control of transfer instructions are performed with the help of control and logic decoder.

FLOW CHART FOR IMPLEMENTATION OF ALU

S tart
E n tearc c ,d a ta ,o p c o d e g iv e x e c lk e

P o s itiv e e d g e o fe x e c lk

O p c o =0 0 00 de

A cc 1 = A c c + d a ta

A cc 1 =

3.1.2 Function of accumulator:


The result of an ALU operation is always stored in accumulator at some specified time based on the control logic instruction and also the exe clk. This output is again fed to ALU as input. If Reset =0, the output of accumulator is cleared to zero. When reset is high and load accumulator signal is set high, the output of the ALU is loaded in to the accumulator at the negative edge of the exe clk.

FLOW CHART FOR IMPLEMENTATION OF ACCUMULATOR

Start Input acc1, ldacc,rst ,execlk


Nega tive edge of execl k Rst =0 Y N

stop
Y N ldacc= 1 Y N

stop

acc=0

acc=ac c1

stop

stop

3.1.4 Function of memory:

Inputs Rd

Description Enables the output buffer of the Memory registers and makes the data available on the Data line when Rd=1.Remains in high impedance state when Rd=0. Enables the input buffer of the Memory registers and makes the data available on the Data line when Wr=1.Remains in high impedance state when Wr=0. Carries the address of the Memory location to be Read or Written upon. Description Bi-directional bus that carries all the data from & to the Memory or Instruction register or Accumulator.

Wr

Addr InOut Data

3.1.5 Function of program counter :


The program counter (PC) contains the address of the next instruction. The CPU fetches an instruction from memory, executes it and increments the content of PC. Thus in the next instruction cycle, it will fetch the next instruction of the program pointed out by the program counter. The instructions are executed sequentially unless an instruction changes the content of program counter.

3.1.6 Function of instruction register:

Instruction register is a register which gets loaded with data from the memory. When LdIr signal is high, the data bus contents get loaded into the Instruction register. The MSBs of this loaded data are the Opcode of the Instruction and the remaining bits [are the address of a memory location to fetch the subsequent data.

3. 2 Function of the project


Let us consider an instance when some information is stored in the memory. Now when the system is switched on, CPU is initialized. In order to fetch an instruction, as a result the program goes to the location in the memory that is pointed out by the program counter. After some instance, the instruction from the memory is put on the data bus. This cycle is called the instruction fetch cycle. The instruction is now available at the data bus. At next instance the instruction is loaded into the instruction register. This is called the instruction load. In this cycle the msbs of the instruction are separated and put in the opcode register and are loaded to control unit as well as ALU. The rest of the bits are sent out as Irout. The outputs of the instruction register and the program counter are connected to a mux. During the negative edge of the fetch signal, the output of the instruction register is selected, while the output from the program counter is selected during the positive edge of fetch cycle.

Now when the fetch signal goes low the mux selects the output from the instruction register and it points to the location of the operand. Now the operand present in the location is placed on the data bus. After an instruction is fetched the program counter is incremented. It points to the next location. Now the operand is available at the ALU. The operand is taken in by the ALU and operates on it. Now the result is available at acc1 at positive edge of execlk. During the negative edge of execlk, the result at the Acc1 register is placed on the data bus, which is sent and loaded into the accumulator for any further operations. If the data has to be stored into the memory, then during this clock cycle, Rd and Wr has to be 0 & 1 respectively. As

a result the accumulator is connected to the memory and the value in the accumulator is sent back to a location in the memory through a module named Buffer.

3.3 Pin diagram of the 8051 :

3.3.1 Pin out Description :


Pins 1-8: Port 1 Each of these pins can be configured as an input or an output

.Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to this pin, the program starts execution from the beginning. Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12: INT0 Interrupt 0 input. Pin 13: INT1 Interrupt 1 input. Pin 14: T0 Counter 0 clock input. Pin 15: T1 Counter 1 clock input. Pin 16: WR Write to external (additional) RAM. Pin 17: RD Read from external RAM. Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. Pin 20: GND Ground. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs. Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by

means of only one additional (and cheap) integrated circuit. In other words, this port is used for both data and address transmission. Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists). Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40: VCC +5V power supply.

3.5 Ports :
There are 4 8-bit ports: P0, P1, P2 and P3. PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output port which can be used for a variety of interfacing tasks. The other ports P0, P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage. PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port, but Port P3 has additional functions such as, serial transmit and receive pins, 2 external interrupt pins, 2 external counter inputs, read and write pins for memory access. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory. PORT P2 acts as A8A15, as can be seen from fig 1.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P0 acts as a multiplexed address and data bus that can be used to access external memory in conjunction with

PORT P2. P0 acts as AD0-AD7, as can be seen from fig 1.1

3.6 Addressing modes :


While operating, the processor processes data as per program instructions. Each instruction consists of two parts. One part describes WHAT should be done, while the other explains HOW to do it. The latter part can be a data (binary number) or the address at which the data is stored. Two ways of addressing are used for all 8051 microcontrollers depending on which part of memory should be accessed:

3.7 Direct Addressing modes :


On direct addressing, the address of memory location containing data to be read is specified in instruction. The address may contain a number being changed during operation (variable). For example: Since the address is only one byte in size (the largest number is 255), only the first 255 locations of RAM can be accessed this way. The first half of RAM is available for use, while another half is reserved for SFRs.
MOV A,33h; Means: move a number from address 33 hex. to accumulator

3.8 Indirect Addressing modes :


On indirect addressing, a register containing the address of another register is specified in instruction. Data to be used in the program is stored in the letter register. For example: Indirect addressing is only used for accessing RAM locations available for use (never for accessing SFRs). This is the only way of accessing all the latest versions of the microcontrollers with additional memory block (128 locations of RAM). Simply put, when the program encounters instruction including @ sign and if the specified address is higher than 128 ( 7F hex.), the processor knows that indirect addressing is used and skips memory space reserved for SFRs.
MOV A,@R0; Means: Store the value from the register whose address is in the

R0 register into accumulator

On indirect addressing, registers R0, R1 or Stack Pointer are used for specifying 8-bit addresses. Since only 8 bits are avilable, it is possible to access only registers of internal RAM this way (128 locations when speaking of previous models or 256 locations when speaking of latest models of microcontrollers). If an extra memory chip is added then the 16-bit DPTR Register (consisting of the registers DPTRL and DPTRH) is used for specifying address. In this way it is possible to access any location in the range of 64K.

CHAPTER 4

APPENDIX

VHDL BASICS : 4.1 Introduction


In the mid-1980s, the U.S. Department of defence and the IEEE sponsored the development of a highly capable hardware description language called VHDL. The language has the following features: 1. Design may be decomposed hierarchically. 2. Each design element has both a well Defined interface and a precise behavioral specification 3. Behavioral specifications can use either an algorithm or an actual hardware structure to define an elements operation. 4. Concurrency, timing and clocking can all be modeled. VHDL handles asynchronous as well as synchronous sequential circuit structures. 5. The logical operation and timing behavior of a design can be simulated. Thus VHDL started out as a documentation and modeling language, allowing The behavior of digital system design to be precisely specified and simulated. While the language and simulation environment were important innovations by themselves, VHDLs utility and popularity took a quantum leap with the commercial development of VHDL synthesis tools. These programs can create logic circuit structures directly from VHDL behavioral and

descriptions. Using VHDL, you can design, simulate, and synthesize anything from a simple

combinational circuit to a complete microprocessor system on a chip. VHDL was standardized by the IEEE in 1987 and extended in 1993.

4.2 Design Flow :


There are several steps in the VHDL based design process called design flow. The front- end begins with figuring out the basic approach and building blocks at the block diagram level. The next step is the actual writing of the VHDL code for modules, their interfaces, and their internal details. A VHDL compiler analyzes the code for syntax errors and also checks it for compatibility with other modules on which it relies. A VHDL simulator allows to define and apply inputs to the design and to observe its outputs, without ever having to build the physical circuit. The purpose of simulation is to verify that the circuit works as desired. The backend begins with synthesis, which converts the VHDL description into a set of primitives or components that can be assembled in the target technology. It may generate a list of gates and a net list that specifies how they should be interconnected. In the fitting step, a fitting tool or fitter maps the synthesized primitives or components onto available device resources. The final step is the timing verification of the fitter circuit. It is only at this stage that the actual circuit delays due to wire lengths electrical loading and other factors can be calculated with a reasonable precision.

Fig 4.2.1 Steps in a VHDL Design Flow

Hierarchy/ block diagram Coding Compilatio n

Simulatio n/ Verificatio n

Fitting/ Synthesis Place + Route

Timing Verificatio n

4.3 Program Structure :


VHDL was designed with principles of structured programming. The key idea is to define the interface of a hardware module while hiding its internal details. Thus a VHDL entity is simply a declaration of modules inputs and outputs while VHDL architecture is a detailed description of the modules internal structure or behavior.

Entity declaration

Architecture definition

Fig 4.3.1

4.4 Design styles :


A design can be modeled into three different styles or in a mixed style.These styles are: 1. Behavioral style modeled using procedural constructs. 2. Data flow style - modeled using continuous assignments. 3. Structural style - modeled using gate and module instantiation.

1. Behavioral style
Behavioral representation describes how a particular design should respond to a given set of inputs. Behavior may be specified by Boolean equations, tables of input and output values, or algorithms written in standard high-level computer languages or special Hardware Description Languages (HDLs). VHDLs key element is process. A process is a collection of sequential statements that execute in parallel with other concurrent statements and other processes.

2. Data flow modeling


In complex designs as the number of gates is very large, the designers can design more effectively by implementing the function at a level of abstraction higher than the gate level, data flow modeling. At this level, the module is designed by specifying the dataflow. The designer is aware of how data flows between hardware registers and how the data is processed in the design.

Dataflow modeling provides a powerful way to implement a design. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow.

3. Structural modeling
A VHDL architecture that uses components is called a structural description or structural design because it defines the precise interconnection structure os signals and entities that realize the entity. The most basic of VHDLs structural design is the component statement. Here component is the name of the previously defined entity that is to be instantiated within the architecture body.

4.5 Advantages of VHDL


VHDL offers several advantages to the designer. They are: 1. Standard language 2. Readily available tools 3. Powerful and versatile description language 4. Multiple mechanisms to support design hierarchy 5. Versatile design reconfiguration support 6. Support for multiple levels of abstraction

CHAPTER 5

SOFTWARE
XILING
Xilinx software is used by the VHDL designers for performing Synthesis operation. Any simulated code can be synthesized and configured on FPGA. Synthesis is the transformation of VHDL code into gate level net list. It is an integral part of current design flow .

Algorithm :
Start the ISE Software by clicking the XILINX ISE icon.
Create a New Project and find the following properties displayed.

Create a VHDL Source formatting all inputs, outputs and buffers if required. which provides a window to write the VHDL code, to be synthesized.

Check Syntax after finally editing the VHDL source for any errors. Design Simulation is done after compilation.

CHAPTER 6

SOURCE CODE
----------------ACCUMULATOR
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity accm is port( acc1: in std_logic_vector (31 downto 0); acc: out std_logic_vector (31 downto 0); ldacc,rst,execlk: in bit); end accm;

architecture acc_beh of accm is begin process(rst,execlk,acc1,ldacc) begin if(execlk='1' and execlk'event) then if rst ='0' then ----clock edge ------reset condition

acc<= "00000000000000000000000000000000"; elsif ldacc ='1' then acc<= acc1; end if; end if; end process; end acc_beh ; -----load accumulator

------------------------------------------ALU
library ieee; use ieee.std_logic_1164 .all; use ieee.std_logic_unsigned.all;

entity alu is port(acc: in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0); opcode: in std_logic_vector(3 downto 0); acc1: out std_logic_vector(31 downto 0); execlk:in bit ); end alu;

architecture aluarc of alu is begin process (execlk) begin

if (execlk='1' and execlk'event and execlk'last_value='0') then -----clock edge case (opcode) is when "0000"=> acc1<=acc + data;--add

when "0001"=> acc1<=acc-data; --sub when "0010"=> acc1<=data+1; --inc when "0011"=> acc1<=data-1; --dec when "0100"=> acc1<=acc and data;--and when "0101"=> acc1<=acc or data;--or when "0110"=> acc1<=acc xor data;--xor when "0111"=> acc1<=not data;--not when "1000"=>--ls acc1<=data(30 downto 0) & data(31); when "1001"=>--rs acc1<=data(0) & data(31 downto 1); when "1010"=>--jmp acc1<=acc; when "1011"=> --skip acc1<=acc; when "1100"=>--hlt acc1<=acc; when "1101"=>--ldacc acc1<= data;

when "1110" =>----stracc acc1<=acc; when others=> acc1<=acc;

end case;

end if;

end process;

end aluarc;

-----------------------------------BUFFER
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity buff is port(acc1:in std_logic_vector(31 downto 0); y:in bit; data:out std_logic_vector(31 downto 0)); end buff;

architecture buff1 of buff is

begin process(y,acc1) begin if(y='1')then data<=acc1; end if; end process; end buff1; -----------Buffer action

-----------------INSTRUCTION library ieee; use ieee.std_logic_1164.all;

REGISTER-----------------

use ieee.std_logic_unsigned.all; entity ir is port(data:in std_logic_vector(31 downto 0); ldir,rst:in bit; irout:out std_logic_vector(27 downto 0); opcode:out std_logic_vector(3 downto 0)); end ir;

architecture ir of ir is begin process(ldir,data, rst) begin if(rst='0') then irout<="0000000000000000000000000000"; ---instruc reg

opcode<="1111";

elsif(rst='1' and ldir='1') then irout<= data(27 downto 0); opcode<= data(31 downto 28);

end if; end process; end ir;

-------------------------------MEMORY

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity memy is port(data: in std_logic_vector(31 downto 0); address: in std_logic_vector(27 downto 0); rd, wr : in bit; rst: in bit; data1: out std_logic_vector(31 downto 0)); end memy;

architecture memarch of memy is

type t_mem is array(0 to 255)of std_logic_vector(31 downto 0); signal memory :t_mem; begin

process(rd,wr,address,rst) --type t_mem is array(0 to 255)of std_logic_vector(31 downto 0); --variable memory :t_mem; begin data1<="00000000000000000000000000000000"; memory <=( 0=>"11010000000000000000000001100101", 1=>"00000000000000000000000001100110", 2=>"11100000000000000000000010000000", 3=>"11000000000000000000000001111100", ------instructions

100=>"00000000000000000000000000000000", -------------------memory 101=>"00000000000000000000000000000001", 102=>"00000000000000000000000000000010", 103=>"00000000000000000000000000000011", 104=>"00000000000000000000000000000100", 105=>"00000000000000000000000000000101", 106=>"00000000000000000000000000000110", 107=>"00000000000000000000000000000111", 108=>"00000000000000000000000000001000", 109=>"00000000000000000000000000001001", ------constants start

110=>"00000000000000000000000000001010", 111=> "00000000000000000000000000001011", 112=> "00000000000000000000000000001100", 113=> "00000000000000000000000000001101", 114=> "00000000000000000000000000001110", 115=> "00000000000000000000000000001111", 116=> "00000000000000000000000000010000", 117=> "00000000000000000000000000010001", 118=>"00000000000000000000000000010010", 119=> "00000000000000000000000000010011", 120=> "00000000000000000000000000010100", 121=> "00000000000000000000000000010101", 122=> "00000000000000000000000000010110", 123=> "00000000000000000000000000010111", 124=>"00000000000000000000000000011000", 125=> "00000000000000000000000000011001", --memory data constants end others=>"00000000000000000000000000000000");

if(rst='0')then

-------1

for x in 0 to 105 loop -- memory(150 + x) :="00000000000000000000000000000000" ; memory(150 + x) <="00000000000000000000000000000000" ; end loop; end if; -------1

if(wr='1' and rd='0')

then

---------2

if(conv_integer(address)>150 and conv_integer(address)<=255) then -- memory(conv_integer(address)):=data; memory(conv_integer(address))<=data; end if; end if; if(rd='1' and wr='0') then --------2 --------3

--data <= memory(conv_integer(address)); data1 <= memory(conv_integer(address)); end if; end process; end memarch; -------3

-----------------------------------MUX
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity mux is port(irout:in std_logic_vector(27 downto 0); pcout:in std_logic_vector(27 downto 0); fetch:in bit; addr:out std_logic_vector(27 downto 0) ); end mux;

architecture mux1 of mux is

--

signal fetch1:bit; begin

--

fetch1<=not fetch ;

-- addr<=pcout after 0ns when fetch='0' and fetch1='1' else -------pcout selected --irout after 0ns when fetch='1' and fetch1='0' else ------irout selected

process(fetch,irout,pcout) begin

--if(fetch='1' and fetch1='0')then if(fetch='1')then addr<=pcout; else --elsif(fetch='0' and fetch1='1')then addr<=irout; end if; end process;

end mux1;

-------------------------------PROGRAM COUNTER
library ieee; use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

entity pc11 is port ( fetch,ldpc,incpc: in bit; irout: in std_logic_vector(27 downto 0); pcout : out std_logic_vector(27 downto 0)); end pc11;

architecture pc2 of pc11 is signal pc3: std_logic_vector(7 downto 0):="00000000"; --- signal fetch1:std_logic; begin --fetch1<= not fetch; -- fetch1<= not fetch; process(fetch,incpc) variable t:std_logic_vector(27 downto 0):="0000000000000000000000000000"; begin if (fetch = '1' and fetch'event) then --pcout<=(others=>'0'); if (incpc='1')then if(pc3 = "11111111") then pc3<="00000000"; t:= "00000000000000000000" & pc3; pcout<=t; -- trigger on clock changes

-- pcout<="0000000000000000000000000000"; trailing-edge triggered. else pc3<= pc3 + "00000001"; t:="00000000000000000000" & pc3; pcout<=t;

--changed to

--pcout<="00000000000000000000000" & pc3; end if; else pcout<=t; end if; else if(fetch='0' and fetch'event)then if(ldpc='1')then pcout<=irout; -- pc3<=irout(4 downto 0); end if; end if; end if; end process; -------------changed

-- process(fetch,ldpc) --variable fetch1:std_logic; --fetch1:=not fetch; -begin --fetch1:=not fetch;

--

if(fetch='0' and fetch'event)then

--if(ldpc='1') then -- pcout<=irout; --end if; -pcout<=""&pc1;

--pcout<="00000000000000000000000" & pc3; -end if; -- end if; -end process;

end pc2;

--------------------------------------CONTROL
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity ctr is

port(fetch : in bit; opcode:in std_logic_vector(3 downto 0); ldir,ldacc,incpc,ldpc,rd,wr,y: out bit; rst: buffer bit); end ctr;

architecture ctr1 of ctr is

begin

incpc<='0' when op code="1011" else '1' ; rd<='0' when op code ="1110" else '1' ; wr<= '1' when op code<="1110" else --sta '0' ; ldacc<='1' when oPcode<="1101" else --ldacc '0'; y<='1' when opcode="1110" else --sta '0'; ldir<= not fetch; --fetch ldpc<='1' when opcode="1010" else --jmp '0' ; rst<='0' when op-code="1100" else '1'; --hlt

end ctr1;

CHAPTER 7

ACCUMULATER:

ALU :

BUFFER :

INSTRUCTION REGISTOR :

MEMORY:

MUX :

PROGRAM COUNTER :

CONTROL :

CHAPTER 8

Advantages of 8051 microcontroller :


More speed

Less power requirement Safe and secure


microcontrollers are used to regulate the brakes on all four wheels,

or a microcontroller to regulate the car air conditioning, or a microcontroller responsible for the cruise control .
Lowest The interfacing of 8051 microcontroller is simple .

The 8051 microcontroller interfacing is having High speed and Low programming overhead.
By using interfacing of 8051 microcontroller implementation of software and hardware is

easy .
Implementation is easy .

Disadvantages of 8051 microcontroller :


Complexity of the circuit board increases. Cost increases. Flexibility decreases
Low speed for long distance, 115200 should be achieved with small microcontrollers

using short distances

CHAP TER9

APPLICATIONS

The 8051 has been in use in a wide number of devices, mainly because it is easy to integrate into a project or build a device around. The following are the main areas of focus: i. Energy Management: Efficient metering systems help in controlling energy usage in homes and industrial applications. These metering systems are made capable by incorporating microcontrollers.

ii.

Touch screens: A high number of microcontroller providers incorporate touch-sensing capabilities in their designs. Portable electronics such as cell phones, media players and gaming devices are examples of microcontroller-based touch screens.

iii.

Automobiles: The 8051 finds wide acceptance in providing automobile solutions. They are widely used in hybrid vehicles to manage engine variants. Additionally, functions such as cruise control and anti-brake system have been made more efficient with the use of microcontrollers.

iv.

Medical Devices: Portable medical devices such as blood pressure and glucose

monitors use microcontrollers will to display data, thus providing higher reliability in providing medical results .

Future scope
In future there is a chance to interface some more devices with this controller without degrading the speed.

C HAPTER 10

CONCLUSION

In this work, initially the investigation on the 8051controller and their interfaces is carried out and its working is identified based on which the block diagram and the specifications are developed for designing the modules using VHDL. The basic aim of our project is to model the memory, program counter, instruction register designs using VHDL Language. The simulation results shows that the behavior of each and every module separately. In this project, 8051 Microcontroller is implemented in Xilinx 9.2i .VHDL coding for the controller and their interfacing modules was done successfully.

Appendix

VHDL BASICS

A.1 Introduction
In the mid-1980s, the U.S. Department of defence and the IEEE sponsored the development of a highly capable hardware description language called VHDL. The language has the following features: 1. Design may be decomposed hierarchically. 2. Each design element has both a well Defined interface and a precise behavioral specification 3. Behavioral specifications can use either an algorithm or an actual hardware structure to define an elements operation. 4. Concurrency, timing and clocking can all be modeled. VHDL handles asynchronous as well as synchronous sequential circuit structures. 5. The logical operation and timing behavior of a design can be simulated. Thus VHDL started out as a documentation and modeling language, allowing The behavior of digital system design to be precisely specified and simulated. While the language and simulation environment were important innovations by themselves, VHDLs utility and popularity took a quantum leap with the commercial development of VHDL synthesis tools. These programs can create logic circuit structures directly from VHDL behavioral and

descriptions. Using VHDL, you can design, simulate, and synthesize anything from a simple

combinational circuit to a complete microprocessor system on a chip. VHDL was standardized by the IEEE in 1987 and extended in 1993.

A.2 Design Flow


There are several steps in the VHDL based design process called design flow. The frontend begins with figuring out the basic approach and building blocks at the block diagram level. The next step is the actual writing of the VHDL code for modules, their interfaces, and their internal details. A VHDL compiler analyzes the code for syntax errors and also checks it for compatibility with other modules on which it relies. A VHDL simulator allows to define and apply inputs to the design and to observe its outputs, without ever having to build the physical circuit. The purpose of simulation is to verify that the circuit works as desired. The backend begins with synthesis, which converts the VHDL description into a set of primitives or components that can be assembled in the target technology. It may generate a list of gates and a net list that specifies how they should be interconnected. In the fitting step, a fitting tool or fitter maps the synthesized primitives or components onto available device resources. The final step is the timing verification of the fitter circuit. It is only at this stage that the actual circuit delays due to wire lengths electrical loading and other factors can be calculated with a reasonable precision.

Fig A.2.1 Steps in a VHDL Design Flow

Hierarchy/ block diagram Coding Compilatio n

Simulatio n/ Verificatio n

Fitting/ Synthesis Place + Route

Timing Verificatio n

A.3 Program Structure


VHDL was designed with principles of structured programming. The key idea is to define the interface of a hardware module while hiding its internal details. Thus a VHDL entity is simply a declaration of modules inputs and outputs while VHDL architecture is a detailed description of the modules internal structure or behavior.

Entity declaration

Architecture definition

Fig A.3.1

A.4 Design styles


A design can be modeled into three different styles or in a mixed style.These styles are: 1. Behavioral style modeled using procedural constructs. 2. Data flow style - modeled using continuous assignments. 3. Structural style - modeled using gate and module instantiation.

1. Behavioral style
Behavioral representation describes how a particular design should respond to a given set of inputs. Behavior may be specified by Boolean equations, tables of input and output values, or algorithms written in standard high-level computer languages or special Hardware Description Languages (HDLs). VHDLs key element is process. A process is a collection of sequential statements that execute in parallel with other concurrent statements and other processes.

2. Data flow modeling


In complex designs as the number of gates is very large, the designers can design more effectively by implementing the function at a level of abstraction higher than the gate level, data flow modeling. At this level, the module is designed by specifying the dataflow. The designer is aware of how data flows between hardware registers and how the data is processed in the design.

Dataflow modeling provides a powerful way to implement a design. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow.

3. Structural modeling
A VHDL architecture that uses components is called a structural description or structural design because it defines the precise interconnection structure os signals and entities that realize the entity. The most basic of VHDLs structural design is the component statement. Here component is the name of the previously defined entity that is to be instantiated within the architecture body.

A.5 Advantages of VHDL


VHDL offers several advantages to the designer. They are: 1. Standard language 2. Readily available tools 3. Powerful and versatile description language 4. Multiple mechanisms to support design hierarchy 5. Versatile design reconfiguration support 6. Support for multiple levels of abstraction

Xilinx
Xilinx software is used by the VHDL designers for performing Synthesis operation. Any simulated code can be synthesized and configured on FPGA. Synthesis is the transformation of VHDL code into gate level net list. It is an integral part of current design flows.

Algorithm Start the ISE Software by clicking the XILINX ISE icon.
Create a New Project and find the following properties displayed.

Create a VHDL Source formatting all inputs, outputs and buffers if required. which provides a window to write the VHDL code, to be synthesized.

Check Syntax after finally editing the VHDL source for any errors. Design Simulation is done after compilation.

Pin diagram of the 8051

Pinout Description
Pins 1-8: Port 1 Each of these pins can be configured as an input or an output. Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to this pin, the program starts execution from the beginning. Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12: INT0 Interrupt 0 input. Pin 13: INT1 Interrupt 1 input. Pin 14: T0 Counter 0 clock input. Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM. Pin 17: RD Read from external RAM. Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. Pin 20: GND Ground. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs. Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one additional (and cheap) integrated circuit. In other words, this port is used for both data and address transmission. Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists). Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40: VCC +5V power supply.

Ports

There are 4 8-bit ports: P0, P1, P2 and P3. PORT P1 (Pins 1 to 8): The port P1 is a general purpose input/output port which can be used for a variety of interfacing tasks. The other ports P0, P2 and P3 have dual roles or additional functions associated with them based upon the context of their usage. PORT P3 (Pins 10 to 17): PORT P3 acts as a normal IO port, but Port P3 has additional functions such as, serial transmit and receive pins, 2 external interrupt pins, 2 external counter inputs, read and write pins for memory access. PORT P2 (pins 21 to 28): PORT P2 can also be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P2 will act as an address bus in conjunction with PORT P0 to access external memory. PORT P2 acts as A8A15, as can be seen from fig 1.1 PORT P0 (pins 32 to 39) PORT P0 can be used as a general purpose 8 bit port when no external memory is present, but if external memory access is required then PORT P0 acts as a multiplexed address and data bus that can be used to access external memory in conjunction with PORT P2. P0 acts as AD0-AD7, as can be seen from fig 1.1

Addressing modes
While operating, the processor processes data as per program instructions. Each instruction consists of two parts. One part describes WHAT should be done, while the other explains HOW to do it. The latter part can be a data (binary number) or the address at which the data is stored. Two ways of addressing are used for all 8051 microcontrollers depending on which part of memory should be accessed:

Direct Addressing modes


On direct addressing, the address of memory location containing data to be read is specified in instruction. The address may contain a number being changed during operation (variable). For example: Since the address is only one byte in size (the largest number is 255), only the first 255 locations of RAM can be accessed this way. The first half of RAM is available for use, while another half is reserved for SFRs.
MOV A,33h; Means: move a number from address 33 hex. to accumulator

Indirect Addressing modes


On indirect addressing, a register containing the address of another register is specified in instruction. Data to be used in the program is stored in the letter register. For example:

Indirect addressing is only used for accessing RAM locations available for use (never for accessing SFRs). This is the only way of accessing all the latest versions of the microcontrollers with additional memory block (128 locations of RAM). Simply put, when the program encounters instruction including @ sign and if the specified address is higher than 128 ( 7F hex.), the processor knows that indirect addressing is used and skips memory space reserved for SFRs.
MOV A,@R0; Means: Store the value from the register whose address is in the R0 register into accumulator

On indirect addressing, registers R0, R1 or Stack Pointer are used for specifying 8-bit addresses. Since only 8 bits are avilable, it is possible to access only registers of internal RAM this way (128 locations when speaking of previous models or 256 locations when speaking of latest models of microcontrollers). If an extra memory chip is added then the 16-bit DPTR Register (consisting of the registers DPTRL and DPTRH) is used for specifying address. In this way it is possible to access any location in the range of 64K.