Fully-Integrated Charge Pumps Without Oxide Breakdown Limitation

Jingqi Liu, Younis Allasasmeh, and Stefano Gregori

School of Engineering, University of Guelph Guelph, Ontario, N1G 2W1, Canada Email: jingqi@uoguelph.ca, yallasas@uoguelph.ca, sgregori@uoguelph.ca

AbstractThis paper considers the design of fully-integrated charge pumps whose output voltage is not capped by the main device voltage limitations such as oxide breakdown. The proposed solutions, which do not need dedicated high-voltage fabrication processes, are compared to conventional circuits with same area occupation and are evaluated through simulations.

oxide BD

p+
junction BD

PT n-well

p+

n+

I. I NTRODUCTION As integrated-circuit technology progresses, the reduction of the minimum channel length of MOS devices is accompanied by lower power-supply voltages (VDD ) and thinner gate oxides (tox ). Since VDD is getting lower and lower, an increasing number of functions require higher voltage levels (e.g. program circuits for Flash memories and drivers for displays and loudspeakers). The simplest way to generate such voltages on chip in a digital CMOS technology is by means of integrated charge pumps (CPs), i.e. voltage multipliers based on switches and capacitors. At the same time, the down-scaling of tox increases the oxide leakage currents and lessens the oxide breakdown voltage, which in turn limits the maximum voltages that can be safely generated on chip by conventional CPs. To overcome the oxide breakdown limitation of standard MOS devices, CPs can be integrated using a fabrication process with high-voltage devices [1], where MOS devices with thicker oxide layer are created using an extra photolithography mask. Besides the added fabrication cost, high-voltage MOS devices have worse performance. As an example, highvoltage MOS capacitors have a lower specic capacitance and therefore require a larger area. CPs based on latched voltage doublers and metal-metal capacitors can avoid the oxide breakdown limitation and be built exclusively with low-voltage devices [2]. However, the specic capacitance of metal-metal structures is low in conventional fabrication technologies, because metal interconnections are required to have minimal capacitive couplings. Such constraint restricts the capacitance that can be integrated in a reasonable silicon area and ultimately limits the CP driving capability. The CPs considered in this paper use only low-voltage devices and their maximum output voltage is not limited by the oxide breakdown voltage of transfer capacitors and MOS switches. The circuits are based on a voltage doubler conguration [3] and on a Cockcroft-Walton conguration [4]. Performance is compared in terms of output resistance considering same number of stages and same area occupation.

p-substrate

junction BD

Fig. 1.

Types of breakdown in a PMOS device.

II. VOLTAGE L IMITS

IN I NTEGRATED

C HARGE P UMPS

A. Voltage Limits in MOS Devices The basic types of breakdown (BD) in a MOS structure are shown in Fig. 1. Punchthrough (PT) occurs in devices with relatively short channel when the source-drain voltage increases to the point that the depletion region surrounding the drain extends to the source. Gate oxide BD happens at an electric eld across the gate of about 6108 V/m to 7108 V/m. The source-gate BD voltage is independent of the channel length and can be increased only with a thicker oxide. Junction BD between n-doped and p-doped regions, such as between n-well and p+ diffusions and between n-well and p-substrate, can be caused by Zener effect (in heavily doped junctions) and avalanche breakdown (in lightly doped junctions). PT, oxide BD, and well-diffusion junction BD (Zener) happen at lower voltages than the well-substrate junction BD (avalanche). Therefore, the main voltage limitations in MOS devices concern the maximum source-gate voltage (due to oxide BD, typically being the dominant limitation), the maximum source-drain voltage (due to PT), and the maximum well-drain and well-source voltages (due to junction BD). The maximum well-substrate voltage is a less stringent limitation because of the lighter doping levels. B. Conventional Designs In CPs based on latched voltage doublers [3], the maximum voltage across any switch is VDD (for any number of stages). Thus, low-voltage CMOS transistors (with fast switching time and low on resistance) can be used without limiting the output voltage in triple-well process [2]. However, transfer capacitors sustain voltages higher than VDD (depending on the number

CCECE 2011 Niagara Falls, Canada 978-1-4244-9789-8/11/$26 2011 IEEE

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VDD 2 PD 2

VDD PD C1 N1 VDD VO IO IO VDD 1 PD' C1' N1' P1' C2' N 2' P2' VO P1 C2 N2 P2

1 0

ND N1 VDD

C1 P1 N2

C2 P2

1 0

ND

driver

driver

VDD PD'

N1'

P1' C1'

N 2'

P2' C2'

2 0

ND'

1st stage

2nd stage

2 0

ND'

Fig. 2.

Integrated voltage-doubler CP (n = 2 stages).

Fig. 3.

Integrated Cockcroft-Walton CP (n = 2 stages).

of stages) and are typically built using high-voltage devices with thicker oxides or metal-metal structures. In any case, the silicon area for obtaining the same total capacitance is larger than when using low-voltage devices. In heap CPs [5], the maximum voltage across any transfer capacitor is VDD (for any number of stages). In this case, low-voltage MOS capacitors (with high specic capacitance) can be used without limiting the output voltage [6]. However, transistors experience voltages higher than VDD and must be built using high-voltage devices to extend voltage range. In this paper, we target CPs where the maximum voltage across any switch and any capacitor is not higher than VDD so that the main MOS device voltage limitations (such as oxide BD) do not cap the maximum output voltage. Leakage currents as well as stress are reduced because of the low voltages (i.e. not higher than VDD ) applied to individual devices. This in turn contributes to better conversion efciency and overall reliability. III. P ROPOSED S OLUTIONS A. Voltage Doubler The output voltage of a CP based on n voltage-doubler stages (Fig. 2) can be described by VO = (n + 1) VDD RO IO , (1)

is inversely proportional to the total capacitance CT and the switching frequency f of the two non-overlapping phases 1 and 2 (and their complements 1 and 2 ). The total capacitance that can be built within a given area A using low-voltage MOS capacitors is ox CT = (3) A, tox where ox is the permittivity of the silicon oxide. The capacitors of a CP with n stages have to sustain a maximum voltage of n VDD . If tox is the oxide thickness suitable for sustaining VDD in low-voltage devices, we can assume that the oxide thickness required to build a CP with n stages has to be increased by a factor n (i.e. using appropriate high-voltage devices). In this case, the capacitance that can be built in the same area is at most ox C CT = A= T (4) n tox n and the corresponding CP output resistance, RO = n3 , f CT (5)

grows with n3 (i.e. the area is kept constant at A = CT tox /ox ). To avoid the use of high-voltage structures, the capacitors can be realized with standard low-voltage MOS devices in series to reduce the voltage across each element. For example, the i-th stage must use i2 unit capacitors to sustain a voltage i VDD with a capacitance equal to the other stages, consequently n the total number of capacitors is i=1 i2 . In this case, the CP output resistance is RO = n2 (2n2 + 3n + 1) , 6 f CT (6)

where RO is the equivalent output resistance and IO is the load current. Such formula applies in static conditions (i.e. VDD and IO constant) and under the slow-switching assumption (i.e. switching period much larger than time constants due to capacitances and resistances of integrated components and interconnects). The output resistance is a key factor when considering the performance of a CP and must be kept as low as possible. The output resistance of the voltage-doubler CP, n2 RO = , f CT (2)

when the area is kept constant at A = CT tox /ox .

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RO f CT 500 VD thick ox VD series cap 400 CW

300

and, as a consequence, have a very low specic capacitance which lead to a high output resistance. In this case, the CW CP based on low-voltage devices is an attractive solution, which has a lower output resistance when compared to the voltagedoubler CP based on series capacitors. IV. S IMULATION R ESULTS We designed voltage doubler and CW CPs with n = 2 and n = 3, using a standard 0.18-m CMOS technology and different capacitor structures. The chosen technology does not favor either circuit topology and allows a fair comparison. The bulks of MOS switches are individually biased using triple-well structures [2]. Transfer capacitors for CW CPs are always implemented with low-voltage NMOS devices. Voltage doubler capacitors are implemented with thicker oxide devices (i.e. metal-metal) or low-voltage NMOS devices in series because they have to withstand a voltage higher than VDD . All results are at the same area occupation and VDD = 1.2 V. The total equivalent capacitances and the switching frequencies used in simulations are shown in Table I. The metal-metal capacitors are constructed in an interleaved conguration which maximizes the capacitance per unit area and uses all 6 metal layers. In addition, such capacitors have low series resistance and time constant (e.g. the resistivity of metal 1 is about 100 times smaller than that of the polysilicon layer) and can operate at higher frequencies [2]. For the 2-stage voltage doubler with metal-metal capacitors, the switching frequency can be increased to fdm = 40 MHz to achieve the same output resistance as the CW CP. In contrast, MOS capacitors have series resistance associated with polysilicon gate and channel resistance, which increases the intrinsic time constant and limits the maximum switching frequency. However, higher frequency means more energy lost during transitions of the switching and the amount of electromagnetic interference will be more pronounced.
TABLE I E QUIVALENT C APACITANCES AND S WITCHING F REQUENCIES
CW CP (n = 2) Voltage Doubler (series cap, n = 2) Voltage Doubler (metal cap, n = 2) CW CP (n = 3) Voltage Doubler (series cap, n = 3) Total Capacitance 300 pF 120 pF 7.2 pF 300 pF 62 pF Switching Frequency 2.5 MHz 2.5 MHz 40 MHz 2.5 MHz 2.5 MHz

200

100

Fig. 4. Normalized output resistance (RO f CT ) as a function of the number of stages (n) for the following circuits: voltage-doubler CP with increased tox (VD thick-ox), voltage-doubler CP with series capacitors (VD series-cap), and Cockcroft-Walton CP (CW).

B. Cockcroft-Walton Charge Pump The success of the Cockcroft-Walton (CW) conguration is due to the fact that the voltage across any device does not exceed the input voltage (e.g. VDD ), therefore the circuit can safely generate very high voltages [4]. In the integrated implementation with latched MOS switches [7], the oxide breakdown limitation is avoided and, with triple-well processes, the only limitation is the relatively high BD voltage between well and substrate. The output voltage of a CW conguration with n stages (Fig. 3) is described by the same relation (1) as for the voltage-doubler CP. However, while for the voltage-doubler CP the output resistance is minimized for a given area when all capacitors are equal, in the CW conguration the output resistance is minimized by using a known procedure [8]. In this case, the output resistance can be expressed in terms of transfer capacitors Ci (with i = 1, . . . , n) as follows
n

RO =
i=1

(n + 1 i)2 . f Ci

(7)

To minimize RO for a constant total capacitance CT , we n combine (7) and the constraint CT = Ci , we set the i=1 partials with respect to Ci equal to zero, and we obtain that the optimal capacitance of each stage is

Ci =

n+1i C , n (n + 1) T

(8)

where C1 indicates any of the two capacitors of the rst stage (i.e. next to the input) and Cn indicates any of the two capacitors of the last stage (i.e. next to the output). The corresponding optimized output resistance is RO = n2 (n + 1)2 . 4 f CT (9)

As shown in Fig. 4, the output resistance of the voltagedoubler CP is lower when tox is scaled with n, as RO grows with n3 according to (5). However, the high-voltage devices come at an extra fabrication cost and solutions based on metalmetal capacitors typically involve a much larger tox than the minimum needed to overcome the oxide breakdown limitation

Fig. 5 shows the output characteristics and the conversion efciencies of the 2-stage CW and voltage doubler CPs. The voltage doubler CP with series capacitors has an output resistance of 12.8 k, which is higher than that of the CW CP (11.6 k), because the series capacitors of the voltage doubler CP have a lower equivalent capacitance. The output voltages of the CPs differ from the ideal values due to parasitic capacitances expressed by the parameters and , which give the stray capacitances Ci (between bottom plate and substrate) and Ci (between top plate and substrate) associated with any capacitor Ci . Moreover, the output voltage of the voltage doubler CP (metal-metal) is reduced by 14% compared

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4 3.5 3 Output voltage (V) 2.5 2 1.5 1 0.5 0 0 0.9 0.8 20 40 60 80 100 120

5 4.5 4 Output voltage (V) 3.5 3 2.5 2 1.5 1 0.5 0 0 0.7 0.6 10 20 30 40 50 60

voltage_doubler_3_stage_series_cap
CW_3_stage

voltage_doubler_2_stage_metal_cap voltage_doubler_2_stage_series_cap CW_2_stage

0.7 Conversion efficiency 0.6 0.5 0.4 0.3 0.2 0.1 0 0 20 40 60 Load current (A) 80 100 120

Conversion efficiency

0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 Load current (A) 40 50 60

voltage_doubler_3_stage_series_cap CW_3_stage

voltage_doubler_2_stage_metal_cap voltage_doubler_2_stage_series_cap
CW_2_stage

Fig. 5. Output characteristics and conversion efciencies of 2-stage CW CP, 2-stage voltage doubler CP with thicker oxide capacitor (metal-metal) and 2-stage voltage doubler CP with series low-voltage capacitors, with CT cw = 300 pF, CT dm = 7.2 pF, CT ds = 120 pF, fcw = 2.5 MHz, fdm = 40 MHz, fds = 2.5 MHz and VDD = 1.2 V. All CPs occupy the same area.

Fig. 6. Output characteristics and conversion efciencies of 3-stage CW CP and 3-stage voltage doubler CP with series low-voltage capacitors, with CT cw = 300 pF, CT ds = 62 pF, fcw = 2.5 MHz, fds = 2.5 MHz and VDD = 1.2 V. All CPs occupy the same area.

to the CW CP, because and of metal-metal capacitors are higher than for low-voltage NMOS capacitors. In addtion, the parasitic capacitances Ci and Ci increase as the distance between utilized metal layers and substrate decreases (e.g. for metal 1-metal 2 capacitors is about 1 and for metal 2metal 3 capacitors is about 0.5). However, the lower metal layers need to be used to achieve higher capacitances even though high and are introduced. The conversion efciency is calculated in steady-state conditions as the average output power divided by the average input power. The maximum efciencies of CW CP, voltage doubler CP with series capacitors, and voltage doubler CP with metalmetal capacitors are 79%, 75%, and 49%. The efciencies decline at high load current due to the increasing resistive loss 2 (IO RO ). The low efciency of the voltage doubler (metalmetal) CP is due to the larger and associated with the metal-metal capacitors, which increase switching losses. Fig. 6 shows the output characteristics and the conversion efciencies of the 3-stage CW and voltage doubler (series capacitors) CPs. The output resistances of the CW and voltage doubler CPs are 45.8 k and 53.9 k, and the maximum efciencies are 65% and 61%. Both output resistance and efciency of the voltage doubler CP are worse than the CW CP, because the total equivalent capacitance of the conguration based on series capacitors is reduced. Moreover, as n increases, the difference in output resistances between voltage doubler and CW CPs gets even larger, because the capacitance of series capacitors decreases dramatically when keeping the same area occupation (RO of the voltage doubler CP with series capacitors is 10.3% higher than CW CP at n = 2, and 17.7% higher at n = 3).

V. C ONCLUSION In this paper, we studied fully integrated CPs that generate voltages higher than the power-supply voltage without the need of high-voltage devices. Particularly, the CW CP can operate without exceeding breakdown voltages of both transfer capacitors and MOS switches. The verication of the proposed solutions conducted through simulations shows that CW CPs made only with low-voltage devices have a competitive performance compared to conventional designs with same area occupation. R EFERENCES
[1] D. Baderna, A. Cabrini, G. Torelli, M. Pasotti, Efciency comparison between doubler and Dickson charge pumps, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 2, pp. 1891-1894. [2] R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, P. L. Rolandi, Power efcient charge pump in deep submicron standard CMOS technology, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1068-1071, Jun. 2003. [3] R. Gariboldi, F. Pulvirenti, A 70 m intelligent high side switch with full diagnostics, IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 915923, Jul. 1996. [4] J. D. Cockcroft, E. T. S. Walton, Further developments on the method of obtaining high-velocity positive ions, in Proc. Roy. Soc., London, U.K., 1932, vol. 131, pp. 619-630. [5] M. Mihara, Y. Terada, M. Yamada, Negative heap pump for low voltage operation Flash memory, in Dig. Tech. Papers Symp. VLSI Circuits, 1996, pp. 76-77. [6] R. Arona, E. Bonizzoni, F. Maloberti, G. Torelli, Heap charge pump optimisation by a tapered architecture, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 2, pp. 1903-1906. [7] R. Zhang, Z. Huang, Y. Inoue, A low breakdown-voltage charge pump based on Cockcroft-Walton structure, in Proc. IEEE Int. Conf. ASIC, 2009, pp. 328-331. [8] M. D. Seeman, S. R. Sanders, Analysis and optimization of switched capacitor DC-DC converters, IEEE Trans. Power Electronics, vol. 23, n. 2, pp. 841-851, Mar. 2008.

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