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s Typical power dissipation 145 mW s Count frequency 42 MHz
Ordering Code:
Order Number DM7490AN Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
DS006533
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DM7490A
Function Tables
BCD Count Sequence (Note 1) Outputs QD L L L L L L L L H H QC L L L L H H H H L L QB L L H H L L H H L L QA L H L H L H L H L H
Logic Diagram
Count 0 1 2 3 4 5 6 7 8 9
Count 0 1 2 3 4 5 6 7 8 9
Outputs R9(2) X L H L X L X QD L L H QC L L L QB L L L QA L L H
R0(2) H H X L X X L
R9(1) L X H X L X L
The J and K inputs shown without connection are for reference only and are functionally at a HIGH level.
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DM7490A
65C to +150C
0.8
16 32 16
DC Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current Conditions VCC = Min, II = 12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max (Note 6) VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 7) VCC = Max (Note 8) A Reset B A Reset B 18 29 2.4 3.4 0.2 0.4 1 80 40 120 3.2 1.6 4.8 57 42 mA mA mA A Min Typ (Note 5) Max 1.5 Units V V V mA
Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: QA outputs are tested at I OL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 7: Not more than one output should be shorted at a time. Note 8: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
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DM7490A
AC Switching Characteristics
at VCC = 5V and TA = 25C Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output From (Input) To (Output) A to QA B to QB A to QA A to QA A to QD A to QD B to QB B to QB B to QC B to QC B to QD B to QD SET-9 to QA, QD SET-9 to QB, QC SET-0 Any Q RL = 400, CL = 15 pF Min 32 16 16 18 48 50 16 21 32 35 32 35 30 40 40 Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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