Development of a Single-Stage Three-Phase PV Module

Integrated Converter
Benjamin Sahan, Antonio Notholt-Vergara, Alfred Engler, Peter Zacharias
Institut f ur Solare Energieversorgungstechnik, ISET e.V.
K onigstor 59, D-34119
Kassel, Germany
Phone: +49 561 7294127
Fax: +49 561 7294400
Email: bsahan@iset.uni-kassel.de
URL: http://www.iset.uni-kassel.de
Acknowledgments
The authors would like to thank the European Commission for their support in the project PV-MIPS
(Contract No. TREN/04/FP6EN/S07.34959/503123). It should be noted that this article reects only
the authors views and the European Commission is not liable for any use that may be made of the
information contained therein.
Keywords
Current source inverter (CSI), Photovoltaic, Renewable energy systems, Three-phase system, Efciency.
Abstract
A transformerless three-phase power conditioning unit interfacing with a high voltage (>200V) pho-
tovoltaic module is presented. The chosen topology, a Current Source Inverter, features a single-stage
power conversion system that feeds directly into the grid. A robust and highly efcient laboratory proto-
type of a Module Integrated Converter has been implemented and demonstrated by experimental results.
Introduction
In grid-connected photovoltaic applications central and string inverters are the most commonly used
system congurations. By integrating the inverter into the PV module and generating a grid compliant
ac output current several system advantages can be achieved [1],[2],[3]:
Ease of installation through exible PV system design, offering plug and play features
PV system redundancy in case of inverter failure
No module mismatch losses due to shading or alignment in different angles due to individual
Maximum Power Point Tracking (MPPT)
No DC cabling
Possible mass production through high quantities and standardised components
Despite the benets of so called Module Integrated Converters (MICs) and several research efforts this
concept was not commercially successful yet [5]. For the most part, this is due to low reliability, high
cost, complexity or poor efciency of the existing devices. Given that a PV system should have a lifespan
of >20 years, reliability is a key issue, especially when module integration is concerned. High peak
temperature stress and thermal cycling requires a highly robust design. Electrolytic capacitors, widely
used in single-phase MICs were identied as one of the critical points of failure [1],[4]. While the latest
commercial inverter designs reach 98% efciency [5], state-of-the-art MICs could not compete in this
aspect yet [1].
Within the integrated EU funded project PV-MIPS (Photovoltaic Module with Integrated Power Con-
version System) a robust and highly efcient MIC is being designed which feeds directly into a three-
phase grid [2], [6].
Basic system design
Approach
Previous approaches for the design of MICs were mainly based on the existing types of PV modules
and the utilization of single-phase systems for small power ranges. To overcome these constraints this
development is based on a three-phase grid connection and on customised high voltage modules:
By three-phase grid connection and thus continuous power ow from the module, energy storage
at the dc-link can be drastically reduced. Susceptible electrolytic capacitors are not needed. They
are one main factor in terms of lifetime limitation, today.
By using a high voltage PV module (> 200V) tailored for delivering an output voltage sufcient
to feed into the grid, no step-up transformer is necessary. This reduces costs as well as losses. To
achieve a high module voltage the main attention is directed towards thin lm technologies where
a structuring of the module in small elementary cells is easily possible. Series connection of these
cells inside the module provides voltages of several hundreds volts [2], [3].
Properties of high voltage PV modules
The output voltage of a PV module has approximately a linear relationship to its temperature given by
the thermal coeffcient . Since is negative the output voltage of a PV module rises with decreasing
module temperatures. When a certain minimal MPP voltage V
MPP
is required for full load operation at
70-80C, the worst case output voltage can occur at open circuit and low temperature (see Fig.1). The
module should be designed in a way that its voltage does not cross certain thresholds.
200 300 400 500 600 700 800
200
400
600
800
1000
1200
1400
V
MPP
Maximum power point voltage [V] at 80C
V
O
C
,
m
a
x

O
p
e
n

c
i
r
c
u
i
t

v
o
l
t
a
g
e

[
V
]
25C(STC)
10C
30C
3) V
CE,max

2) V
pv
<1kV
1) V
CE,rec

Figure 1: Maximum open circuit voltage V
OC,max
of
high voltage CIS PVmodule at different operating tem-
peratures vs. V
MPP
, = -0,0029/C
1
158
968
1212
941
662
441
225
34
0
0
200
400
600
800
1000
1200
1400
-
2
0

t
o

-
1
0
-
1
0

t
o

0
0

-

1
0
1
0

-

2
0
2
0

-
3
0
3
0

-

4
0
4
0

-

5
0
5
0

-

6
0
6
0

-

7
0
7
0

-

8
0
Module temperatures [C]
O
p
e
r
a
t
i
n
g

h
o
u
r
s

[
h
]
Figure 2: Temperature measurement of a CIS PV
module (Year: 2003, Location: Kassel, Germany)
In this context, the measured temperature distribution of a typical CIS module at a location in Central
Germany is provided by Fig.2.
PV systems are typically tested and certied up to 1000V, therefore threshold 2) should never be ex-
ceeded. Regarding the breakdown voltage of the power semiconductors a safety factor of 1,5 needs to be
taken into account. The factor of 1,5 is based on long term experiences for power switches. Depending
on the structure of the switching device, the FIT (Failure In Time) rate due to cosmic irradiation rapidly
grows exceeding two third of the nominal switch voltage [5]. For this reason 1200V semiconductors
should not frequently be operated at more than 800V, see also threshold 1) in Fig 1.
Inverter topolgy
Inverter topologies can be basically divided into two main types: voltage source inverters (VSI) and
current source inverters (CSI). To some extend, the recently introduced Z-Source Inverter [7] represents
a combination of both.
A VSI with neutral-point connection needs at least a dc-link voltage of 650V to feed into a three-phase
400V grid as each dc-link capacitor needs to have a voltage higher than the amplitude of the phase
voltage. In the practical design, the dc-link voltage actually needs to be 700-750V due to a 10% grid
voltage tolerance and some control reserve. The reason why the neutral point should be connected to
the dc-link is to minimise common-mode voltages at the PV module. This issue will be discussed in the
following sections. A VSI directly connected to the PV module would even need a higher MPP voltage
because of a module manufacturing tolerance. Such high MPP voltages are not feasible according to Fig.
1 and the previous discussion. An additional dc-dc boost converter (BC) would be required which can
work with lower MPP voltages (see Fig. 3).
A CSI (see Fig. 4) is a viable alternative to a VSI+BC due to its voltage step-up characteristic [6],[8]. The
CSI directly connected to the PV module features a single-stage power conversion system for feed-in and
MPPT. With regard to the CSI at unity power factor, the MPP voltage has an upper limit of about 440V
which is derived from the minimum of the rectied phase to phase voltage minus a grid voltage tolerance.
A comparison between these basic concepts presented in [8] revealed that an IGBT-equipped VSI+BC
Figure 3: Typical circuit diagram of a MOS-equipped
VSI+BC for a PV module generation system
Figure 4: Circuit diagram of a MOS-equipped CSI for
a PV module generation system
tends to have a better performance in medium power fuel cell applications. However, these results can not
be fully transferred to a low power PV inverter. E.g. the CSI is well suitable for using MOSFETs as the
series diodes providing reverse voltage blocking capability prevent current from owing into the inherent
body diodes. These are generally considered as poor concerning switching losses. A VSI using external
diodes would require additional series diodes as depicted in Fig. 3. The part count and complexity of the
two-stage concept (VSI+BC) which impacts reliability and costs motivated to investigate the CSI as the
more promising solution. The CSI is mainly known from high power drives and lately it was used for
fuel cell inverters in the kW-range [8]. The application in a 200W PV inverter is a novelty though.
Operation of a CSI on a high voltage PV module
While the CSI exhibits several advantageous characteristics, it also presents several challenges, most of
themconcern the modulation strategy and control. The control of a CSI can be regarded as uncomplicated
once the basic transfer function is described since, in theory, it is only required to have one measured
dc quantity. Moreover, the control speed is mostly dictated by the size of the dc-link inductors as the
following section shows.
System Description
Looking at the CSI in a synchronous rotating reference frame (
1
) the dc-link current i
dc
controls the
active (d-) component of the ac phase currents. To change the power factor of the phase currents, e.g. for
compensating capacitive currents drawn by the ac lter, the q-component i
rq
can be adjusted in an open-
loop fashion (see Fig. 5) [10]. For the scope of this paper, unity power factor is assumed, i.e. i
rq
0.
PWM
1
j
e
T
rd
i x
d
PLL
dc
V
k
v
dc
L
a
C
a
L
a
i
dc
i
a
1
M
1
P
rq
i
*
dc
i
dc
i
r
i
D
r
i
E
1
T
y
d
z
d
dc
L
MPPT
a
v
N
1
T
b
c
2
T
5
T
4
T
3
T
6
T
Figure 5: CSI schematic and control block diagram
Space vector modulation (SVM) can be applied to a CSI (see Fig 6) . There are nine valid switching
congurations provided that tne CSI do not allow an open loop at any time (see Table I). It can be
observed that state vectors 7, 8 and 9 imply a short circuit of the dc-link which magnetise the dc-link
inductors. In these states there is no current ow to the ac-side of the inverter. These so-called zero
states are used to maintain an equilibrium in i
dc
and control the magnitude of the phase current vector
respectively. The actual power transfer is performed by the active active state vectors i
1
i
6
.
I
II III
V VI

j
IV
r
i
r
i
D
r
i
E
1
T
1
i
6
i
7,8,9
i
2
i
3
i
4
i
5
i
Figure 6: CSI space vector plane and switching states
state i
y
switches v
k
v
M1N
v
P1N
i
1
1 , 6 v
a
v
c
v
c
v
a
i
2
6 , 3 v
b
v
c
v
c
v
b
i
3
3 , 2 v
b
v
a
v
a
v
b
i
4
2 , 5 v
c
v
a
v
a
v
c
i
5
5 , 4 v
c
v
b
v
c
v
b
i
6
4 , 1 v
a
v
b
v
b
v
a
i
7
1 , 2 0 v
a
v
a
i
8
3 , 4 0 v
b
v
b
i
9
5 , 6 0 v
c
v
c
Table I: Switching states of the CSI and resulting
voltages
A combination of two active states and one or more passive ones form a complete switching sequence
(see Fig 6). The SVM yields the duty cyles of the switching states depending on the length and position
of the reference current vector i
r
[9], [10]. The duty cycle of the lower active state shall be dened as d
x
,
the upper one as d
y
and the zero-state(s) as d
z
. Since there are only these three switching states at any
given sequence d
x
+d
y
+d
z
= 1.
The modulation index M is dened by the ratio between the amplitude of the reference current vector
and the dc-link current (0 M 1).
M =
|i
r
|
I
dc

i
r,d
I
dc
(1)
For sector I it can be shown that the slope of the short-time mean dc-link current I
dc
is given by (2)
I
dc
=
1
2L
dc

2T
s
T
s
([V
dc
(v
a
v
b
)] d
x
+[V
dc
(v
a
v
c
)] d
y
+V
dc
d
z
) dt (2)
while all other sectors behave in an analogue manner. I
dc
is the change on the dc-link current after the
given switching period has elapsed, L
dc
is the dc-link inductance, T
s
is the switching period and v
a
, v
b
and
v
c
are the phase voltages (Fig. 5) . In steady-state and assuming no control deviation I
dc
is zero. Since
the phase voltages have a fundamental frequency much smaller than the switching frequency, they can
be regarded as constant on time at any given switching period. After solving the integral and simpling,
equation (2) can be written as:
I
dc
=
T
s
2L
dc
[V
dc
v
a
(d
x
+d
y
) +v
b
d
x
+v
c
d
y
] (3)
The duty cycles d
x
and d
y
are directly related to the output waveform as well as to the energy transferred
from the dc-link to the ac grid by means of the modulation Index M. Equation (4) denes d
x
and d
y
in
sector I in proportion to v
b
and v
c
:
d
x
= M
|v
b
|

2V
a
= M| cos(
1
2/3)| d
y
= M
|v
c
|

2V
a
= M| cos(
1
+2/3)| (4)
where V
a
is the RMS phase voltage and v
b
(
1
) =

2V
a
cos(
1
2/3), v
c
(
1
) =

2V
a
cos(
1
+2/3).
When solving and simplifying the equation for I
dc
the following relation is obtained:
I
dc
=
T
s
2L
dc

V
dc

2
V
a
M

(5)
The dc-link current can be controlled with an I or PI controller. The control speed is determined by
T
s
L
dc
as
it is known from a boost converter. In steady-state the maximum dc voltage of the PV generator appears
at M = 1 according to (5) so that V
dc,max
= 3V
a
/

2.
The general concept implies a further advantage: No ac current sensors are required and the dc-link
current can be measured via an inexpensive shunt resistor.
Optimised modulation strategy regarding common mode current
Galvanic connection of the PV module to the grid involves earth leakage currents due to parasitic capaci-
tances of the module [11]. Leakage currents introduce problems with safety, EMI and additional power
losses. The earth capacitance C
E
(see Fig. 7) varies with environmental and mounting conditions of the
module. Several studies reported that C
E
can range from 1nF-75nF/kW (crystalline Si-modules) [11].
The instantenous values of v
M1
and v
P1
depend on the switching states of the bridge (see Table I). The
common mode voltage v
0
which drives a common mode current to ground is dened according to equa-
tion (6).
v
0
(t) =
v
P1
(t) +v
M1
(t)
2
(6)
dc
L
dc
L
a
v
a
C
a
L
0
i
N
1
M
1
P
0
i
1 P
v
1 M
v
E
C
E
C
0
v
sc
I
Figure 7: Circuit diagram CSI and parasitic ground capacitances of PV module
Neglecting all ohmic resistances the equivalent circuit diagram regarding common mode is depicted in
Fig. 8 (see also [12]). The voltage source V

0
represents the open circuit voltage if C
E
was zero. The
common mode source is connected to the load impedance consisting of C
E
and L
dc
. The common mode
current I
0,
in the frequency domain depends on V

0,
and the equivalent total impedance Z
0
which is
ploted in Fig. 9.
|I
0,
| =
|V

0,
|
2|Z
0
|
=
|V

0,
|
2(
L
dc
2

1
2C
E

L
a
33
2
L
a
C
a
)
(7)
Considering that the resonant frequency of Z
0
depends mostly on C
E
(see Fig. 9) it is necessary to place
external capacitors C

E
in parallel to keep it in a certain range. The resonant frequency should be well
below the switching frequency and of course, L
a
and C
a
should not resonate either. In a practical design,
the frequency range is most critical between 1-13kHz (see Fig. 9).
0
' V
2
E
C
2
dc
L
3
a
C
3
a
L
N
0
2I
Figure 8: Common mode equivalent circuit diagram
10
2
10
3
10
4
10
5
10
6
10
1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
Frequency f [Hz]
C
o
m
m
o
n

m
o
d
e

i
m
p
e
d
a
n
c
e

|
Z
0
|

[

]
C
E
= 100nF
C
E
= 22nF
C
E
= 1nF
Figure 9: |Z
0
( j)| with variable C
E
and L
dc
=40mH,
L
a
=1mH and C
a
=150nF
Since the waveform of v

0
depends on the modulation strategy, the degree of freedom is basically the
selection of zero-states. A modulation optimised for minimal switching losses should have the least
possible number of commutations [9]. This can be realised by choosing a zero-state which clamps
one phase for every 60 degree either on the positive or on the negative rail. For sector I the switching
sequence would be typically [i
1
],[i
6
],[i
7
] where T1 is turned ON permanently. The waveform of v

0
and
its corresponding FFT is ploted in Fig.10.
As illustrated by the FFT there is a high harmonic content in the range of 1-10kHz. With this modulation
the common mode current tends to oscillate easily.
0.02 0.025 0.03 0.035 0.04
400
200
0
200
400
Time [s]
A
m
p
l
i
t
u
d
e

v
0

[
V
]
10
2
10
3
10
4
10
5
10
6
0
20
40
60
80
100
120
Frequency [Hz]
A
m
p
l
i
t
u
d
e

v
0

[
V
]
Figure 10: Simulated waveform and FFT of v

0
at
f
s
=25kHz using switching loss optimised modulation
strategy
0.02 0.025 0.03 0.035 0.04
400
200
0
200
400
Time [s]
A
m
p
l
i
t
u
d
e

v
0

[
V
]
10
2
10
3
10
4
10
5
10
6
0
20
40
60
80
100
120
Frequency [Hz]
A
m
p
l
i
t
u
d
e

v
0

[
V
]
Figure 11: V
0
Simulated waveform and FFT of v

0
at
f
s
=25kHz using common mode optimised modulation
strategy
By selecting the zero-states according to minimal potential differences in v
M1
and v
P1
respectively, the
peak-to-peak common-mode voltage is reduced, particularily at the sector transitions. Moreoever, there
is almost no harmonic content below the switching frequency as demonstrated in Fig. 11. In this case,
there are four active switches per switching period increasing switching losses accordindly.
Dimensioning of electrical components
The design of a PV inverter highly depends on its targeted efciency, size and cost. The main power
electronic components of the circuit are the dc-link inductors and the power semiconductors of the three-
phase bridge which shall be discussed in the following context.
Dc-link inductors
The dc-link inductor is one of the key components within the CSI so its dimensioning needs detailed
analysis. The value of the dc-link inductance is determined by its voltage-sec balance. When the bridge
is short-circuited the voltage across one dc-link inductor corresponds to half of V
dc
during the boosting
period d
z
T
s
.
L
dc
=
V t
i
dc
=
V
dc
d
z
T
s
2i
dc
(8)
In steady-state it can be demonstrated from equation (2) that at each sector transition equation (9) applies:
V
dc
d
z
= (v
k,max
V
dc
) (1d
z
) v
k
>V
dc
(9)
where v
k,max
=

6V
a
is the amplitude of the phase to phase voltage. When the dc-link current shall not
become discontinuous in order to maintain a linear transfer function, the maximum allowed current
ripple, i
dc,max
is determined by the minimal dc power of the PV module and V
dc
:
i
dc,max
= 2
P
pv,min
V
dc
(10)
Finally, dc-link inductance L
dc,min
to prevent discontinous conduction mode is given by equation (11)
which is derived from the equations above depending on V
dc
.
L
dc,min
=

6V
a
V
dc

V
2
dc
4

6V
a
P
pv,min
f
s
(11)
The minimum required inductance is maximal at a dc voltage of V

dc
.
dL
dc,min
dV
dc
= 0 V

dc
=
2

6V
a
3
(12)
L

dc,min
=
2V
2
a
9P
pv,min
f
s
(13)
The conduction losses of L
dc
are calculated according to (14) with the winding resistance R
dc
.
P
C
Rdc
= R
dc

P
dc
V
dc

2
(14)
Power semiconductors
Choosing the right semiconductors is a cost-performance issue. The efciency is determined by conduc-
tion and switching losses and with increasing switching frequency the size of passive components can be
reduced.
The calculation of conduction losses is straight forward and relatively simple (see also [8]). In a CSI
there are two conducting transistors and diodes at any given. For the diodes follow:
P
C
D
= 2 V
F

P
dc
V
dc
(15)
At low power the forward voltage drop of common 1200V, 5A diodes is fairly constant at V
F
11, 5V
neglecting the ohmic losses. The conduction losses of the transistors are as follows:
P
C
T
2

P
dc
V
dc
V
T,0
+

P
dc
V
dc

2
r
T

(16)
For a MOSFETV
T,0
0 and r
T
=R
DSon
. The value of the on-state resistance varies with the drain current
and chip junction temperature.
P
C
MOS
2 R
DSon

P
dc
V
dc

2
(17)
For low power IGBTs V
T,0
=V
CE,0
1V and equation (16) applies.
100 150 200 250 300 350 400 450 500
0.95
0.96
0.97
0.98
0.99
1
r
e
l
.

s
e
m
i

c
o
n
d
u
c
t
i
o
n

l
o
s
s
e
s
MOS 1 :
MOS 4 :
IGBT
V
dc
[V]
Figure 12: Relative conduction losses of Diode+MOSFET, Diode+IGBT depending on V
dc
at P
dc
=100W, V
F
= 1V,
different R
DSon
, V
CE,0
= 1V, r
T
IGBT
= 0,5
Fig. 12 depicts the relative semiconductor conduction losses of MOSFET and IGBT as a function of V
dc
at partial load P
dc
=100W. For all curves the same diode values are used.
Two MOSFETs with four times different R
DSon
are compared. The curves start to converge at an input
voltage of V
dc
>300V. The IGBT is only slighty worse than the 1 MOS.
Regarding the calculation of switching losses it is difcult to nd accurate analytical expressions for
device currents and voltages during the switch commutations [9]. Most data sheets normally specify turn-
on and turn-off losses for a specic commutation diode and at a single blocking voltage with the current
as a parameter. However, by calculating the conduction losses and sustracting them from the measured
total power losses the sum of switching losses P
S,tot
can be approximately aquired. Alternatively, the
differential of the measured power losses at different switching frequencies also roughly yields P
S,tot
.
Experimental results
A laboratory prototype of a grid-connected MIC has been successfully put into operation (Fig. 13).
The common-mode current that ows inside of the inverter could be kept within a tolerable level (Fig.
14), the value of the dc-link inductance was chosen relatively high for testing purposes. The SVM and
control was run on a 16-bit microcontroller of the XC16x family. As Fig. 13 illustrates theres still room
for improvement concerning the waveform of the grid current. This is going to be realised through the
adjustment of control parameters and output lter design.
Figure 13: Waveforms of operation at the mains,
V
dc
=300V, f
s
= 25kHz, L
dc
= 35mH, C
a
= 150nF
Figure 14: Common mode waveforms, V
dc
=300V,
f
s
= 25kHz L
dc
=35mH, C
a
=150nF, C

E
=22nF
Efciency measurements were carried out at different operating conditions and using different semi-
conductors (Fig. 15-18). The weighted European efciency [1] has been also calculated based on an
interpolation of the measured curves. A peak efency of 98% has been achieved at V
dc
=380V and
f
s
=25kHz. However, all meausrements do not include the internal power consumption needed mainly
for the supply of the microcontroller and gate drivers.
Comparing conventional fast Si-diodes and newly introduced 1200V SiC diodes, the latter increase ef-
ciency by some margin, especially at higher switching frequency. In this application, IGBTs can be
an interesting alternative to MOSFETs. IGBTs are generally more common at voltage classes above
600V and require less specic chip area. According to the measurements in Fig. 15 and 17 the IGBT in
combination with SiC diodes can well compete with the MOSFET in terms of efciency.
A loss distribution was estimated by calculating the conduction losses and substracting them from the
measured power losses. Fig. 19 exemplarily depicts the loss distribution for the 1200V MOSFET and
SiC diode setup. Switching losses are dominating. Besides, they are fairly constant so that partial load
efciency is distinctly reduced.
0 50 100 150 200
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
Input power P
dc
[W]
M
e
a
s
u
r
e
d

e
f
f
i
c
i
e
n
c
y

(
P
d
c

)
V
dc
=380V, f
s
=25kHz,
eur
=97,0
V
dc
=380V, f
s
=50kHz,
eur
=94,8
V
dc
=300V, f
s
=25kHz,
eur
=96,4
V
dc
=300V, f
s
=50kHz,
eur
=94,4

Figure 15: Measured efciency with 1200V,14A MOS
and 1200V,5A SiC diode
0 50 100 150 200
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
Input power P
dc
[W]
M
e
a
s
u
r
e
d

e
f
f
i
c
i
e
n
c
y

(
P
d
c

)
V
dc
=380V, f
s
=25kHz,
eur
=96,6
V
dc
=380V, f
s
=50kHz,
eur
=94,2
V
dc
=300V, f
s
=25kHz,
eur
=96,1
V
dc
=300V, f
s
=50kHz,
eur
=93,4
Figure 16: Measured efciency with 1200V,14A MOS
and 1200V,5A Si Ultra-fast diode
0 50 100 150 200
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
Input power P
dc
[W]
M
e
a
s
u
r
e
d

e
f
f
i
c
i
e
n
c
y

(
P
d
c

)
V
dc
=380V, f
s
=25kHz,
eur
= 96,9
V
dc
=380V, f
s
=50kHz,
eur
= 95,2
V
dc
=300V, f
s
=25kHz,
eur
= 96,2
V
dc
=300V, f
s
=50kHz,
eur
= 94,4
Figure 17: Measured efciency with 1200V,3A IGBT
and 1200V,5A SiC diode
0 50 100 150 200
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
Input power P
dc
[W]
M
e
a
s
u
r
e
d

e
f
f
i
c
i
e
n
c
y

(
P
d
c

)
V
dc
=380V, f
s
=25kHz,
eur
=96,2
V
dc
=380V, f
s
=50kHz,
eur
=94,0
V
dc
=300V, f
s
=25kHz,
eur
=95,4
V
dc
=300V, f
s
=50kHz,
eur
=92,8
Figure 18: Measured efciency with 1200V,3A IGBT
and 1200V,5A Si Ultra-fast diode
Figure 19: Estimated loss distribution of P
L,tot
for 1200V,14A MOS and 1200V SiC,5A diode setup
Conclusion
This paper deals with the development of a transformerless three-phase Module Integrated Converter for
photovoltaic systems. The Current Source Inverter has been identied and implemented as a promising
solution for MICs in combination with high voltage thin lm PV modules. It has been demonstrated by
experimental results that feed-in is done by only controlling the dc-link current. By connecting external
capacitors parallel to the PV module terminals, leakage currents can be kept mostly inside the circuit. As
a result of an optimised modulation strategy such common-mode currents occured in a tolerable level.
The commercial success of a PV system largely depends on the efciency of the inverter. Furthermore,
high efciency supports reliability of inverters as the thermal stress is reduced. Therefore it has been a
focal point during the development of the MIC. Eventually, a peak efency of 98% could be achieved
using 1200V MOSFETs and SiC diodes. IGBTs with SiC diodes could be an interesting alternative
reaching a comparably high efciency.
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