UL

LSI/CSI

LS7290

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

(631) 271-0400 FAX (631) 271-0405

A3800

FEATURES:

STEPPER MOTOR CONTROLLER

DESCRIPTION:
The LS7290 generates Phase Drive outputs and PWM outputs for controlling
two phase Bipolar motors or four phase Unipolar motors, respectively. The
LS7290 contains a mode controlled look-up table for generating the motor duty
cycle drive sequences. There are four outputs which are used to drive two HBridges for the two motor windings in the Bipolar motor or the four Driver Transistors for the two center-tapped windings in the Unipolar motor (Refer to Table
2). The LS7290 can step a motor in full steps, half steps or in 1/4, 1/8, 1/16 or
1/32 microsteps. The LS7290 uses 32 microstepping phase controls for each
motor step in half step or in 1/4, 1/8, 1/16 or 1/32 microsteps. The LS7290 uses
stepping as shown in Table 2 for full step control. A table pointer is used which
is incremented or decremented by a value determined by the operating mode
and the direction control. The 8-bit PWM control and the refresh rate are set using an internal oscillator controlled by a crystal or by use of an external input
clock. Typical refresh rate is equal to 31.25kHz. Peak current feedback control using pulse width modulation chopping can only be used in full-step
or half-step modes. The chopper consists of a voltage comparator, flip-flop
and external sense resistor. The internal oscillator sets the flip-flop and enables
the INH1 and INH2 outputs at the beginning of each PWM cycle. Once the
peak motor current causes the voltage across the sense resistors to reach the
voltage set by VREF, the outputs are disabled until the next oscillator pulse.
The VREF voltage sets the peak current in each motor winding. In all other
modes, the VREF input should be set to VDD and the sense inputs should
be grounded.
INPUT/OUTPUT DESCRIPTION
RESET Input
Active low. Resets the PWM table pointer to HOME position per Table 2 and
brings INH1 and INH2 low. Upon power-up, a POR circuit also resets the PWM
table pointer.
ENABLE Input
Active low. When high (inactive), brings PHA, PHB, PHC, PHD, INH1 and INH2
outputs low.
STEP Input
Active low. A low-going pulse on this input causes the motor to advance one
step.
7290-073109-1

M0

M1

24

V DD

23

INH1

M2

22

INH2

RESET

21

PHA

STEP

20

PHB

FRD/REV

19

PHC

ENABLE

18

PHD

HOME

17

DS1

Rx

16

DS0

CLK

10

15

SENSE1

Cx

11

14

SENSE2

VSS

12

13

VREF

LS7290

Controls Bipolar and Unipolar Motors

Cost-effective replacement for L297 in Bipolar applications
Full, 1/2, 1/4, 1/8, 1/16, 1/32, step mode selected with 3 mode inputs
Direction control
Reset input
Step control input
Enable input
PWM chopper circuit for current control
8-bit PWM resolution
Two peak current comparators with external reference input
Step control frequency and duty cycle controlled by an external frequency
source or by an internal crystal controlled oscillator (typically 8MHz)
All inputs and outputs TTL/CMOS compatible (TTL for 5V operation)
3V to 5.5V Operation (VDD - VSS).
LS7290 (DIP), LS7290-S (SOIC), LS7290-TS (TSSOP) - See Figure 1 -

PIN ASSIGNMENT
TOP VIEW
LSI

July 2009

FIGURE 1

FRD/RVRS Input
A low input causes the motor to move in decremental steps
per Table 2. A high input causes the motor to move in incremental steps per Table 2 Switching directions can occur at
any time.
M0, M1, M2 Inputs
Defines the stepping modes as follows:
M2 M1 M0
full step mode
0
0 0
1/2 step mode
0
0 1
1/4 step mode
0
1 0
1/8 step mode
0
1 1
1/16 step mode
1
0 0
1/32 step mode
1
0 1
1/32 step mode
1
1 0
1/32 step mode
1
1 1
Stepping Mode can be changed at any time.
SENSE1 / SENSE2 Inputs
SENSE1 is the input for the voltage across the sense resistor
determined by the current in the motor winding driven by the
PHA and PHB power stages. SENSE2 is the input for the voltage across the sense resistor determined by the current in the
motor winding driven by the PHC and PHD power stages.
VREF Input
External voltage reference for current control comparators.

Rx, Cx, CLK

These three pins can be configured in one of three ways to obtain the primary clock. A crystal connected between Rx and
CLK pins or a resistor-capacitor pair connected among all three
pins (see Figure 4) can make use of the internal oscillator. Alternatively, the CLK pin can be driven from an external clock
source.
DS0 / DS1 Inputs
The phase drive is blanked out between steps by switching outputs INH1 and INH2 low in order to reduce audible noise and
power consumption. The duration of the blanking is selected by
DS0 and DS1 according to Table 1

PHA / PHB / PHC / PHD Outputs

The state of these phase outputs are determined by the look-up table
and are used to control either the left or right half of each of the HBridge drivers. A low on a phase output enables the bottom driver
while a high on the output enables the top driver.
HOME Output
Indicates Step0 state per Table 2 with a logic low.
INH1 / INH2 Outputs
These outputs are used to provide PWM control to each of the two HBridge drivers.

Table 1
DS1
0
0
1
1

DS0
0
1
0
1

Blanking Time, IPB, at fc = 8MHz

1.25us
2.50us
3.75us
5.00us

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

ENABLE

(+V )

M0

M1

2
3

RESET

4
5

FRD/RVRS

23 INH1
22

LOOK-UP
TABLE

20 PHB
19 PHC

RX

CLK

10

CX

11

18 PHD

OSCILLATOR

+
-

+
-

17

DS0

16

DS1

15 SENSE1
14

V SS

12

(-V )

SENSE2

13 VREF

FIGURE 2. LS7290 BLOCK DIAGRAM

7290-092607-2

INH2

21 PHA

OUTPUT
CONTROL
LOGIC

HOME

V DD

MODE
SELECT

M2

STEP

24

ABSOLUTE MAXIMUM RATINGS:

PARAMETER

SYMBOL

VALUE

UNIT

DC Supply Voltage
Any Input Voltage
Operating Temperature
Storage Temperature

VDD - VSS
VIN
TA
TSTG

+7
VSS - 0.3 to VDD +0.3
-20 to +85
-85 to +150

V
V
C
C

ELECTRICAL SPECIFICATIONS (-25C < TA < +85C)

PARAMETER
Supply Voltage
Supply Current
CLK frequency
Enable Propagation Delay
FRD / RVRS Setup Time
(before step pulse)

SYMBOL
VDD
IDD
fc
tepd
tds

MIN
3.0
100
0

TYP
8.00
-

Step Pulse Width

SPW

1.0

Interstep Pulse Delay

Interstep Phase Blanking
Reset Pulse Width
Reset to Step Pulse Delay
Hi-Level Input Voltage
Low-Level Input Voltage

ISD
IPB
RPW
trs
ViH
VIL

32
1.25
1.0
0
2
-

Hi-Level Input Current

Low-Level Input Current

IH
IL

Output Sink Current

MAX
5.5
2.0
-

UNIT
V
mA
MHz
ns
us

CONDITIONS
Outputs floating, Inputs high
-

us

at fc = 8 MHz

5.0
0.8

us
us
us
us
V
V

at fc = 8 MHz
at fc = 8 MHz
at fc = 8 MHz
VDD = 5 0.25V
VDD = 5 0.25V

50
50

nA
nA

Leakage Current
Leakage Current

Io
Io

-10
-5

mA
mA

Vo = 0.4V, VDD = 5V
Vo = 0.4V, VDD = 3.3V

Output Source Current

Io
Io

5
2.5

mA
mA

Vo = 4.0V, VDD = 5V
Vo = 2.5V, VDD = 3.3V

Comparator Offset Voltage

Input Reference Voltage

VOS
VREF
VREF

0.5
0.5

5
-

15
3.0
1.5

mV
V
V

VREF = 1V
VDD = 5V
VDD = 3.3V
+V
24

VDD

LS7290
9

R
f C ~ 1/5RC
C

At VDD = 5V and R = 2.2k , C = 12pF,

oscillator frequency is 8MHz (typical)

10

11

RX

CLK

CX

VSS
12

FIGURE 3. RC OSCILLATOR FOR CLOCK GENERATOR

7290-121508-3

RESET

RPW

SPW

STEP

PHA

PHB

PHC

PHD
IPB

IPB

INH1

IPB

INH2

IPB

PWM

HOME

FIGURE 4. PARTIAL SEQUENCE IN FORWARD 1/2 STEP MODE

7290-011409-4

5V

1
2
3

MCU

4
5
6
7

VM

M0

VDD

INH1

M1

INH2

M2

PHA

RESET
STEP

PHB

FRD/RVRS

PHC

ENABLE

24

PHD

23

22

11

21

20

77

19

10

18

12

INH1
INH2

PHA

13

PHB
PHC L298

14

PHD

LS7290
25pF

RX

10M
10

CLK

25pF
12

VSS

SENSE1
SENSE2

VREF

15

100

14
13
0.01uF

15

100
0.01uF

FIGURE 5. TYPICAL APPLICATION SCHEMATIC FOR A TWO PHASE

BIPOLAR MOTOR USING A SINGLE MOTOR DRIVER IC

7290-060608-5

STEPPER
MOTOR
WINDINGS

5V
VM

1
2
3

MCU

4
5
6
7

24
VDD

M0

VS

PHA

M1

PHB

M2

INH1

21

IN1

20

VREF
220nF

FRD/RVRS

MOTOR
WINDINGS

OUT1

ENABLE

RESET
STEP

BOOT1

IN1

23

15nF

L6201
L6201PS
L6202
L6203

15nF

BOOT2

OUT2

SENSE

ENABLE

GND

LS7290
25pF

RX

10M
10

PHC
PHD

CLK

25pF

INH2

VS

19

IN1

18

IN1

22

ENABLE
VREF
220nF

15nF

MOTOR
WINDINGS

BOOT1
OUT1
L6201
L6201PS
L6202
L6203

15nF

BOOT2

OUT2
SENSE

GND

SENSE1
12

SENSE2
V SS

VREF

15

100

14
13

100
0.01uF

0.01uF

FIGURE 6. TYPICAL APPLICATION SCHEMATIC FOR A TWO PHASE

BIPOLAR MOTOR USING TWO SEPARATE MOTOR DRIVER ICs

7290-073109-6

5V
VM

1
2
3

MCU

4
5
6
7

24
VDD

M0

PHA

M1

PHB

M2

INH1

21
20

4
5

STEP

SENSE1

23

RESET

Q1

74HC08
6
Q2

15

FRD/RVRS
ENABLE

0.01uF

LS7290
25pF

100

RX

VM

10M
10

CLK

25pF

PHC
PHD
INH2

19
18
22

9
10
12
13

Q3

74HC08
11
Q4

12

SENSE2

VSS

VREF

14

100

13
0.01uF

NOTE: Q1, Q2, Q3, Q4 are MOSFET Power Transistors suitable for 5V Gate Drive
Typical P/Ns = IRLZ44N and IRF3708

FIGURE 7. TYPICAL APPLICATION SCHEMATIC FOR A FOUR PHASE

UNIPOLAR MOTOR USING DISCRETE MOSFET TRANSISTORS

7290-060608-7

TABLE 2
Step Number
Full 1/2 1/4 1/8
0

% Duty Cycle
1/16 1/32
0
1

2
3

4
5

6
7

8
9

10
11

12
13

14
15

16
17

18
19

7290-092607-8

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

INH1

INH2

100.0
99.9
99.5
98.9
98.1
97.0
95.7
94.2
92.4
90.4
88.2
85.8
83.1
80.3
77.3
74.1
70.7
67.2
63.4
59.6
55.6
51.4
47.1
42.8
38.3
33.7
29.0
24.3
19.5
14.7
9.8
4.9
0.0
-4.9
-9.8
-14.7
-19.5
-24.3
-29.0

0.0
4.9
9.8
14.7
19.5
24.3
29.0
33.7
38.3
42.8
47.1
51.4
55.6
59.6
63.4
67.2
70.7
74.1
77.3
80.3
83.1
85.8
88.2
90.4
92.4
94.2
95.7
97.0
98.1
98.9
99.5
99.9
100.0
99.9
99.5
98.9
98.1
97.0
95.7

Phases
PHA

PHB

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

PHC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

PHD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Step Angle
HOME
2.81
5.63
8.44
11.25
14.06
16.88
19.69
22.50
25.31
28.13
30.94
33.75
36.56
39.38
42.19
45.00
47.81
50.63
53.44
56.25
59.06
61.88
64.69
67.50
70.31
73.13
75.94
78.75
81.56
84.38
87.19
90.00
92.81
95.63
98.44
101.25
104.06
106.88

TABLE 2 (continued)
Step Number
Full 1/2 1/4 1/8
5

10

% Duty Cycle
1/16 1/32

INH1

INH2

PHA

PHB

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

-33.7
-38.3
-42.8
-47.1
-51.4
-55.6
-59.6
-63.4
-67.2
-70.7
-74.1
-77.3
-80.3
-83.1
-85.8
-88.2
-90.4
-92.4
-94.2
-95.7
-97.0
-98.1
-98.9
-99.5
-99.9
-100.0
-99.9
-99.5
-98.9
-98.1
-97.0
-95.7
-94.2
-92.4
-90.4
-88.2
-85.8
-83.1
-80.3
-77.3
-74.1
-70.7
-67.2
-63.4
-59.6

94.2
92.4
90.4
88.2
85.8
83.1
80.3
77.3
74.1
70.7
67.2
63.4
59.6
55.6
51.4
47.1
42.8
38.3
33.7
29.0
24.3
19.5
14.7
9.8
4.9
0.0
-4.9
-9.8
-14.7
-19.5
-24.3
-29.0
-33.7
-38.3
-42.8
-47.1
-51.4
-55.6
-59.6
-63.4
-67.2
-70.7
-74.1
-77.3
-80.3

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

20
21

11

22
23

12

24
25

13

26
27

14

28
29

15

30
31

16

32
33

17

34
35

18

36
37

19

38
39

10

20 40
41

7290-092607-9

Phases
PHC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

PHD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Step Angle
109.69
112.50
115.31
118.13
120.94
123.75
126.56
129.38
132.19
135.00
137.81
140.63
143.44
146.25
149.06
151.88
154.69
157.50
160.31
163.13
165.94
168.75
171.56
174.38
177.19
180.00
182.81
185.63
188.44
191.25
194.06
196.88
199.69
202.50
205.31
208.13
210.94
213.75
216.56
219.38
222.19
225.00
227.81
230.63
233.44

TABLE 2 (continued)
Step Number
Full 1/2 1/4 1/8
21

% Duty Cycle
1/16 1/32
42
43

11 22

44
45

23

46
47

12

24

48
49

25

50
51

13

26

52
53

27

54
55

14

28

56
57

29

58
59

15

30

60
61

31

62
63

0
7290-092607-10

84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
0

Phases

INH1

INH2

PHA

PHB

PHC

PHD

-55.6
-51.4
-47.1
-42.8
-38.3
-33.7
-29.0
-24.3
-19.5
-14.7
-9.8
-4.9
0.0
4.9
9.8
14.7
19.5
24.3
29.0
33.7
38.3
42.8
47.1
51.4
55.6
59.6
63.4
67.2
70.7
74.1
77.3
80.3
83.1
85.8
88.2
90.4
92.4
94.2
95.7
97.0
98.1
98.9
99.5
99.9
100.0

-83.1
-85.8
-88.2
-90.4
-92.4
-94.2
-95.7
-97.0
-98.1
-98.9
-99.5
-99.9
-100
-99.9
-99.5
-98.9
-98.1
-97.0
-95.7
-94.2
-92.4
-90.4
-88.2
-85.8
-83.1
-80.3
-77.3
-74.1
-70.7
-67.2
-63.4
-59.6
-55.6
-51.4
-47.1
-42.8
-38.3
-33.7
-29.0
-24.3
-19.5
-14.7
-9.8
-4.9
0.0

0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0

Step Angle
236.25
239.06
241.88
244.69
247.50
250.31
253.13
255.94
258.75
261.56
264.38
267.19
270.00
272.81
275.63
278.44
281.25
284.06
286.88
289.69
292.50
295.31
298.13
300.94
303.75
306.56
309.38
312.19
315.00
317.81
320.63
323.44
326.25
329.06
331.88
334.69
337.50
340.31
343.13
345.95
348.75
351.56
354.38
357.19
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23

INH1

6
SLOW / FAST

L298
LS7290

21

PHA

PHB

20

FIGURE 8. Selecting Between Fast and Slow Decay for One Stepper Motor Winding
(Use identical circuit for the other stepper motor winding)
NOTE: In fast decay mode, inhibit windings are chopped.
In slow decay mode mode, phase windings are chopped
NOR Gates: CD4001

7290-061609-11

OR Gates: CD4071

VM = 120V

1N758

PHA

1k

1k

21 (19)

Q1

10k

Q3

MOTOR
WINDING

10k
2N5551

PHB
20 (18)

1N4003

1N758

10k
2N5551

Q2

1N4003

Q4

LS7290
INH1

10k

23 (22)

SENSE1
15 (14)

Inverters = 74HC04
Gates = 74HC08
Q1 = Q3 = IRF6218 (Typical)
Q2 = Q4 = IRF3615(Typical)

FIGURE 9. 120V Motor Discrete Component Driver

7290-061609-12