8085 P

1. Classify 8085 P in terms of Memory Access architecture and Instruction Set Architecture. 2. Address space of 8085 is ____KB and I/O space is ____ ports. 3. If Tosc is the time period of frequency of crystal connected to 8085 and Tout is the time period of clock frequency out from 8085 (pin 37), then the ratio Tosc: : Tout is ____. 4. What is the content in accumulator after execution? MVI A, 45H MOV B, A STC CMC RAR XRA B 5. An 8085 executes the following instructions. All addresses and constants are in Hex. Just after executing PCHL, what is the content of PC (Program Counter) and HL (HL Register Pair)? 2710: LXI H, 1388H 2713: DAD H 2714: PCHL 6. Write an 8085 ALP for multiplying two numbers present in B and C registers (theres no MUL instruction in 8085 P). 7. In an 8085 P, CMP B instruction was executed while the content of accumulator is less than that of B register. What is the status of Carry and Zero flag (Set/Reset)? 8. Which of the following is illegal in 8085 assembly language? a. PUSH A b. DCR 40H c. XTHL d. RNZ 9. Which of the following is true about HLT instruction? a. Address and Data buses are tri-stated. b. Interrupt or reset is necessary to exit from the halt state.

c. MPU enters HALT Acknowledge cycle and wait states are inserted. d. Finishes execution and prevents further execution. 10.Total number of interrupts in 8085 is ____. 11.The interrupt in 8085 which is both level and edge sensitive is ____ 12.In 8085 P, Service routine starts from a fixed memory location that cannot be set, but the interrupt can be delayed or rejected. Such an interrupt is called____ and ____. 13.If the logic levels of Status signals IO/M, S1, S0 are 1, 1 and 0 respectively, then the ongoing machine cycle is ____ ____. 14.Which of the following 8085 machine cycles is longer (in terms of T-States, without wait states)? a. Memory Write b. Opcode Fetch c. Memory Read

15.If data has to be transferred between I/O device and all of the registers in P, then the I/O must be connected a. Serially b. As I/O mapped I/O c. As Memory mapped I/O

8086 P
1. The ____ bit of the Opcode helps the CPU identify between the 8-bit and 16-bit
operations.

2. The ____ prefix when added with the instructions prevents the bus access by
another master.

3. Four words of memory are reserved by using the ____ pre-processor. 4. The ____ operator directs the assembler to decide the data type of the specified
label and replaces the label by decided data type.

a. PTR b. TYPE c. EXTRN d. LENGTH 5. What is the difference between TEST and AND instructions?

6. The 1Mbyte memory is divided into ____ logical segments each with a size of
____bytes.

7. If the value in the direction flag is 1 then the string will be processed in ____
mode.

8. What is the effective address in MOV AX, 5000H [BX] if the [DS] =1000H and
[BX] =2000H?

9. The ____ processor can accept the instructions of 8086 but has an 8 bit data bus. 10. 11. 12. 13. 14.
The ____ bit is used by REP instruction to control the loop. The address on reset for 8086 is ____. The DOS function calls are available under ____ instruction.

The size of the interrupt vector table in 8086 is ____ and each interrupt type occupies ____ bytes.

The value of CX and the flag that would be set on execution of the following program MOV AX, SEG1 MOV DS, AX MOV AX, SEG2 MOV ES, AX MOV SI, OFFSET STRING1 MOV DI, OFFSET STRING2 MOV CX, 010H CLD REPE CWPSW When the two string are equal are, 15. 8086 is classified as a ____ processor based on instruction set and follows ____ endian method.

8051 C

1. Though the architecture is same, what is the difference between the 8031 and
the 8051?

2. Draw the power-on reset (with debounce) circuitry for 8051. 3. In 8051 RAM, Bit-addressable memory locations are from ____H to ____H
addresses. 4. What are the conditional flags present in Program Status Word of 8051? 5. The I/O port of 8051 that does not have a dual-purpose role is port ____. 6. Relative Jump address range for SJMP instruction is ____ bytes.

7. What is the value in Accumulator after execution of this BCD addition?

MOV A, #52H ADD A, #87H DA A 8. Write an ALP (two lines) to reset the LSB and set the MSB of a number in Accumulator. 9. Which of these are illegal in 8051 Assembly Language? a. PUSH A b. SUB A, R1 c. MOVC @A+DPTR, A d. SHL A 10. Assuming RAM location 40H contains 47H, find the value in Acc and 40H after execution. MOV A, #74H MOV R1, #40H XCHD A, @R1 11. In 16 bit timer mode, what is the required value to be loaded into TH1 & TL1 if 50 ms delay is needed?(Assume 12 MHz Crystal, therefore 1 timer count = 1 s) 12. The TH1 value to be loaded for achieving 4800 baud rate 8 bit UART in 8051 is ____H. 13. List all the interrupts in 8051 in the order of increasing/decreasing priority. 14. The control word of 8255(Programmable Peripheral Interface) if all the ports of A, B, and C are output ports is ____H. 15. Which of the following pins of ADC 0804 specify that the conversion has finished?

a. b. c. d.