A DSTATCOM Modelling, Analysis and Performance for Unbalanced and Non-linear Load

C N Bhende, Non-member Dr M K Mishra, Non-member Dr H M Suryawanshi, Member

This paper describes the modelling and analysis of distribution static compensator (DSTATCOM), which is capable of balancing the source currents inspite of unbalanced and non-linear load currents. In addition to this, the power factor can also be set to a desired value. The theory of instantaneous symmetrical components is used here to extract the three-phase reference currents. These reference currents are then tracked using voltage source inverter (VSI), operated in a hysteresis band control mode. The detailed simulation results are presented to support the concept. The two-level and three-level neutral clamped inverter topologies are used to realize the compensator. It is demonstrated that three-level inverter gives less total harmonic distortion (THD) in source currents as compare to two-level inverter.
Keywords: DSTATCOM; Load compensation; Three-level VSI; PI voltage controller

NOTATION h : hysteresis current control band ifa, ifb, ifc : three-phase compensator currents

i * , i * , i * : three-phase compensator reference currents fa fb fc

ila, ilb, ilc isa, isb, isc K p , Ki Lf Plav Ploss Rf vc1, vc2
v c1 , v c 2
c yl c yl

: three-phase load currents : three-phase source currents : proportional, integral gains of voltage controller : interface inductance : average load power : switching losses of the inverter : internal resistance of interface inductance : voltages across capacitors C1, C2 : voltages across capacitors C1, C2 at the end of each cycle : reference voltage across the capacitor : instantaneous positive sequence source voltage, current : phase angle between source voltage and source current

vcref vsa1, isa1 f

vsa, vsb, vsc : three-phase source voltages

INTRODUCTION The unbalanced and the non-linear loads affect the quality of source currents to a large extent. It affects the voltage at point of common coupling (PCC) where the facility is connected. This has adverse effects on the sensitive equipments connected to PCC and may damage the equipment appliances. Many techniques have been proposed to improve the supply side power factor to cancel out the harmonics generated by power electronic loads. L Gyugyi proposed sampling and averaging techniques to realize thyristor controlled time varying reactive network1. Disadvantage of these methods is that these have been carried out only for sinusoidal steady state conditions. In fast Fourier transform (FFT) technique2, the disadvantage is that it adds inherent one cycle delay. Source current synthesis using the capacitor voltage feedback can also be used 3-4 for load compensation. However, the transient performance of the compensator based on this method is poor4-5. Recently, pq theory which is also called instantaneous reactive power theory6 has drawn much attention. The pq theory, not only compensates the fundamental reactive power under transient conditions but also compensates for harmonic currents in the load. However, pq theory fails if the source voltages are unbalanced and non-sinusoidal. Furthermore, it needs a large number of transducers including complex transformations, which makes the operation complex. The theory of instantaneous symmetrical components7-8 can be used for the purpose of load balancing, harmonic suppression, and power factor correction. The theory of instantaneous symmetrical components for compensation7-8 is much more simplified as compared to the pq theory6. Algorithms provided by instantaneous symmetrical component theory can practically compensate any kind of unbalance and harmonics in the load, provided it has a high bandwidth current source to track the filter reference currents. 297

C N Bhende, Dr M K Mishra and Dr H M Suryawanshi are with the Department of Electrical Engineering, Visvesvaraya National Institute of Technology (formerly VRCE), Nagpur. This paper (modified) was received on July 7, 2005. Written discussion on this paper will be received until May 31, 2006.

Vol 86, March 2006

In this paper, the theory of instantaneous symmetrical components is used to extract instantaneous reference currents, which are then realized by voltage source inverter circuit and are injected at the point of common coupling (PCC). It can be shown that instantaneous power in the electrical system containing unbalanced and non-linear load has an oscillating component that rides a dc value7. The objective of the compensator is to supply this zero-mean oscillating power such that dc component of power is supplied by the source. The method of reference current generation based on the theory of instantaneous symmetrical components is described in the next section. REFERENCE CURRENT GENERATION SCHEME The schematic diagram of three-phase four-wire compensated system is shown in Figure 1. The compensator and the load are connected at a point called as point of common coupling (PCC). The load may be unbalanced and non-linear. The compensator is assumed to be ideal, (ie, infinite bandwidth). In the analysis given below, it is assumed that the ideal * compensator tracks the reference currents perfectly, ie, i f i f . The purpose of the proposed scheme is to generate the three reference current waveforms, which will then be supplied as reference to the three VSIs. In three-phase four-wire system, three phase currents are independent. Thus, three independent equations are required to generate these currents. The extraction of reference currents is given as follows. Criterion 1: The supply current must be balanced From the above Criterion
i sa + isb + i sc = 0

Substituting value of a, the above equation can be written as

tan 1 K 1 / K 2 = tan 1 K 3 / K 4 +

(3)

where

K1 = K3 =
Defining

3 v sb v sc , 2 3 i isc , 2 sb

K 2 = v sa K 4 = isa

1 1 v sb v sc 2 2

isb i sc 2 2

tan / 3
Solving (3), gives (Appendix)

(4)

bv

sb

v sc v sa isa + v sc v sa v sb isb

g b

+ v sa v sb v sc isc = 0
The instantaneous reactive power q is defined as6
q= 1 i sa v sc v sb + i sb v sa v sc + i sc v sb v sa 3

(5)

n b

g b

g b

gs

(6)

when = 0, = 0 and equation (5) becomes

1 isa v sc v sb + isb v sa v sc + isc v sb v sa 3

n b

g b

g b

gs = 0

(7)

(1)

Criterion 2: The desired power factor of the source can be set explicitly From the power factor consideration, it is assumed that the phase of the vector isa1 lags vsa1 by an angle f ie,
v sa + v sb + v sc = isa + isb + isc +

Equation (7) implies that when the power factor angle is assumed to be zero, the instantaneous reactive power supplied by the source is zero. when 0, 0 and equation (5) becomes
1 isa v sc v sb + isb v sa v sc + isc v sb v sa 3

t o

(2)

n b

g b

g b

gs

where

= 3 v sa isa + v sb isb + v sc isc

(8)

= e j120
vsa N vsb vsc

i sa i sb i sc PCC

i la i lb i lc

LOAD LOAD LOAD io n

Equation (8) implies that when power factor angle is non-zero, the source supplies a reactive power that is equal to b times instantaneous power. Criterion 3: The source should supply the average load power The instantaneous power in a balanced three-phase circuit is constant while for an unbalanced circuit it has a double frequency component in addition to the dc value. The objective of the compensator is to supply the double frequency component such that the source supplies the dc value of the load power. Therefore it is obtained
v sa isa + v sb i sb + v sc isc = Plav

Ideal compensator

i* fa

i* fb

i* fc n`

(9)

Figure 1 Schematic diagram of the compensation scheme for star connected load with 4-wire supply

where, Plav is the average load power and is computed using a moving average filter (MAF). Moving average filter has been used to provide fast transient response to the compensator. The IE (I) JournalEL

298

conventional low pass filter gives poor transient response typically about 4-5 cycles5. It is to be noted that any harmonic component in the load does not require any real power from the source provided source voltages are balanced and sinusoidal. The formulation of equation (9) is thus valid even when the load current contains harmonics. Combining equation (1), (5) and (9)

For a balanced supply voltages, vs 0 = 0 and equation (15) reduces to

i * = ila fa i * = ilb fb v sa + v sb v sc v sb v sc
sc sa

A* is = Pl
where
iT i sa isb isc , PlT = 0 0 Plav and A = s

(10)

i * = ilc fc

b g P + bv v g P + bv v g P
sa sb

lav lav

lav

U | | | V | | | W

(16)

Fv GH

sc

v sa

1 3 v sb v sb

LMF v NMGH I FG v JK H

sb

v sc

1 3v sa v sa 1 3 v sc v sc

sa

v sb

IJ K IJ OP K PQ

where
=
j = a, b , c

2 v sj

Applying KCL at PCC

i sa = ila i * , isb = ilb i * , i sc = ilc i * fa fb fc

(11)

Using (10)-(11), gives

Ai * = Ail Pl f

(12)

COMPENSATOR STRUCTURE AND MODELLING To realize the reference currents described earlier, a suitable compensator structure is required. In the present work neutral clamped inverter topology9 is used to track the reference currents given by equation (16) using two-level voltage source inverter as shown in Figure 2(a) and three-level voltage source inverter as shown in Figure 2(b). The structure of two-level VSI consists of six IGBT switches (S1 S6), each with anti-parallel diodes and two dc storage capacitors. In three-level inverter twelve IGBT switches are used each with anti-parallel diodes. Two additional diodes are also required to provide useful path for zero voltage level in each leg as shown in Figure 2(b). The compensator is connected to the point of common coupling (PCC) through interfacing inductance Lf with its internal resistance Rf. This practical inverter has also switching and other losses. If the dc storage capacitors are used for VSI operation, they will discharge in due course of time, due to switching losses in the compensator. If the voltage across any of these capacitors falls below the peak of system voltage, then the inverter will not track the reference currents properly. Therefore for proper
vsa N vsb vsc i1 i sa i sb i sc i fa i fb i fc S1 a n` C2 vc 2 i2 S4 b S6 c S2 S3 S5 Rf Lf
PCC

where
i *T = i * i * i * , ilT = ila ilb ilc f fa fb fc

Premultiplying both the sides of equation (12) by, A1 gives

i * = il A1 Pl f

(13)

To simplify equation (13) it is noted that

A =3

where

LM N

j = a, b , c

2 v sj 3 v s20

OP Q

(14)

v s0

1 = 3

j = a, b , c

v sj

i la i lb i lc

LOAD LOAD LOAD

Then the equation for generating reference currents is given as

i * = ila fa i * = ilb fb i* fc = ilc

bv bv bv

sa sb sc

v s 0 + v sb v sc v s0 v s0
sc

g b g + bv g + bv

v sa v sb

sa

g P g P g P

lav lav

lav

U | | | V | | | W

(15)

C1

vc 1

where

j = a, b , c

v sj

3 v s20

Figure 2(a) The compensated system with two-level inverter

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vsa N vsb vsc i1 S1a C1 vc 1 n` C2 vc 2 i2 a S2a b S3a S4a S3b S4b S1b S2b

i sa i sb i sc

PCC

i la i lb i lc

LOAD LOAD LOAD

i fa i fb i fc S1c S2c S3c S4c Rf Lf

signal for S4 is the complementary signal S a . Similarly, Sb , Sb , S c , Sc represents gating signals for switches S3, S6, S5, S2, respectively. The switches of the inverter are operated such that in each leg one of the switches is always gated. Therefore the currents i1 and i2 in the input lines of the inverter (Figure 2(a)) can be written in terms of inverter currents and gating signals as follows
i1 = S a i fa + S b i f b + S c i fc
i2 = S a i fa + S b i fb + S c i fc

(20) (21)

Figure 2(b) The compensated system with three-level inverter

The voltage source inverter configuration of switches S1 to S6 is operated in the hysteresis current control mode. When the current ifa hits a pre-calculated lower limit, switch S1 is closed. The equivalent circuit for this mode is shown in Figure 3. By applying KVL around the loop
di fa dt = Rf Lf i fa + v c1 Lf v sa Lf

operation of compensator, the total voltage across the capacitors is to be maintained at the reference voltage level. To achieve this, the term Ploss, which is equivalent to switching losses and other losses in the inverter should come from the source in balanced manner. The source therefore should now supply average load power Plav and switching losses Ploss. Hence, the equation (16) is modified to
i * = ila fa i * = ilb fb i * = ilc fc v sa + v sb v sc v sb v sc
sc sa

(22)

Similarly, if the current ifa hits a pre-calculated upper limit, switch S1 is opened and S4 is closed. An equivalent circuit gives,
di fa dt = Rf Lf i fa + v c2 Lf v sa Lf

b g bP + bv v g bP + bv v g bP
sa sb

lav lav

+ Ploss + Ploss + Ploss

lav

gU | | g| V | g| | W

(23)

(17)

Using the binary variables Sa and S a defined above we get from equations (22) and (23)
di fa dt = Rf Lf i fa + S a v c1 Lf Sa v c2 Lf v sa Lf

To generate Ploss term in equation (17), a suitable feedback control is used, which regulates the total voltage v c = v c1 + v c 2 across the two capacitors to a reference value 2 v cref , (where, v cref is the reference voltage across each capacitor). The average capacitor voltage is held constant if the average value of the dc capacitor current over a cycle is zero. Thus a simple proportional-plus-integral (PI) controller is chosen as
Ploss = K p e + K i

(24)

Similar equations can be written for other two phases. By using equations (20)-(21) the following equations can be written assuming C1 = C2 = C
vsa

z edt
e

(18)
S1 (Closed)

Rf Lf

where, Kp and Ki are the constants of PI controller and

e = e1 + e 2 = 2 v cref

c yl v c1

c yl vc2

j
c yl

(19)

C1

vc1

c yl In equation (19), e1 = v cref v c1 and e 2 = v cref v c 2 , where v cref is the dc voltage to which the capacitors are regulated, c yl c yl v c1 , v c 2 are the values of the voltages across capacitors C1 and C2 at the end of each cycle7.

C2

vc2

ifa S4 (Open)

STATE SPACE MODELLING OF COMPENSATOR The gating signal for S1 in Figure 2(a) is represented by a binary variable Sa. If Sa = 1, S1 is closed, and if Sa = 0, S1 is open. A gating 300
Figure 3 Equivalent circuit for phase-a when S1 is closed and S4 is open

IE (I) JournalEL

dv c1 dt
dv c 2 dt

= Sa
= Sa

i fa C
i fa C

Sb
Sb

i fb C
i fb C

Sc
+ Sc

i fc C
i fc C

SIMULATION STUDIES AND RESULTS (25) (26) Using state space model as given in equation (27), the states are computed in MATLAB. First the system is initialized and then system states are updated. After this, these state variables i fa , i fb , i fc are compared with reference currents given by

From equations (24)-(26), the following state space model is obtained

equation (17) in a hysteresis band h. If , i fa > i * + h , v c 2 fa voltage level is applied. If i fa < i * + h , + v c1 voltage level is fa
Table 1 System parameters Values 360 V peak (Balanced and sinusoidal)

& x = Ax + B u
where

(27)

x t = i fa i fb i fc v c1 v c 2

System Parameters

LM R / L MM 0 A= M 0 MM S / C MN S / C
f a a

0 Rf / Lf 0 Sb / C Sb / C

0 0 Rf / Lf Sc / C Sc / C

Sa / L f Sb / L f Sc / L f 0 0

Sa / L f Sb / L f Sc / L f 0 0

OP PP PP PP Q

System voltage Load

z a = 25 00 , z b = 50 300 , z c = 100 600 ,

3-phase rectifier drawing current of 5 A

Interface impedance dc capacitor

R f = 2 , L f =0.02 H
2200 mF

Load Currents, Amps

LM 1 / L MM 0 B=M 0 MM 0 MN 0
and

0 1 / L f 0 0 0

0 0 1/ L f 0 0

OP PP PP PP Q

20

ila ilb ilc

20 0 0.02 0.04 Time, s (a) 10000 0.06 0.08

u t = v sa v sb v sc

The state space model derived in equation (27) is valid for threelevel inverter also, only change is that the switching logic has to be modified. As shown in Figure 2(b), each leg of the three-level inverter consists of four switches, ie, S1a, S2a, S3a and S4a in the leg concerned to phase-a. With this inverter, three levels are possible, ie, + vc1, 0 and vc2. The zero voltage level is an additional voltage level if compared with two-level inverter. For voltage level + vc1, S1a and S2a are closed while S3a and S4a are open. Zero voltage level is obtained by opening all the four switches. To achieve vc2 voltage level, the bottom two switches, ie, S3a and S4a are closed and the top switches S1a and S2a are open. Though three-level inverter requires more numbers of switches and diodes comparable to two-level inverter, it has following significant advantages: l It can be used for high power applications as the semiconductor devices are subjected to less voltage and current stresses. Gives less THD in the source current.

pl

pl

Watts and VAr

4000 2000 ql

4000 0

ql

0.02

0.04 Time, s (b)

0.06

0.08

Figure 4(a) Load currents which are also the source currents when compensator is not connected; and (b) active and reactive load powers

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isa

isb

Source currents, Amps

15

isc 20

vsa/15 isa

Volts and Amps

20 15 0 0.02 0.04 Time, s (a) 0.06 0.08 0 0.02 0.04 Time, s (a) 0.06 0.08

15

isa

isb

isc 20

vsa/15

isa

isb

isc

Source currents, Amps

Volts and Amps

20 15 0 0.02 0.04 Time, s (b) 0.06 0.08 0 0.02 0.04 Time, s (b) Figure 6 Power factor of source current is set to (b) 0.8 lagging (a) unity; and 0.06 0.08

Figure 5 Three-phase source currents with (a) two-level inverter; and (b) three-level inverter
* * applied. For two-level inverter, if i fa + h < i fa < i fa + h then

the status of the switches is retained and for three-level inverter, switches status corresponding to the zero voltage level is produced. Based on the above logic, the simulation is carried out and the simulation results are given below. Consider three-phase, fourwire system as shown in Figure 1. The system parameters for the simulation studies are given in Table 1. The source voltages are assumed to be balanced and sinusoidal. The load currents are unbalanced and non-linear. When the compensator is not connected, the source currents are equal to the load currents as shown in Figure 4(a). The THD in the load currents is 8.37%, 13% and 21% for phases a, b and c, respectively. For this the instantaneous load powers (pl and ql ) and the average load powers ( pl and q l ) are shown in Figure 4(b). When the compensator is connected, it gives balanced set

of source currents inspite of non-linear and unbalanced load currents as shown in Figure 5(a) and Figure 5(b). Figure 5(a) is showing the source currents by using the two-level inverter and Figure 5(b) is showing for three-level inverter. The THD in the source currents in case of two-level inverter is 3.71%, 2.87% and 1.82% for phases a, b and c, respectively, while in case of threelevel inverter, the THD is 2.08%, 1.59%, 1.46% for phases a, b and c, respectively. It seems that THD in three-level inverter is less than that of two-level inverter. The power factor of source current is set to unity as shown in the Figure 6(a). In order to set unity power factor, from (4), = 0 . Substituting this b in equation (17), reference currents are generated and then these currents are tracked. For unity power factor of the source current, the active power supplied by the source (ps ) is constant and it is equal to the average load power ( p l ) as shown in Figure 7(a). Also, source should not supply any reactive power, ie, reactive power supplied by source (qs ) is zero which is shown in Figure 7(a). The compensator supplies whole reactive load

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ps = pl = plav 7000 1200 vc1 + vc2

Watts and VAr

Volts
0.04 Time, s (a) 0.06 0.08

qs 0

1160

4000 0 0.02

1120

0.2

0.4 Time, s (a)

0.6

0.8

4000

pl pf = ~

Watts

650 vc2

4000

Volts

4000

qf = ql

600 vc1 550

VAr

4000 0 0.02 0.04 Time, s (b) Figure 7 Active and reactive and (b) compensator power supplied by (a) source; 0.06 0.08

500

0.2

0.4 Time, s (b)

0.6

0.8

power (qf = ql ) and zero oscillating instantaneous active load ~ power ( p f = pl ) as shown in Figure 7(b). The power factor can also be set to any other desired value. For example if power factor of 0.8 is desired, then from equation (4), is 0.433. For this, three-phase source currents and a-phase source voltage are shown in Figure 6(b). The controller is required to maintain the voltage across capacitors to reference value. When controller is not used, the capacitors will discharge and voltage across them will go on reducing as shown in Figure 8(a). By using PI controller, voltage across each capacitor is maintained at vcref as shown in Figure 8(b). Transient performance of compensator is evaluated in Figure 9. At the end of fourth cycle the load current in phase c reduces to zero while in phases a and b only rectifier load current is present as shown in Figure 9(a). At the end of eighth cycle, the load currents regain. The compensator source currents are shown in Figures 9(b) and (c). It is seen that inspite of load transient, source currents change sinusoidally with the settling time of half cycle. This ensures fast transient response of the compensator.

Figure 8 (a) Without voltage control; and (b) with voltage control (PI controller) 20 0 20 0

ilb

ila

Currents, Amps

20 0 20 20 0 20

0.08 isa

(a)

0.16

0.24

0 isa isb isc

0.08

(b)

0.16

0.24

0.08

Time, s (c)

0.16

0.24

Figure 9 Transient response (a) load currents; (b) source current of phase; and (c) three-phase source currents

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CONCLUSIONS A compensator with two-level and three-level inverter structure is proposed for three-phase, four-wire distribution system. It is capable of compensating sinusoidal or non-sinusoidal load currents. It can simultaneously correct the power factor to unity. A detailed state space model of the compensator is derived. The paper discusses the use of three-level inverter, which can be used for the high power applications and to reduce the THD in source currents. The scheme discussed here is also computationally simple, as it does not require complicated transformations and definition of many powers. REFERENCES
1. T J E Miller (ed). Reactive Power Control in Electric System. John Wiley, New York, 1982. 2. G Ha and M H Park. Analysis and Control of Active Power Filter with Optimized Injection. IEEE Transaction Power Electronics, vol 4, no 4, 1989, pp 427-433. 3. D A Torrey and A Al-Zamel. Single-phase Active Power Filters for Multiple Non-linear Loads. IEEE Transaction Power Electronics, vol 10, no 3, May 1995, pp 263-271. 4. K K Mahapatra, A Ghosh and S R Doradla. An Active Harmonic Current Compensator Using Quasi-resonant dc Link Inverter. Proceedings of CIGRE Regional Meeting on Power Quality-Assessment of Impact, Session VI, New Delhi, September 1997, pp 80-89. 5. H Akagi, A Nabae and S Atoh. Control Strategy of Active Power Filters using Multiple Voltage-Source PWM Converters. IEEE Transaction on Industry Application, vol 22, no 3, 1986, pp 460-465. 6. H Akagi, Y Kanazawa and A Nabae. Instantaneous Reactive Power Compensator Comprising Switching Devices without Energy Storage Components. IEEE Transaction on Industry Application, vol 20, no 3, 1984, pp 625-630. 7. A Ghosh and A Joshi. A New Approach for Load Balancing and Power Factor Correction in Power Distribution System. IEEE Transaction Power Delivery, vol 15, no 1, January 2000, pp 417-422.

8. A Ghosh and A Joshi. A New Method for Load Balancing and Power Factor Correction using Instantaneous Symmetrical Components. IEEE Power Engineering Review, vol 18, no 9, 1998, pp 60-62. 9. M K Mishra, A Ghosh and A Joshi. A New STATCOM Topology to Compensate Loads Containing ac and dc Components. IEEE Winter Power Meeting, Singapore, 2000. APPENDIX By rewriting equation (3)

tan 1 ( K 1 / K 2 ) = tan 1 ( K 3 / K 4 ) +
where
K1 = 3 v sb v sc 2 3 isb isc 2

(A.1)

h,

v 3 v K 2 = v sa sb sc = v sa 2 2 2 K 4 = isa isb isc 3 = isa 2 2 2

K3 =

h,

From (A.1)

tan tan 1 ( K 1 / K 2 ) = tan tan 1 ( K 3 / K 4 ) +

By solving (A.2)

(A.2)

K 3 / K 4 + tan K1 = K K2 1 3 tan K4
Putting values of K1, K2, K3 and K4 in (A.3), gives

(A.3)

V sb v sc 3 v sa
where

3 isb isc + 2 isa 2 isb 2 isc 2 isa isb isc 3 isb + 3 isc

(A.4)

tan / 3
By solving (A.4), gives

cv

sb

v sc v sa isa + v sc v sa v sb isb + v sa v sb v sc isc = 0

h c

h c

(A.5)

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