PCI BUS INTRODUCTION:

The PCI (Peripheral Component Interconnect) is a high performance Bus for interconnecting chips, expansion boards, and memory cards. It was originated at Intel Inc. In the early 1990s as standard methods of interconnecting chips on a board. It was later adopted as an industry standard administered by the PCI Special Interest Group or the PCI SIG. The basic form of the PCI presents a fusion of sorts between ISA and VL-Bus. PCI can connect more devices than VL-Bus, up to five external components. Each of the five connectors for an external component can be replaced with two fixed devices on the motherboard. Also, you can have more than one PCI bus on the same computer, although this is rarely done. The PCI bridge chip regulates the speed of the PCI bus independently of the CPU's speed. This provides a higher degree of reliability and ensures that PCI hardware manufacturers know exactly what to design for. PCI originally operated at 33 MHz using a 32bit-wide path. Revisions to the standard include increasing the speed from 33 MHz to 66 MHz and doubling the bit count to 64. Currently, PCI-X provides for 64-bit transfers at a speed of 133 MHz for an amazing 1-Gbps (gigabit per second) transfer rate. Although Intel proposed the PCI standard in 1991, it did not achieve popularity until the arrival of Windows 95 (in 1995). This sudden interest in PCI was due to the fact that Windows 95 supported a feature called Plug and Play (PnP). PCI supports devices that use either 5 volts or 3.3 volts. The PCI bus provides superior performance to the VESA local bus; in fact, PCI is the highest performance general I/O bus currently used on PCs. This is due to several factors.

The PCI bus can transfer information in a burst mode, where after an initial address is provided multiple sets of data can be transmitted in a row. This works in a way similar to how cache bursting works. PCI supports full bus mastering, which leads to improved performance. The bus supports three independent address spaces: memory,I/O and configuration. The I/0 address space is intended for use with processors, such as Pentium, however the system designer may choose to use memory mapped I/Other configuration space is intended to give the PCI its plug and play capability. A 4 bit command that accompanies the address identifies which of the three spaces is being used in a given data transfer operation. The PCI Bridge provides a separate physical connection for the main memory as shown below...

At any given time, one device is the bus master. It has the right to initiate data transfer by issuing read and write commands. A master is called an initiator in PCI.This is either a processor or DMA controller. The addressed device that responds to read and write command is called target.

DATA TRANSFER:
To understand the operation of the bus and its various features, let us examine a typical bus transaction. The main bus signal used for transferring data is listed below.. Name CLK FRAME# AD C/BE# IRDY#,TRDY# DEVSEL# Function A 33-MHZ or 66=MHZ\clock Sent the initiator to indicate the duration of the transaction. 32 address/data lines, which may be optionally increased to 64 4 command/byte enable lines(8 for a 64bit) Initiator-ready and target-ready signals A response from the devices indicating that it has recognized its address and is ready for a transaction Initialization device select

IDSEL#

Consider a bus transaction in which the processor reads four 32 bits words from the memory. In this case the initiator is the processor and target is the memory. A complete transfer operation on the bus, involving an address and a burst of data, is called a transaction. Individual word transfer with in a transaction is call phases. A clock signal provides the timing reference used to coordinate different phases of a transaction. All signal transitions are triggered by the rising edge of the clock. In clock cycle1, the processor asserts FRAME# to indicate the beginning of a transaction. At the same time, it sends the address on the AD lines and a command on the C/BE#lines.in the case the command indicates a read operation and the memory address space being used. Clock cycle 2 is used to turn the AD bus lines around. The processor removes the address and disconnects its drivers from the AD lines.because, the DEVSEL# is in low pulse stage. The selected target enables its drivers on the AD lines, and fetches the requested data to be placed on the bus during clock3.it asserts DEVSEL# and maintains it in the asserted state until the end of transaction.

During clock cycle 3, the initiator asserts the initiator ready signal, IRDY#, to indicate that it is ready to receive data. If the target has data ready to send at this time, it asserts target ready, TRDY# and sends a word of data. The initiator loads the data into its input buffer at the end of the clock cycle. The target sends three more word of data in clock cycle 4 to 6. The initiator uses the FRAME# signal to indicate the duration of the burst. It indicates the signal during the second last word of the transfer. Since it wishes to read four words, the initiator negates FRAME# during clock 5,the clock cycle in which it receives the third word. After sending the fourth word in clock cycle6, the target disconnects its drivers and negates DEVSEL# at the beginning of the cycle 7.

How the IRDY# and TRDY# signals can be used by the initiator and target, to indicate a pause in the middle of a transaction. The read operation starts the same way, and the first two words are transferred. The target sends the third word in cycle 5.however we assume that the initiator is not able to receive it.hence,it negates IRDY# .in response, the target maintains the third data word on the AD lines until IRDY# is asserted again. Cycle 6, the initiator asserts IRDY# and loads the data in to its input buffer at the end of the cycle. At this point, we assume that the target is not ready to transfer the fourth data immediately.hence,it negates TRDY# at the beginning of cycle 7.in clock 8,it sends the fourth word and asserts TRDY#.since,the FRAME# was negated with the third data word, the transaction ends after the fourth word has been transferred.

DEVICE CONFIGURATION:
Another important aspect of the PCI specification is the auto-configuration of PCI device on the bus. With ISA today, when a one adds a new I/O cards to the PC, one must be aware of the I/O requirements of the card to be added. Typically this involves setting jumpers and adjusting base addressing and interrupts.

The PCI specification requires that all devices must have a set of configuration registers that are examined upon power up. Jumpers and switches cannot be used for PCI configuration. Upon power up, the configuration software detects the presence of all PCI devices on the bus.onces detected; the software assesses the configuration space of each device and assigns memory and I/O regions that are guaranteed not used by other PCI devices. All the confutation will be performed automatically. The visible results is that the end user merely power down the PC,inserts the new cards, and then powers up the PC.
PCI configuration Registers:

PCI devices implement a 256 byte space for configuration registers which provide a software interface for board and system set-up.the first 64 byte locations are predefined by the PCI specification. The remaining 192 locations are device-specific.

General things How PCI Works: Installing a New Device. Once a new device has been inserted into a PCI slot on the motherboard 1. Operating System Basic Input/output System (BIOS) initiates Plug and Play (PnP) BIOS. 2. PnP BIOS scans the PCI bus for any new hardware connected to the bus. If new hardware is found, it will ask for identification.

3. The device will respond with its identification and send its device ID to the BIOS through the bus. 4. PnP checks the Extended System Configuration Data (ESCD) to make sure the configuration data already exists for the card. (If the card is new, then there will be no data for it.) 5. PnP will assign an Interrupt Request Line, Direct Memory Access, memory address and Input/output settings to the card, then stores the information in the ESCD. 6. When the Windows software loads, it will check the PCI bus and the ESCD to see if there is new hardware. Windows will alert the user that new hardware has been found if there is new hardware installed and will also identify the hardware. 7. Windows will determine the device and attempt to install its driver. The operating system may ask the user to insert a disk containing the driver or direct it to where the driver is located. In the event that Windows is unable to determine what the device is, it will provide a dialog window so the user can identify the hardware and load its driver.

ELECTRICAL CHARACTERISTICES:
The PCI bus has been defined for operation with either a 5 or 3.3 v power supply. The PCI connecter is used to connect peripherals cards to the motherboard of later generation PC compatible. The connector is a 98-pin card-edge connector.

PCI BUS GLOSSARY:

AGENT:

Each PCI device, whether a bus master or a target is referred to as a PCI agent. A local entity that operates on a computer bus. The term applies collectively to functions of a bus master of a bus slave, or to a combination or both.

Bridge:

The logic that connects one computer to another, allowed an agent on one bus to access an agent on the other.

Bus transfer:

The basic bus transfer mechanism of PCI.A burst is comprised of an address phases; and one or more data phases.

Bus commands: Signals used to indicate to a target the type of transaction the master is requesting. During the address phases of a PCI transaction, the initiator broadcasts a command on the C/BE bus. Bus device: A bus device can be either a bus master or target. MASTER: An agent which has an ability to obtain control of the interface and perform memory or I/O reds and writes to systems resources. Transaction:

 An address phase plus one or more data phases.

CONCLUSION:
Due to the need for growing data transfer rates among IO devices, the original PCI Architecture has become outdated

A new model of PCI, called PCI Express will replace the dated architecture giving it life for another decade.

REFERENCES:
Text book: Computer organization-v.c.hamacher-fifth edition. http://wikipedia.org www.codepedia.com http://people.bu.edu/bkia/PDF/06.%20PCI.pdf

SUBMITTED BY, NIKHIL K PRAKASH S2 MCA

Roll NO: 30