INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT163 Presettable synchronous 4-bit binary counter; synchronous reset

Product specication File under Integrated Circuits, IC06 December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Synchronous reset Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT163 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT163 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 17 21 11 51 33 HCT 20 25 14 50 35 ns ns ns MHz pF pF UNIT Notes

74HC/HCT163

Preset takes place regardless of the levels at count enable inputs (CEP and CET). For the 163 the clear function is synchronous. A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 fmax = -----------------------------------------------------------------------------------------------t P ( max ) (CP to TC) + t SU (CEP to CP)

fmax CI CPD

3.5 3.5

1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL VCC2 fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC 1.5 V

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 SYMBOL MR CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC NAME AND FUNCTION

74HC/HCT163

synchronous master reset (active LOW) clock input (LOW-to-HIGH, edge-triggered) data inputs count enable input ground (0 V) parallel enable input (active LOW) count enable carry input ip-op outputs terminal count output positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74HC/HCT163

Fig.4 Functional diagram.

FUNCTION TABLE INPUTS OPERATING MODE MR reset (clear) parallel load count hold (do nothing) Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = dont care = LOW-to-HIGH CP transition I h h h h h X X CP CEP X X X h I X CET X X X h X I X I I h h h PE X I h X X X Dn L L H count qn qn Qn L L
(1) (1) (1)

OUTPUTS TC

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74HC/HCT163

Fig.5 State diagram.

Fig.6

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74HC/HCT163

Fig.7 Logic diagram.

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC output transition time +25 40 to +85 40 to +125

74HC/HCT163

TEST CONDITIONS UNIT V CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS

typ. max. min. max. min. max. 55 20 16 69 25 20 36 13 10 19 7 6 185 37 31 215 43 37 120 24 20 75 15 13 100 20 17 100 20 17 100 20 17 220 44 37 0 0 0 4 22 26 230 46 39 270 54 46 150 30 26 95 19 16 120 24 20 120 24 20 120 24 20 265 53 45 0 0 0 4 18 21 280 56 48 320 65 55 180 36 31 110 22 19 Fig.8 ns

tPHL/ tPLH

Fig.8

ns

tPHL/ tPLH

Fig.9

ns

tTHL/ tTLH

Figs 8 and 9

ns

tW

clock pulse width HIGH or LOW set-up time MR, Dn to CP set-up time PE to CP set-up time CEP, CET to CP hold time Dn, PE, CEP, CET, MR to CP

80 16 14 80 16 14 80 16 14 175 35 30 0 0 0

17 6 5 17 6 5 22 8 6 58 21 17 14 5 4 15 46 55

Fig.8

ns

tsu

Figs 10 and 11

ns

tsu

Fig.10

ns

tsu

Fig.12

ns

th

Figs 10, 11 and 12

ns

fmax

maximum clock pulse 5 frequency 27 32

Fig.8

MHz

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard ICC category: MSI Note to HCT types

74HC/HCT163

The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT MR CP CEP Dn CET PE

UNIT LOAD COEFFICIENT 0.95 1.10 0.25 0.25 0.75 0.30

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tsu tsu tsu th propagation delay CP to Qn propagation delay CP to TC propagation delay CET to TC output transition time clock pulse width HIGH or LOW set-up time MR, Dn to CP set-up time PE to CP set-up time CEP, CET to CP hold time Dn, PE, CEP, CET, MR to CP 20 20 20 40 0 +25 40 to +85 40 to +125

74HC/HCT163

TEST CONDITIONS UNIT V CC (V) ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS

typ. max. min. max. min. max. 23 29 17 7 6 9 11 24 5 39 49 32 15 25 25 25 50 0 49 61 44 19 30 30 30 60 0 59 74 48 22 Fig.8 Fig.8 Fig.9 Figs 8 and 9 Fig.8 Figs 10 and 11 Fig.10 Fig.12 Figs 10, 11 and 12

fmax

maximum clock pulse 26 frequency

45

21

17

MHz

4.5

Fig.8

December 1990

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

AC WAVEFORMS

74HC/HCT163

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.

(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).

December 1990

10

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74HC/HCT163

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the MR set-up and hold times.

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.12 Waveforms showing the CEP and CET set-up and hold times.

APPLICATION INFORMATION The HC/HCT163 facilitate designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous reset.

Fig.14 Modulo-11 counter.

PACKAGE OUTLINES Fig.13 Modulo-5 counter. See 74HC/HCT/HCU/HCMOS Logic Package Outlines.

December 1990

11

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