Part I. Multiple choice questions.

Please select one answer for each question by circling the index of the answer. Five points for each question. You may also write down a short sentence in the provided space to explain your choice. If your choice is wrong but your explanation is partially correct, partial credit will be given.

1. The binary representation for -65 ten in 8 bits is (a) 01000110 (b) 10111111 (c) 11010110 (d) None of the above.

Ans. B. 65=01000001 -> 10111110 -> 10111111

2. The single precision floating number representation of -12.25 ten is (a) 1 10000100 100 0100 0000 0000 0000 0000 (b) 1 10000101 100 0000 0000 0000 0000 0000 (c) 0 10000100 100 0100 0000 0000 0000 0000 (d) None of the above. Ans. (d). 12.25=1.10001*2^3, so 1 10000010 100 0100 0000 0000 0000 0000

3. Which of the following correctly implements the for loop, assume that i is in $s0 and k is in $s1? (Hint: blt is branch if less than.)
for (i=0;i<10;i++) k += i;

(a)

li $s0, 0

li $t0, 10 L1: add $s1, $s1, $s0 blt $s0, $t0, L1

(b) L1:

li $s0, 0 li $t0, 10 add $s1, $s1, $s0 addi $s0, $s0, 1 j L1

(c) L1:

li $s0, 0 li $t0, 10 add $s1, $s1, $s0 addi $s0, $s0, 1 blt $s0, $t0, L1

(d) None of the above.

Answer: (c)

4. Which of the following statement about MIPS is true? (a) If a function is calling another function, the caller must save $ra. (b) Any call to a function must change the stack. (c) Both of the above. (d) None of the above.

Answer: a.

5. The opcode of lw instruction in MIPS is 100011. So, instruction lw $t0, 0($a0) should have an encoding of (Hint: $t0 is register 8, $a0 is register 4. The lw instruction starts with the opcode field, followed by rs, then rt, then the offset. For lw $t0, 0($a0), $t0 is rt, $a0 is rs.)

(a) 0x8c8f0000 (b) 0x8c890000. (c) 0x8d040000 (d) None of the above. 100011 00100 01000 0000 0000 0000 0000 1000 1100 1000 1000 0000 0000 0000 0000 Answer: (d) 0x8c880000

6. The following shows the design of ALU in MIPS. The ALU is controlled by four bits, Ainvert, Binvert, ALUOp1, and ALUOp0. If the operation to be carried out is sub, what should the four bits be? (Hint: Recall that the operation bits are used to select one of the four inputs to the MUX as output.)

(a) 1000

(b) 1101 (c) 0110 (d) None of the above. Answer: C.

7. Suppose you are implementing the jr instruction for the MIPS processor. Which of the following statement is true?

(a) It will involve a read from the register file. (b) It needs extra data path to be added to the MIPS processor supporting R-type, beq, lw, sw, and j. (c) Both of the above. (d) None of the above.

Answer:c.

Part II. Short answer questions.

Problem 1 (20 points) Read the MIPS code and answer the following questions. (a) What does function f1 do?

(b) What will f1 return in $v0?

Ans. 3 .text .globl main main: la $a0, la $a1, la $a2, li $a3, jal f1 A B C 10

li $v0,10 #exit syscall f1: li $v0, -1 ble $a3, $0, L3 li $t7, 0 L1: lw $t0, 0($a0) lw $t1, 0($a1) lw $t2, 0($a2) sub $t0, $t0, $t1 blt $t0, $t2, L2 addi $a0, $a0, 4 addi $a1, $a1, 4 addi $a2, $a2, 4 addi $t7, $t7, 1 blt $t7, $a3, L1 j L3 L2: addi $v0,$t7,0 L3: jr $ra .data A: B: C: .word 10,21,45,8,100,15,29,12,3,19 .word 2,5,33,5,20,1,53,52,5,5 .word 6,8,5,4,5,22,53,12,33,89

Problem 2 (20 points) Design a circuit that has two inputs, clk and X, and produces one output O. X may change every clock cycle, and the change happens at the falling edge. The circuit samples the input at every rising edge of the clock. If the input is 1, consider as read a 1, else read a 0. O is 1 (for one clock cycle, from positive edge to positive edge) if the last three bits read are 001. (a) (20 points) Draw the state diagram. Close to an arc, show X=1 or X=0 to indicate whether the change of state happens when X=1 or when X=0. S0: got nothing S1: got 0 S2: got 00 S3: got 001

X=1

S0

X=0 X=1

S1 X=0

X=1 S3

X=0 S2 X=1 X=0

(b) (10 points) Draw the next-state table, and derive the functions for D1 and D0. Derive the

output function. S0:00, S1:01, S2:10, S3:11. O = Q1&Q0

Q1 0 0 0 Q0 0 0 1 X 0 1 0 D1 0 0 1 D0 1 0 0

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 1 1 0 0

0 0 1 1 0

Q1Q0 X 0 1

00

01

11

10

Q1Q0 X 0 1

00

01

11

10

D1 = (~Q1&Q0&~X)|(Q1&~Q0);

D0 = (~Q1&~Q0&~X)|(Q1&X); (c) (10 points) Write down a Verilog module for this circuit. Use the following code as a

template.
module HW6P2 (clk, X, O); input clk, X; output O;

wire D1, D0, Q1, Q0, Q1bar, Q0bar; assign D0 = (~Q1&~Q0&~X)|(Q1&X); Dff1 C0 (D0, clk, Q0, Q0bar); assign D1 = (~Q1&Q0&~X)|(Q1&~Q0); Dff1 C1 (D1, clk, Q1, Q1bar); assign O = Q1&Q0; endmodule

Problem 3 (10 points) The following is the state diagram for a circuit that has two inputs, clk and X, and four states. Similar to the previous question, X may change every clock cycle, and the change happens at the falling edge of the clock. The circuit samples the input at every rising edge of the clock. If the input is 1, consider as read a 1, else read a 0. Assume that the circuit started in state S0. Please write in the figure to indicate the change of the state according to the input.

X=1

S0

X=0

S1

X=0 X=1

X=0 S3 X=0 X=1

X=1 S2

S0

S1

S1

S2

S3

S2

S3

S1

Problem 4 (15 points) (a). (10 points)Design the datapath for a MIPS processor supporting only R-type and beq instructions by making connections in the following figure. Assume the control signals have been properly generated.

(b) (5 points) Assume the delay for memory is 200ps, register file read is 50ps, ALU and the two adders are all 100ps. Assume that the set-up time for the D-flip-flops in PC and the register file is 10ps. ASSUME all other components have zero delay. What is length of the minimum clock cycle?
Answer: For the R-type: 200+50+100+10 = 360. For beq: 200+50+100+10=360. Both 360. (the clock-to-q delay is not considered in this particular problem)