SRI PADMAVATHI COLLEGE OF ENGINEERING Department of Electronics and Communication Engineering

SUBJECT CODE SUBJECT NAME FACULTY NAME CLASS OBJECTIVES To understand different methods used for the simplification of Boolean functions To design and implement combinational circuits To design and implement synchronous sequential circuits To design and implement asynchronous sequential circuits To study the fundamentals of VHDL / Verilog HDL UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 8 : : DIGITAL PRINCIPLES AND SYSTEM DESIGN. : Mr. S V DHARANI KUMAR : II Yr/III Sem/ IT

Review of binary number systems - Binary arithmetic Binary codes Boolean algebra and theorems - Boolean functions Simplifications of Boolean functions using Karnaugh map and tabulation methods Implementation of Boolean functions using logic gates. UNIT IICOMBINATIONAL LOGIC Combinational circuits Analysis and design procedures - Circuits for arithmetic operations - Code conversion Introduction to Hardware Description Language (HDL) UNIT III DESIGN WITH MSI DEVICES 8 9

Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable logic HDL for combinational circuits UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC 10

Sequential circuits Flip flops Analysis and design procedures - State reduction and state assignment - Shift registers Counters HDL for Sequential Circuits. UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC 10

Analysis and design of asynchronous sequential circuits - Reduction of state and flow tables Race-free state assignment Hazards. ASM Chart.

TEXT BOOKS 1. M.Morris Mano, Digital Design, 3rd edition, Pearson Education, 2007. REFERENCES 1. Charles H.Roth, Jr. Fundamentals of Logic Design, 4th Edition, Jaico Publishing House, Cengage Earning, 5th ed, 2005. 2. Donald D.Givone, Digital Principles and Design, Tata McGraw-Hill, 2007.6 Staff In-charge H.O.D

Principal

SRI PADMAVATHI COLLEGE OFENGINEERING

Department of Electronics and Communication Engineering LESSON PLAN

STAFF NAME: S V Dharani Kumar SUB CODE :

DEPT : ECE SUBNAME: Digital Principles and System Design

Total No.of

Sl.No

Hour Required

Topics
UNIT-1 Review of binary number systems, Binary Arithmetic Binary Codes Boolean Algebra and Theorems Boolean Functions Simplifications of Boolean Functions using Karnaugh Map and Tabulation methods Logic Gates UNIT-2 Combinational Circuits Analysis and Design Procedures Circuits for Arithmetic Operations Code Conversion Introduction to Hardware Description Language(HDL) UNIT-3

Book & Page No

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

1 1 1 1 2 2 2 2 2 2 1

01/08/2011 02/08/2011\ 03/08/2011 04/08/2011 05/08/2011 08/08/2011 09/08/2011 10/08/2011 11/08/2011 12/08/2011 16/08/2011 17/08/2011 18/08/2011 19/08/2011 22/08/2011 23/08/2011 24/08/2011

12. 13. 14. 15. 16.

2 2 2 2 2

Decoders and Encoders Multiplexers and Demuultiplexers Memory and Programmable logic HDL for Combinational Circuits UNIT-4 Sequential Circuits, Flip flops

25/08/2011 26/08/2011 29/08/2011 30/08/2011 02/09/2011 06/09/2011 07/09/2011 08/09/2011 09/09/2011 13/09/2011

17. 18. 19. 20. 21. 22. 23. 24. 25. 26.

2 2 1 1 2 2 2 2 2 2

Analysis and Design procedures State Reduction and State Assignment Shift Registers Counters HDL for Sequential Circuits UNIT-5 Analysis and Design of Asynchronous Sequential Circuits Reduction of State and Flow Tables Race Free State Assignment Hazards ASM Chart

14/09/2011 20/09/2011 21/09/2011 22/09/2011 23/09/2011 26/09/2011 27/09/2011 28/09/2011 29/09/2011 03/10/2011 04/10/2011 05/10/2011 06/10/2011 07/10/2011 10/10/2011 11/10/2011 13/10/2011 14/10/2011 H.O.D

Staff In-charge Principal