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loop of the modulator as shown in Fig. 11. With a 5-V power supply and a 50-MHz sampling rate, it has achieved a 59-dB dynamic range and a 57-dB peak signal-to-noise ratio with an oversampling ratio of 64.4 The maximum sampling frequency is about 57 MHz. The sampling rate is limited by the comparator, not the current switches. With an improved comparator, the modulator is expected to operate at even higher sampling rates. The performance of the current switch and the modulator is summarized in Table I.

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[14] J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology, IEEE J. Solid-State Circuits, vol. 30, pp. 11191127, Oct. 1995. [15] P. J. Lim and B. A. Wooley, A high-speed sample-and-hold technique using a Miller hold capacitance, IEEE J. Solid-State Circuits, vol. 26, pp. 643651, Apr. 1991. [16] V. Comino, M. S. J. Steyaert, and G. C. Temes, A first-order currentsteering sigma-delta modulator, IEEE J. Solid-State Circuits, vol. 26, pp. 167183, Mar. 1991.

VI. CONCLUSION A new high-speed differential current switch is presented. The clockfeedthrough problem has been successfully solved. With the help of an SRD, the current switch operates up to 100 MHz, with less than 0.1% error when implemented in a 2-m process. With a more advanced sub-micron process, this current switch is expected to operate in the multi-hundred megahertz range with a very good performance.5 A prototype continuous-time switched current modulator using this current switch has been implemented and tested, which validates performance of this current switch.

A Continuous-Time Common-Mode Feedback Circuit (CMFB) for High-Impedance Current-Mode Applications

Louis Luh, John Choma, Jr., and Jeffrey Draper

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REFERENCES
[1] T. S. Fiez and D. J. Allstot, CMOS switched-current ladder filters, IEEE J. Solid-State Circuits, vol. 25, pp. 13601367, Dec. 1990. [2] L.-J. Pu and Y. P. Tsividis, A transistor-only current-mode modulator, IEEE J. Solid-State Circuits, vol. 27, pp. 821830, May 1990. [3] R. Koch, B. Heise, F. Eckbauer, E. Engelhardt, J. A. Fisher, and F. Parzefall, A 12 bit sigma-delta analog-to-digital converter with 15 MHz clock rate, IEEE J. Solid-State Circuits, vol. SSC-21, pp. 10031010, Dec. 1986. [4] C. Lin and K. Bult, A 10-b, 500-MSample/s CMOS DAC in 0.6 mm , IEEE J. Solid-State Circuits, vol. 33, pp. 19481958, Dec. 1998. [5] H. C. Yang, T. S. Fiez, and D. J. Allstot, Current-feedthrough effects and cancellation techniques in switched-current circuits, in Proc. IEEE Int. Symp. Circuits Syst., May 1990, pp. 31683188. [6] B. Jonsson and N. Tan, Clock-feedthrough compensated first-generation SI circuits and systems, Analog Integr. Circuits Signal Processing, vol. 12, no. 3, pp. 201210, May 1997. [7] M. Song, Y. Lee, and W. Kim, A clock feedthrough reduction circuit for switched-current systems, IEEE J. Solid-State Circuits, vol. 28, pp. 133137, Feb. 1993. [8] H. Cha, S. Ogawa, and K. Watanabe, A clock-feedthrough compensated switched-current memory cell, IEICE Trans. Fundamentals, vol. E80-A, no. 6, pp. 10691072, June 1997. [9] C. Wu, C. Chen, and J. Cho, A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques, IEEE J. Solid-State Circuits, vol. 30, pp. 522532, May 1995. [10] M. Bracey, W. Redman-White, J. Richardson, and J. B. Hughes, A full Nyquist 15MS/s 8-b differential switched-current A/D converter, IEEE J. Solid-State Circuits, vol. 31, pp. 945951, July 1996. [11] B. P. Del Signore, D. A. Kerth, N. S. Sooch, and E. J. Swanson, A monolithic 20-b delta-sigma A/D converter, IEEE J. Solid-State Circuits, vol. 25, pp. 13111317, June 1990. [12] E. J. van der Zwan and E. C. Dijkmans, A 0.2-mW CMOS modulator for speech coding with 80 dB dynamic range, IEEE J. Solid-State Circuits, vol. 31, pp. 18731880, Dec. 1996. [13] L. Luh, J. Choma, and J. Draper, A 50 MHz continuous-time switchedcurrent modulator, Proc. IEEE Int. Symp. Circuits and Systems., vol. I, pp. 579582, May 1998.

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AbstractA continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to stabilize and minimize the offset of the common-mode voltage. A long-channel differential-difference amplifier (DDA) input stage enables this CMFB circuit to have a wide input voltage range without a serious linearity problem. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. This circuit has been immodulator in a plemented within a continuous-time switched-current 2- m CMOS process. It achieves a 1-V input voltage range with an active area of 100 m 60 m and a power dissipation of 270 W from a single 5-V power supply.

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Index TermsCompensation, continuous-time systems, feedback circuits.

I. INTRODUCTION Common-mode feedback circuits (CMFBs) stabilize common-mode voltages for differential-mode circuits. In the past, most differential-mode circuits have been implemented with voltage-mode circuits, where differential nodes in the signal paths have low impedance. In such circuits, the impedances of the common-mode circuits have insignificant effects on the node impedance. Since a low node impedance does not introduce low-frequency poles, stability problems are not an issue for designing CMFBs for voltage-mode systems. Recent advances in current-mode signal processing have proven that continuous-time current-mode circuits are good alternatives for highspeed signal processing. The use of fully-differential mode architectures for continuous-time current-mode circuits minimizes the noise injected from the power rails and the environment and also increases the available dynamic range. However, continuous-time differential current-mode circuits introduce unique requirements for common-mode feedback circuits. Since differential nodes in current-mode circuits normally have high impedances, the impedance of the CMFB may have a significant effect on the node impedance. Variation in the node impedances in current-mode circuits usually results in changes in the locations of the

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4The required higher oversampling ratio and reduced resolution is mainly caused by excessive loop delay, which is caused by the comparator and the continuous-time integrators, which require whole clock cycles to complete integration. 5Our later prototypes of modulators show 110 and 400 MHz sampling rates for 1.2-m and 0.5-m CMOS processes, respectively.

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Manuscript received April 1999; revised December 1999. This work was supported by DARPA under Contract DABT63-95-0136). This paper was recommended by Associate Editor F. Maloberti. The authors are with the University of Southern California, Los Angeles, CA 90089 USA. Publisher Item Identifier S 1057-7130(00)03125-6.

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Fig. 1. pair.

The (a) DDA CMFB can be simplified as (b) a single-stage differential

poles and zeros of the systems transfer function, which impacts the system performance. Stability problems may also occur. For example, high-impedance differential nodes cause low-frequency poles. If the CMFB itself has another low-frequency pole, this CMFB circuit may be unstable. Accordingly, common-mode feedback current-mode circuits must satisfy the requirements of very high input and output impedances and stable response. This paper proposes a stand-alone continuous-time common-mode feedback circuit, which can be inserted into any current-mode circuit without changing or upsetting the existing circuit. It is designed with very high output impedance to preserve the original locations of the poles and zeros. It also exhibits a wide operating range and high internal loop-gain to stabilize the common-mode voltage and minimize the common-mode offset voltage. A special compensation scheme is used to guarantee the stability of this circuit. In Section II, different approaches for implementing common-mode feedback circuits are briefly reviewed. Their deficiencies are discussed to reveal the necessity of further improvement for continuous-time current-mode operation. Section III describes the proposed common-mode feedback circuit, and an experimental result is shown in Section IV. II. DIFFERENT APPROACHES CMFBs stabilize common-mode voltages for differential-mode analog systems by means of adjusting the common-mode output currents. The two differential input(output) voltages are averaged to form a common-mode voltage (VCM ), which is compared with the designated reference common-mode voltage (VRCM ). The difference is then amplified and converted into the common-mode output current to adjust the common-mode voltage (VCM ). Most of the currently used common-mode feedback circuits fall into the following three categories: 1) switched-capacitor CMFB; 2) differential difference amplifier (DDA) CMFB; 3) resistor-averaged CMFB. 1) Switched-Capacitor CMFB: The switched-capacitor CMFB uses two equal-sized capacitors to average the voltages of the two differential nodes [1], [2]. Suffering from clock-injected (switching) noise, switched-capacitor common-mode feedback circuits are suitable only for sampled-data circuits [1], [2]. Since the switched-capacitor CMFB is too noisy to be used in continuous-time current-mode circuits, no further discussion of this type of CMFB is given in this paper. 2) DDA CMFB: CMFBs implemented by DDAs use four identical transistors to average and compare the common-mode voltages [3][6] (as shown in Fig. 1). Due to the limited input range and nonlinearity of the differential pairs, DDA CMFBs are suitable for circuits

with relatively small voltage swings. The input range and linearity can be improved, however, by reducing the aspect ratios (W/L) of the MOS transistors (M1M4) or increasing the bias current source (I1 , I2 ). The use of transistors with small aspect ratios (or long-channel transistors) reduces the transconductance gain of DDA circuits and leads to more common-mode offset voltage (jVCM -VRCM j). 3) Resistor-Averaged CMFB: Resistor-averaged common-mode feedback circuits use resistors to average the voltages of the two differential nodes and send the result to a differential pair to compare with VRCM [7], [8] (as shown in Fig. 2). This technique reduces the common-mode voltage error caused by the nonlinearity of the differential pair. The voltage swing ranges are not limited by the differential pair, and hence, more voltage swing is allowed without a significant offset of common-mode voltage. The disadvantage of the resistor-averaged CMFB is the requirement of large-valued resistors. Not only do these resistors require more silicon area, but they also load down the output and cause a reduction of the gain. Moreover, they affect output impedances, which are very critical in current-mode systems since they influence the pole and zero locations. An important performance factor for common-mode feedback circuits is the transconductance gain (ACMFB ). ACMFB is equal to the open-loop common-mode output current (IO ) divided by the common-mode error voltage (VCM:ERR ), which is the difference between the common-mode output voltage (VCM ) and the reference common-mode voltage (VRCM )

ACMFB =

IO VCM:ERR

= VCMI 0 VRCM :
O

With a large ACMFB , a smaller common-mode offset voltage (jVCM:ERR j) and a faster response can be achieved. Most continuous-time CMFB circuits use single-stage structures [3][7]. For single-stage DDA CMFBs [3][5], if the nonlinear effect of the differential pair can be ignored, the CMFB circuits can be simplified as shown in Fig. 1. Single-stage resistor-averaged CMFB [7] circuits can be simplified as shown in Fig. 2. The differential output current is then mirrored to the output as the common-mode output current. From Figs. 1 and 2, we find that the transconductance of a single-stage CMFB is roughly equal to the transconductance gain of a differential pair. The typical transconductance gain for a differential pair is in the range of 10100 A/V. When a 1 A common-mode offset current is applied on the output, it will cause a 10100 mV common-mode offset voltage (jVCM:ERR j). Some systems may not tolerate this amount of common-mode offset voltage. One solution to improve the transconductance gain is to use a twostage architecture [6], [8]. With one extra stage, the gain increases about 100 times, which greatly reduces the common-mode offset voltage. However, the two-stage structure has a stability problem and must be compensated. Two places in the CMFB circuit contribute to the stability problem. One is caused by the two external differential nodes. The other is an internal node which connects the first stage to the second stage. For voltage-mode CMFBs with low output impedances [8], the pole caused by the external node is located in a very high frequency range. This makes the compensation easier by simply moving the pole generated by the internal node to a low-frequency location. For current-mode systems, the external nodes may have high impedances and result in a pole at very low frequencies, which is difficult to compensate. In this paper, a two-stage CMFB circuit for high-impedance current-mode circuits is presented. Frequency compensation is achieved by moving one pole to be the dominant pole and introducing an extra

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(a) Fig. 2. The (a) resistor-averaged CMFB can be simplified as (b) a single-stage differential pair.

(b)

pair of pole and zero for polezero cancellation. The linearity of the DDA is improved by using long-channel transistors for the input stage to accommodate the input voltage swing.

Without MC and CC , the two dominant poles P1 and P2 are located at node B (P1 ) and point A (P2 ). P1 is due to R1 , CB , and the gate-todrain overlap capacitance (CGD ) of M2 (with Miller effect)
P1

III. CIRCUIT DESIGN The proposed continuous-time CMFB circuit is a two-stage DDA CMFB as shown in Fig. 3. The first stage is composed of M1M7 and current sinks M14M17. The second stage is composed of M8M11. By using a two-stage structure, the DDA CMFB design is not forced to trade off between gain and input voltage range. The first stage can be optimized to have a wide range to accommodate the input voltage swing, while the second stage can be optimized to have a large gain. A cascode output stage design (M8M11) enables this CMFB to have a very high output impedance, retaining the high-impedance property of the two differential nodes. This two-stage structure, however, introduces two low-frequency poles and has a stability problem. These two poles are introduced by point A (the two differential nodes) and node B (connection between first stage and second stage). A special compensation scheme is required to stabilize the loop. This scheme consists of adding the transistor MC and capacitance CC (as shown in Fig. 3) and is further discussed and analyzed in Section III-A. Techniques for optimizing performance of this two-stage CMFB circuit are presented in Section III-B. A. Compensation Scheme for Proposed CMFB A traditional pole-split compensation scheme for two-stage amplifiers cannot be used in this circuit. Since the pole-split compensation scheme requires a Miller capacitor connected between the input and output of the second stage, two compensation capacitors connected between point A and node B would be required. These compensation capacitors would cause extra capacitance on the differential nodes, which would affect the locations of the poles and zeros of the system. Thus, this scheme is not viable. Frequency compensation for this common-mode circuit is achieved by adding CC and MC . The equivalent small-signal model for this circuit can be expressed as in Fig. 4(a), where RDi is the equivalent output resistance of transistor Mi (i 2 f1  11g), RL and CL represent the load resistance and load capacitance, respectively, CB is the total parasitic capacitance at node B, and RM is the equivalent resistance of MC . For simplicity, this circuit is equivalent to Fig. 4(b). Where R1 = RD2 kRD3 kRD6 , and R2 = RL kRD9 . If this CMFB is properly designed, RD9 should be much greater than RL , and hence, R2  RL .

R1

2(

+ CGD2

01

m2 1 R1 )

(1)

Note that CGD2 also introduces another pair of pole and zero. However, because CGD2 is very small (in the femto farad range), this pair of pole and zero has an insignificant effect on the loop gain and is therefore ignored in the following analysis. Since CC is parallel with CGD2 and CC  CGD 2 , ignoring CGD 2 does not affect the analysis result. Whereas the second stage is a cascode stage, the Miller effect is neutralized, and therefore, CGD8 and the parasitic capacitance at point A have an insignificant effect on P2 when compared with CL . Thus, the second pole is
P2

R2

01 2 1

(2)

The loop gain of this CMFB is

A

V0 =

m2 1 gm8 1 R1 1 R2

S P1

S P2

(3)

and VOUT is given by

VOUT

V 0 1 (VRCM 0 VCM ):

(4)

Accordingly, this CMFB functions as an OPAMP with VRCM connected to the noninverting input and VCM connected to the inverting input. With the output connected to the input (VOUT connected to VCM ), this CMFB operates as a unity-gain voltage follower, which forces the output (VOUT , averaged voltage of the two differential nodes) to follow VRCM . With the compensation transistor and capacitor MC and CC , the loop gain can be solved from the equivalent circuit in Fig. 4(b),
g A

VC

m2 1 gm8 1 R1 1 R2 1

1
S

S Z

= 1

0 01

S P2

1 (1 +

K1

+ K2

(5)
S

2)

where
Z

MC 1 CC K1 = gm2 1 R1 1 RMC 1 CC + R1 1 CB + (R1 + RMC ) 1 CC K2 = R1 1 R2 1 CB 1 CC :

=
R

(6) (7) (8)

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(a)

(b) Fig. 3. (a) Proposed CMFB circuit and (b) its compensation scheme.

The locations of the two newly generated poles can be calculated by finding the roots of the second term of the denominator in (5)
1
S

Thus, from (9), the root of the second term of the denominator of (5) can be easily solved and the two new poles are then
P1
0

0 16
K

K1

04

K2

By inspection, CC  CB , gm2 1 R1  1, gm2 1 R1 1 RMC 1 CC  R1 1 CB . R1 and RMC are about the same order. (R1 + RMC ) 1 CC  2R1 CC . Furthermore, gm2 1 RMC  2, which leads to gm2 1 R1 1 RMC 1 CC  (R1 + RMC ) 1 CC . K1 can then be simplified as
K1

(9)

m2 1 R1 1 RMC 1 CC

01

(13)

m2 1 R1 1 RMC 1 CC

P3

(10) B. Performance Optimization (11)

0! 01

(14)

K1

K2

R1

is normally about the same order as R2 . The product gm 1 RMC is about the voltage gain of a single-stage amplifier (MOS inverted amplifier), and hence gm 1 RMC  1. Also, CC  CB . These characteristics lead to
K1

2 2 2 2 m2 1 R1 1 RMC 1 CC R1 1 R2 1 CB 1 CC 2 2 gm2 1 R1 1 RMC 1 CC  : R2 1 CB

By using a two-stage structure, there are more degrees of freedom in optimizing the performance of this CMFB circuit. The first stage is optimized to accommodate the input voltage swing. The second stage is optimized to have sufficiently large output impedance and wide bandwidth. The size of MC and CC can be determined from Section III-A (15) to have
R

K2

0!

K1

 41

K2 :

(12)

MC 1 CC

L 1 CL :

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(a)

(b) Fig. 4. (a) Equivalent small-signal model of the proposed CMFB circuit. (b) Simplified small-signal model of (a).

1 jP2 j, the loop gain has a maximum phase shift gain. When jZC j  in the unity-gain bandwidth of about 0 , which gives a 45 phase margin within the unity-gain bandwidth.The proposed compensation scheme keeps P2 unchanged but moves P1 to a lower frequency range. Besides this, it generates an extra pair of pole and zero. Since the newly generated pole is located at a very high frequency, it has an insignificant effect on the frequency response and stability. By properly placing the newly generated zero, this zero can be used to cancel out P2 , which 0 makes P1 the only dominant pole. To achieve this, we need

=6

135

Fig. 5.

A second-order continuous-time switched-current

61 modulator.

ZC  P2 ) RM C 1 CC  R2 1 CL  RL 1 CL :
The transfer function of the loop gain becomes
8  (1 + (g 22 11 R11 11 R2 1 g 1 C )S ) g R R 1  (1 +g(g2 12 RR11 RR 1 g1 C8 )S ) : 1 1
m m m MC C m L m m L L

(15)

To optimize the first stage, if the current generated by each of the current sinks M14M17 is I , the maximum available input range is equal to

VIN:MAX 

 1 COX 1 W

81I 1L

AV C

(18)

(16)

From this equation, the length, L, and the width, W , of M1M4 and the current I can be determined. However, to avoid common-mode offset voltages caused by the nonlinearity of the input differential pairs, the input range should be slightly smaller than this in practice. In other words, the actual aspect ratios of M1M4 should be smaller than that calculated from this equation. When optimizing the second stage, besides the output impedance and the bandwidth considerations, M8 and M10 should have a long channel to improve the matching between these two transistors. Any mismatch between these two transistors will cause a differential-mode offset, which may cause a dc offset for the overall system. This CMFB circuit can tolerate a range of ZC variation. If the third and higher poles are much higher than the unity-gain bandwidth (as is normally true if this CMFB is designed properly), ZC does not need to be exactly equal to P2 . ZC can be as large as six times P2 , and this CMFB will still have a stable response. When ZC P2 , zero-pole cancellation is achieved, and this CMFB has a dominant pole response. When jZC j < jP2 j, the loop gain has a small bandwidth, but it offers a better phase margin for this circuit to have a very stable response. When jZC j > jP2 j, ZC is used to correct the phase shift of the loop

The unity-gain bandwidth becomes

!unity 

gm8 : CL

(17)

This unity-gain bandwidth determines how fast this CMFB can respond to a change of the common-mode offset voltage on the differential nodes. As the unity-gain bandwidth solely depends on the gm of the second stage and the value of load capacitances, gm of the first stage does not affect the speed of this CMFB. Accordingly, the first stage can be optimized to satisfy the linearity requirement without affecting the CMFBs speed, while the second stage should have a sufficiently large gm to satisfy the speed requirement. IV. EXPERIMENT RESULT The proposed CMFB has been implemented within a second-order continuous-time switched-current modulator (Fig. 5) in a 2-m CMOS process with a single 5-V power supply and a designated common-mode voltage of 2.3 V [9]. The accuracy and stability of the

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Fig. 7. (a)

Open-loop transconductance of the proposed CMFB.

(b) Fig. 6. V versus differential input voltage: (a) within (b) zoom-in view within the 1-V range.

62-V range and

common-mode voltages in the modulator are important since they affect the gain of the voltage-to-current converter (in Fig. 5) due to the body effect [9]. The proposed CMFB is designed to accommodate a 61-V differential voltage swing with load capacitors equal to 2 pF, a load resistance of about 5 M and I (in Fig. 3) equal to 5 A (IREF in Fig. 5 10 A), which places the second pole (CL 1 RL ) at about 20 kHz. Fig. 6 shows the relationship (dc characteristics) between common-mode error voltage VCM:ERR , and the differential input voltage.1 Fig. 6(b) shows the zoom-in view within 61 V, where jVCM:ERR j is less than 0.5 mV within the designated differential input voltage range.2 The low-frequency transconductance gain is about 2 mA/V (as shown in Fig. 7). Compared to the transconductance gain of an ordinary single-stage CMFB (about 20100 A/V), this CMFB circuit achieved 3040 dB improvement. With a 1-A common-mode offset

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Fig. 8. Open-loop voltage gain of the proposed CMFB. (a) The first stage and overall voltage gain. (b) The phase response of the overall voltage gain.

1Simulations were performed by applying differential voltages to the closed-loop CMFB with R and C connected to the differential nodes. 2In this simulation, the mismatch between transistors is ignored.

current applied to the differential nodes, only a 0.5-mV common-mode voltage offset is induced. For optimization of frequency compensation, instead of having RM C 1 CC  RL 1 CL , we implemented a slight overdesign by having RM C 1 CC > RL 1 CL to accommodate process variation. This trades off a bit of response speed for guaranteed stability. The SPICE simulation of the open-loop transconductance of this

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TABLE I EXPERIMENTAL RESULTS

V. CONCLUSION A continuous-time common-mode feedback circuit is presented. The two-stage CMFB structure minimizes the common-mode error voltage (3040 dB improvement) without a stability problem. The high output impedance (75 M compared to 110 k for resistor-averaged CMFB) and small common-mode offset voltage (<0.5 mV) make it an ideal CMFB, even for a high-impedance current-mode system. The special compensation scheme makes the frequency compensation easy to achieve without affecting the locations of poles or zeros of the system. The proposed CMFB can be easily implemented in any differential mode circuit without modifying differential amplifiers or other circuits in the system. The measured result of a second-order continuous-time switched-current modulator validated the performance of this CMFB.

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REFERENCES
[1] R. Castello and P. R. Gray, A high-performance micropower switchedcapacitor filter, IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 11221132, Dec. 1985. [2] D. Senderowics, S. F. Dreyer, J. H. Huggins, C. F. Rahim, and C. A. Laber, A family of differential CMOS analog circuits for a PCM codec filter chip, IEEE J. Solid-State Circuits, vol. SC-17, pp. 10141023, Dec. 1981. [3] T. Kwan and K. Martin, An adaptive analog continuous-time CMOS biquadratic filter, IEEE J. Solid-State Circuits, vol. SC-26, pp. 859867, June 1991. [4] J. Silva-Martinez, M. S. Steyaert, and W. Sansen, Design techniques for high-performance full-CMOS OTA-RC continuous-time filters, IEEE J. Solid-State Circuits, vol. 27, pp. 9931001, July 1992. [5] K. Lee and R. G. Meyer, Low-distortion switched-capacitor filter design techniques, IEEE J. Solid-State Circuits, vol. SC-20, pp. 11031113, Dec. 1985. [6] Z. Czarnul, S. Takagi, and N. Fujii, Common-mode feedback circuit with differential-difference amplifier, IEEE Trans. Circuits Systems I, vol. 41, pp. 243246, Mar. 1994. [7] M. Banu, J. M. Khoury, and Y. Tsividis, Fully differential operational amplifiers with accurate output balancing, IEEE J. Solid-State Circuits, vol. SC-23, pp. 14101414, Dec. 1988. [8] J. N. Babanezhad, A low-output-impedance fully differential OP Amp with large output swing and continuous-time common-mode feedback, IEEE J. Solid-State Circuits, vol. SC-26, pp. 18251833, Dec. 1991. [9] L. Luh, J. Choma, and J. Draper, A continuous-time switched-current modulator with reduced loop delay, in Proc. IEEE 8th Great Lakes Symp. VLSI, Feb. 1998, pp. 286291.

Fig. 9. Microphotograph of the proposed CMFB, which is implemented as part of a continuous-time switched-current modulator.

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CMFB in Fig. 73 shows the zero is located at about 10 kHz (<20 kHz generated by RL 1 CL ), and the pole is located at about 200 Hz. The open-loop voltage gain (with CL and RL connected to the outputs) is shown in Fig. 8. The low-frequency loop gain is about 7 KV/V (77 dB) with a phase margin of about 80 . By observing the first-stage gain and the overall gain in Fig. 8(a), we can find that the first-stage gain is nullified (reduced to 1) by the feedthrough effect (zero) and reduces the CMFB to a single-stage CMFB circuit. The single-stage response at high frequencies avoids the stability problem, while the two-stage performance at low frequencies maximizes the loop gain and minimizes the common-mode offset error. The performance summary is shown in Table I. Fig. 9 shows a microphotograph of the proposed CMFB circuit. The size of this CMFB is 100 m 2 60 m. A second-order continuous-time switched-current modulator with the proposed CMFB has been implemented in a 2-m CMOS process and achieved 59-dB dynamic range in a 390-kHz bandwidth with a 50-MHz clock. The stable modulator performance is achieved by the use of the proposed common-mode feedback circuit to stabilize the operation of all the components in the modulator.

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Comments on A Systematic Approach for Design of Digit-Serial Signal Processing Architectures

B. E. Sa lam, G. Cosgl, and G. Dndar g

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In the above brief,1 Parhi has modified the square-root algorithm and the relevant architecture presented in his reference [1]. Although the example computed in this note, also repeated here in Fig. 1(a), gives

Manuscript received 1/28. The authors are with the Department of Electrical and Electronics Engineering, Bo azici University, Bebek 80815, Istanbul, Turkey. g Publisher Item Identifier S 1057-7130(00)03128-1.
1K. K. Parhi, IEEE Trans. Circuits Syst., vol. 38, no. 4, pp. 358375, Apr. 1991.

3This test is performed by connecting both inputs (gates of M1 and M4) to a voltage source, shunting the outputs to two 2.3-V dc voltage sources, and measuring the output currents.

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