CS221:DigitalDesign CS221: Digital Design

LogicComponents&QMLogic Minimization

Dr.A.Sahu DeptofComp.Sc.&Engg. Dept of Comp. Sc. & Engg. IndianInstituteofTechnologyGuwahati

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Out e Outline
Karnaugh mapwith>=5variable StudyofComponents d f
Multiplexor,Decoder LogicImplementationUsingMUX&Decoder Mux: 7 Segment Display Mux:7SegmentDisplay 4BitAdder

Q i M Cl k (QM) L i Mi i i ti QuineMcCluskey (QM)LogicMinimization MoreExamples

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Multiple OutputCircuits MultipleOutput Circuits

Manycircuitshavemorethanoneoutput Cangiveeachaseparatecircuit,orcanshare h h gates Ex:F=ab +c,G=ab +bc
a b F c a b F c

(a)
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(b)

Option 1: Separate circuits

Option 2: Shared gates

Decoder
Receptioncounter:Whenyoureacha AcademicInstitute Academic Institute
ReceptionistAsk:WhichDepttoGo? Receptionist Redirect you to some building ReceptionistRedirectyoutosomebuilding accordingtoyourAnswer.

Decoder : knows what to do with this: Decode Decoder:knowswhattodowiththis:Decode Ninput:2N output MemoryAddressing
Addresstoaparticularlocation
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Decoders
Decoder:Popularcombinationallogicbuilding block,inadditiontologicgates block in addition to logic gates
Convertsinputbinarynumbertoonehighoutput

2input decoder: four possible input binary 2inputdecoder:fourpossibleinputbinary numbers

So has four outputs one for each possible input Sohasfouroutputs,oneforeachpossibleinput binarynumber
d0 0 0 i0 i1 d1 d2 d3
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1 0 0 0 1 0 i0 i1

d0 d1 d2 d3

0 1 0 0 0 1 i0 i1

d0 d1 d2 d3

0 0 1 0 1 1 i0 i1

d0 d1 d2 d3

0 0 0 1

 Internaldesign

DecodersandMuxes Decoders and Muxes

ANDgateforeachoutputtodetectinputcombination

Decoderwithenablee
Outputsall0ife=0,Regularbehaviorife=1

ninputdecoder:2n outputs i d d 2
1 i0 i1 e 1

d0 d1 d2 d3 1

0 0 0 1

i1 i0 i1i0 i1i0 i1i0 i1i0 i1i0

d0 d1 d d2 d3

d0 1 1 i0 i1 e 0 d1 d2 d3

0 0 0 0

i1
6

i0

CoversAll Covers All Minterms

4to16Decoderusingtwo3to8 Decoders d
D0toD7

D8toD15

BooleanFunctionImplementation usingDecoders d
Using a nto2n decoder and OR gates any Usingan to 2ndecoderandORgatesany functionsofnvariablescanbeimplemented. Example: Example:
S(x,y,z)= (1,2,4,7),C(x,y,z)=(3,5,6,7)

FunctionsSandCcanbeimplementedusinga 3to8decoderandtwo4inputORgates
Decoder:CoversAllMinterms Decoder: Covers All Minterms

ImplementationofSandC Implementation of S and C

X Y Z

ConfigurableFunctionusingDecoder &Memory
1 0 1 1 0 0 1 1

a b c

Decod er

AnyFunctioncanbe implemented FunctiondependonMemory Elements,Direct El Di correspondencetoTruthTable

8rowx1col memory

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Multiplexor(Mux) Multiplexor (Mux)

Mux:Anotherpopularcombinationalbuildingblock
RoutesoneofitsNdatainputstoitsoneoutput,basedon outes o e o ts data puts to ts o e output, based o binaryvalueofselectinputs
4inputmux needs2selectinputstoindicatewhichinputtoroute g through 8inputmux 3selectinputs Ninputs log2(N)selects

Like a railyard switch Likearailyard

Mux Internal Design InternalDesign

i0

i0 (1*i0=i0) 1
d

21 i0 i1 d s0 0 i0 i1

21 d s0 0 0 i0 i1

21
i1

d s0 0 1 0s0

0
a

i0 (0+i0= i0)

2x1mux 2x1 mux

Mux Internal Design InternalDesign

4 1 i0 i1 i2 i3 s1 s0 i3 d i0 i1 d i2

4x1mux
s1 1 s0 0

CoversAll Minterms

Muxes CommonlyTogether Nbit Mux

a3 b3 a2 b2 a1 b1 a0 b0 s0 0 i0 2 1 i1 s0 d i0 2 1 i1 s0 d i0 2 1 i1 s0 d 0 i0 2 1 i1 s0 d A B 4 4 I0 I1 s0 c3 s0 c2 c1 c0 0 4-bit 2x1 4 D Simplifying notation: 4 C C is short for

Ex:Two4bitinputs,A(a3a2a1a0),andB(b3b2b1b0)
4bit2x1mux (justfour2x1muxes sharingaselectline)can selectbetweenAorB

Multiplexed7SegmentDecoder Multiplexed 7 Segment Decoder

HOUR
HR1 4

MIN

HR2

MUX
MIN1 4 4

7 Segment Decoder D d

DEMUX

MIN2

2bitcounter g Ruuning AtKhZ

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ImplementinglogicFunctionusing MUX
4 1 1 0 1 0 i0 i1 i2 i3 s1 s0
A B

F(A,B)=m(0,2) F (A B) (0 2)

4x1mux
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