FINAL REPORT Ashutosh Jaiswal

Evaluation and Real Time Implementation of Different Techniques for a Wireless Indoor
Communication Channel and a Comparative Study of their effect on the BER

Ashutosh Jaiswal
Master Degree Project Report
Aug 2007
Abstract coding techniques and then comparative evaluation

combined with block interleaving technique. Most
A lot of research has already been done on various of the indoor channel are characterized by low
coding techniques for an indoor communication Doppler Spreads implying a time invariant
channel to improve the performance and reliability. channel. In this project the Doppler spread is
This project focuses on three different negligible as the transmitter, receiver and the
communication schemes, their implementation and underlying channel are stationary. The
a comparative evaluation of performance based on performance of the system was evaluated with
the Bit Error Rate (BER). BER is used as a convolutional coding and block interleaving for a
measure because it is directly proportional to the fading Indoor Rician Channel.
characteristics of the channel and these BER was evaluated for various Signal to noise
characteristics pose challenges for transmitting ratio’s. However, because there was no means to
data over space, for which various schemes to measure the signal to noise ratio, distance between
transmit and receive data are required. In this the transmitter and receiver was varied as it is
project the main schemes being studied and directly proportional to the SNR. The various steps
implemented are convolutional encoding, Viterbi that were carried out for evaluation of performance
decoding and block interleaving. are,
Keywords: Convolutional encoding, Viterbi
i) Transmission and reception of the data over
decoding, channel performance, BER, Interleaving
the channel without any coding/decoding.
ii) Transmission and reception of the data over
1 . Introduction
the channel with convolutional encoding
and Viterbi decoding.
Forward Error Correction or channel coding
iii) Transmission and reception of the data over
techniques form an essential block in the digital
the channel with encoding/decoding and
communication system design. This area has been
with block interleaving.
well researched and efficient codes have been
developed for various applications. The For each of these configurations the BER was
performance of various codes for digital wireless determine and a plot between the BER and the
applications has also been well researched. Indoor distance (between transmitter and receiver) was
wireless networking applications have become used to evaluate the performance. Real time
very popular as they provide flexibility of location embedded system implementation of convolutional
with low infrastructural and maintenance costs. encoding, Viterbi decoding and block interleaving
Proper modeling of the wireless indoor channel is was accomplished using Texas Instruments
critical to evaluate the performance of the end-to- TRF6903 bi-directional RF Transceiver and
end system. MSP430 Ultra Low Power Baseband
Microcontroller.
The main focus of this masters project was to
evaluate the performance of indoor point-to-point
wireless data transmission system with channel
1 St. Mary’s University, San Antonio

Master Degree Project Report, Aug 2007
2 . TRF 6903 Transceiver common data rates, is provided by the TRF6903.

This feature reduces the need for extensive
The TRF 6903 single chip solution is an integrated oversampling and data decisions in the micro-
circuit intended for use as a low-cost multiband controller during receive. During transmit, the data
FSK or OOK transceiver to establish a frequency clock can be used to clock the transmit data from
programmable, half duplex, bi-directional RF link. the microcontroller to the TRF6903 at predefined
The multichannel transceiver is intended for digital data rates.
modulated applications in the North American and Figure 1 shows all the interface definitions
European 315-MHz, 433-MHz, 868-MHz and 915- between the MSP 430 and the TRF6903. Some of
MHz ISM bands. It operated down to 2.2 V and is these interface pins are optional and may not be
designed for low power consumption. Two fully needed to establish a functional wireless link.
programmable operation modes, Mode0 and
Mode1, allow fast switching between two
preprogrammed settings without reprogramming
the device.
2.1. Transmitter
The transmitter consists of an integrated VCO and

tank circuit, a complete synthesizer, and a power
amplifier. The dividers, pre-scaler, and a reference
oscillator require only the addition of an external
crystal and a loop filter to provide a complete PLL
with a typical frequency resolution of better than
200 kHz. Since the typical RF output power is Figure 1: System Block Diagram for Interfacing to the
approximately 8 dBm, no additional external RF MSP430
power amplifier is necessary in most applications.
2.4. TRF6903 Evaluation Board
2.2. Receiver The evaluation kit has two circuit boards, where
each of them can be used as a transceiver. Each
The integrated receiver is intended to be used as a
unit has a TRF6903 RF transceiver and a
single-conversion FSK/OOK receiver. It consists
MSP430F449 microcontroller. Each board is
of low noise amplifier, mixer, limiter FM/FSK
capable of sending and receiving half duplex
demodulator with an external LC tank circuit.
wireless data. The MSP430 MCU flash memory
can be repeatedly erased and reprogrammed. The
2.3. Baseband Interface on-chip emulation logic allows real-time
debugging and fast code development. The MCU
The TRF 6903 can easily be interfaced to a can be programmed via a USB-JTAG interface and
baseband processor such as the Texas Instruments the data to transmit and receive uses the RS-232
MSP430 ultralow-power microcontroller. The port.
TRF6903 serial control registers are programmed The set up used to carry out the evaluation will
by the MSP430 and the MSP430 performs be discussed in latter sections.
baseband operations in the software. A
synchronized data clock, programmable for most

3 . System and Protocol Definition The MAX3232 3-V to 5.5-V RS232 line driver is
used for logic level voltage conversion between the
3.1. System Definition computer and the MSP-430 microcontroller. The
signal at the UART TX line of the microcontroller
The overall wireless UART system setup is shown in Figure 3. The start bit is a high pulse,
implemented in the firmware consists of two 26.04 micro-secs long (38.4 kbps). Then the first
computers exchanging data wirelessly. The data data bit is sent beginning with the LSB. After 8
transmission is half-duplex and bi-directional. The data bits, the stop bit arrives generating a low pulse
various phases of data transmission are illustrated on the RS-232 line.
in Figure 2.
3.2. Protocol Definition
The RS-232 protocol used to transfer data to and

from the computer and the RF protocol used to
transmit packets wirelessly is explained in the
following sub-sections.
Figure 3: RS-232 Protocol
3.2.2. Wireless Protocol
The protocol used for wireless packet transmission

is illustrated in Table 1.
Table 1: Wireless Protocol used for Packed Data Transfer

Bit Rate Bit Training Start Bit
(kbps) Duration Sequence Duration CODING
(us) (ms) (us)
19.2 52.06 6 156.18 NRZ
38.4 26.04 3 78.12 NRZ
51.2 19.53 2.5 58.59 NRZ
The entire wireless protocol consists of three parts:
i) Training sequence
ii) Start Bit
iii) Data packet that includes 32 bytes of data and
2 bytes of checksum
Figure 2: Various phases of data transmission
3.2.2.1. Training Sequence
3.2.1. RS-232 Protocol
Besides the ability to receive return to zero coded
The default protocol used for RS-232 serial signals, the TRF 6903 features the availability to
transmission and reception is 38.4 kbps data rate receive NRZ coded signals. This doubles the
with eight data bits, one stop bit and no parity. The maximum achievable data transmission rate.
firmware has been written to support this protocol.

The training sequence is a square wave signal 3.2.2.2. Start Bit

of equal high and low pulses. The voltage across
the sample-and-hold capacitor is charged up to the The start bit is shown in Figure 4. The purpose of
dc value of the received and demodulated signal. the start bit is to enable the reception of data by
After a long enough period to achieve good marking the beginning of the actual data package
accuracy of this reference voltage value, the and to synchronize the receiver. The length of the
TRF6903 is switched from reception in learning start bit can be within a wide range, but it must
mode, to reception in hold-mode. In the hold mode, enable a distinction to be easily made between the
the voltage across the sample-and-hold capacitor is pulses of the training sequence and the pulse of the
maintained. Typically the hold time is several start bit. In this firmware the pulse width is set to
seconds. This makes the reception of a signal with three times the pulse length of the training sequence,
many successive ones or zeros possible. giving a start bit of 78.12 us duration for a bit rate of
It has two purposes: The first is to enable the 38.4 kbps.
receiver to adapt to the transmitted signal, charge
the sample-and-hold capacitor to dc value of the 3.2.2.3 Data Packet
signal, and thereby enable reception of NRZ coded
signals. The second is to enable the receiver to The data packet is that part of the RF protocol that
distinguish between noise or invalid signals and the contains the actual data to be transmitted. The
valid data. firmware implements a data link for transmitting 32
Achieving these purposes allows the minimum bytes, as well as for transmitting two additional
length of the training sequence to be calculated. bytes containing the checksum for these 32 bytes.
The factors to be considered are run-in-time of the For data transmission the first two transmitted bytes
receiver (from standby to receive modes), the time are checksum of the transmitted data package as
during which the microcontroller on the receiver calculated by the sender, followed by 32 bytes of
side needs to recognize the training sequence, and actual data. These 34 bytes in the data package are
some overhead to minimize the number of training not separated by start and stop bits.
sequences that are unrecognized because of timing Figure 5 shows the data package when sending
problems. The firmware implemented in this the 32 bytes of data bytes.
project uses a training sequence of 3ms long.
Figure 4 shows the training sequence used in
the firmware.
Figure 5: Data Packet- Sending 32 Bytes of Data
4. TRF6903 Register Setup

Figure 4: Training Sequence
The TRF6903 is controlled through a serial interface.
There are five 24 bit control words (A, B, C, D and

E). The A and B words are almost identical and set process is depicted in Figure 7. Each step shown in
the device for two modes, designated as Mode0 and the flowchart is implemented as a function in the
Mode1, which are used to configure the transmit and firmware.
receive states. The C word sets the reference dividers,
the power amplifier bias, and contains various reset Table 2: TRF6903 Register Settings
bits. The D word is used to trim the external crystal REGISTER PARAMETER VALUE
frequency and tune the demodulator. The E word A PA Attenuation 0 dB
Mode 0 TX
contains the bit-rate select, data clock control bits and Charge Pump 0.5mA
the power amplifier bias control registers. Frequency Band 915Mhz
The registers used with the wireless UART B PA Attenuation 0dB
firmware are shown in Table 2. Mode 0 RX
Modulation FSK
Brownout Threshold 2.2V
5. The Graphic User Interface (GUI) Brownout Detector OFF
C Reference Divider 48
Reference Frequency 409.6 KHz
A GUI provided by Texas Instruments is being used
D Crystal Tune 20.23 pF
for transmission and reception of data for test Reset Signal for PFD Derived from
purposes. A snapshot of the GUI is shown in Figure prescaler
6. The GUI provides a means to set the baud rate, Crystal Switch Closed
E Receive Data Mode Self Train
select the COM port from where data is to be
(RXM)
sent/received and also displays the receive and sent Dividers D1, D2, D3 38.4 kbps
data. If the transmit data is acknowledged, the Transmit Capture select Set
received packet stream will be displayed in the
Received Data list box. Table 3: MSP430 Port Configuration
MSP430 Port PURPOSE DIRECTION
P1.0 to P1.3 Buttons Output
P1.4 to P1.7 LED’s Output
P2.0 RXDATA Input
P2.1 DCLK Input
P2.2 TXDATA Output
P2.3 RX-FLAG Input
P2.4 USART0 TX DATA Output
P2.5 USART0 RX DATA Input
P2.6 LOCKDET Input
P2.7 BROWN-OUT DET Input
P3.0 to P3.3 DIP SWITCH Input
P3.4 LN/HOLD Output
P3.5 STDBY Output
P3.6 CLK Output
Figure 6: Wireless UART GUI to transmit and receive P3.7 MODE Output
P4.0 DATA Output
6. Implementation of Wireless Transmission P4.1 STROBE Output
P6.0 to P6.3 LED’s Output
The firmware details used to implement wireless
transmission is explained in this section. The
firmware has been written using IAR embedded
workbench. The flowchart of the transmission

6.1. Configure Input Output Ports system cost and ultralow-power consumption. The
FLL+ features digital frequency-locked loop (FLL)
The MSP430 ports configured for input and output hardware. The FLL operates together with a digital
are shown in Table 3. modulator and stabilizes the internal digitally
All the ports are configured as general purpose controlled oscillator (DCO) frequency to a
input/output ports except USART0 TXDATA, programmable multiple of the LFXT1 watch
USART0 RXDATA, RXDATA and DCLK. These crystal frequency. The FLL+ clock module can be
pins are configured as peripheral module pins. This is configured under full software control. After a
accomplished using the Function Select Register PUC, MCLK and SMCLK are sourced from
Pxsel. This peripheral module selection configures DCOCLK at 32 times the ACLK frequency. When
RXDATA as Timer A Capture Input and DCLK as a 32,768-Hz crystal is used for ACLK, MCLK, and
Timer B Capture Input. SMCLK stabilizes to 1.048576 MHz. The
SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and
FLL_CTL1 registers configure the FLL+ clock
module. The FLL+ can be configured or
reconfigured by software at any time during
program execution.
In the firmware, the DCO frequency is set to
75 times the watch crystal frequency = 75 x 32,768
= 2.4576 MHz. Thus the MCLK and SMCLK are
sourced by a 2.4576-MHz clock.
6.3. Configure the UART
The ports 2.4 and 2.5 of MSP430 are configured to

transmit and receive data to/from the serial port.
The USART is configured for UART mode by
clearing the SYNC bit in the UCTL0 register. The
character length is chosen to be 8 bits by setting
the CHAR bit in the UCTL0 register. Initially, the
UART is disabled by clearing the SWRST bit
setting in the UCTL0 register. SMCLK is
configured to source the Baud rate Clock BRCLK
by configuring the UTCTL0 register. The UART
baud rate control register UBR00 is set to 64 so
that the baud rate generated is 2.4576 MHz/64 =
Figure 7: Transmit Flowchart 38.4 kbps. Thus, the UART is configured to
operate at 38.4 kbps.
6.2. Configure Baseband clock
6.4. Configure TRF6903
A 32.768-kHz watch crystal is used as a clock
source for MSP430. The watch crystal is connected The firmware routines used to program the
to pins 8 and 9 of the MSP430. The frequency TRF6903 is explained in this section. Depending
locked loop (FLL+) clock module supports low on the transceiver bit rate chosen in the wireless

UART GUI, the clock recovery bit rate dividers interrupt and restarts. The RXDATA signal is
D1, D2, and D3 is chosen to program register E. applied to a capture-compare block.
The transceiver baud rate is set by DR_DLY_CNT, In recognizing the training sequence, the code
a global parameter used across all files in the distinguishes between three different states:
project. The formula used for calculation is: • No valid pulse is detected.
• Fewer than 16 valid consecutive pulses are
Transceiver Bit Rate = 2.4576 detected.
DR DLY CNT + 1 • More than 16 valid consecutive pulses are
detected—the training sequence is recognized.
If the bit rate is 38.4 kbps DR_DLY_CNT =
63; if the bit rate is 19.2 kbps DR_DLY_CNT = 7.2 Detection of Start Bit
127; If bit rate is 51.2 kbps DR_DLY_CNT = 47.
The principle of start-bit recognition is similar to
the detection of the training-sequence pulse except
7. Implementation of Wireless Reception
that the start bit consists of a single pulse. To
distinguish between the pulses of the training
Once the TRF6903 is initialized and configured, it
sequence and the pulse of the start bit, the length of
operates in the receive mode waiting for a training
the start bit was set to three times 26.04 s, i.e.,
sequence. The wireless receive protocol has three
three times as long as the pulses of the training
stages,
sequence. The falling edge of the start-bit pulse is
• Training sequence recognition
the trigger for the scanning and reading of the data
• Start bit recognition
package.
• Data bits recognition
7.3 Detection of Data Bits

7.1. Detection of Training sequence
Data reception is handled using the TRF6903 clock
The MSP430 on the EVK board programs the recovery feature. The field RXM in register E
TRF6903 for reception in learn mode at the determines the clock recovery mode used in
selected frequency. The TRF6903 is then switched TRF6903. If RXM is set to Self Train Mode, the
to active mode. The MSP430 scans the received data clock circuitry provides an output at terminal
signal for a valid data package. Because the band 27 (DCLK) a data clock based on a programmable
always contains noise, the data slicer output bit rate. DCLK is programmed at the configured
necessarily always delivers a digitized signal transceiver bit rate. The received data RXDATA is
component. Another cause for a signal at the data synchronous to the bit rate clock at DCLK. The
slicer output is another application using the same RXDATA transition is timed to coincide with the
frequency band. In any case, the TRF6903 always falling edge of DCLK, thus the rising edge of
delivers a signal to RXDATA when it is active and DCLK is exactly at the center of the RXDATA bit.
in receive mode. The MSP430 must distinguish The MSP430 can then latch RXDATA on the
between valid and invalid signals. The MSP430 rising edge of DCLK.
uses the Timer_A module to make this distinction. In the wireless UART firmware the MSP430
The clock source for Timer_A is MCLK and is is programmed to latch RXDATA on the falling
clocked at 2.4576 MHz. The selected mode is the edge of DCLK rather than the rising edge as
continuous-up mode. In this mode Timer_A counts indicated before. This is recommended for data
continuously from 0 to FFFFh, then generates an rates 30 kbps and higher. This is because the ISR

that services the DCLK trigger has latency of about

6-8 s. This when added to the actual code
execution latency, results in a total latency of about
10 s from the triggering of DCLK to the time
RXDATA value is latched by the MSP430. For
data rates of the order of 38.4 kbps (a pulse width
of 26.04 s), there is about 13.02 s from the
positive edge of DCLK (pulse width center) to the
next data bit. Thus, if the MSP430 is triggered on
the rising edge of DCLK, there is a chance that due
the jitter of the RXDATA signal incorrect bit may
be latched resulting in bit errors. This is illustrated
Figure 9: Actual Project Set-up
by the timing diagram for a 38.4-kbps bit rate
system in Figure 8
transmit data waits until it is full, as the data from
PC comes into it. Once it is full this data is
transferred over the air via TF6903.
In Figure 10, there is a USB cable that
interfaces the EVM via a USB-JTAG converter.
This is used to write the program on the MCU’s
flash memory.
Figure 8: Receive data reception using DCLK
The BLUE arrow (point 1) indicates the time when

the MSP430 is triggered. Due to the latency in the
interrupt servicing and execution, the RXDATA is
actually sampled at point 3 indicated by RED
arrow. This occurs about 10 s after the MSP430 is
triggered.
8. Project Set Up
Figure 10: Block Diagram of Project Set-up
The actual project set-up is shown in Figure 9. A
block diagram of the set-up is depicted in Figure 9. Transmission without encoding/decoding
10. As shown in the figure, the EVM is interfaced
The first step was implementation of a wireless
with the PC via RS-232 cable. This RS-232 cable
link for sending and receiving data. The first step
is used to transmit and receive data to and from the
was to make sure that the RS-232 protocol and the
MSP430. While receiving MSP430 fills a buffer
wireless protocol are implemented appropriately
until all 32 bytes are full. As soon as the overflow
and the data is being transmitted over the link
occurs, the data in the buffer is sent to the PC via
correctly. In order to implement this, the data being
the RS-232 serial interface. The serial port of the
sent from the PC to the transmitter was directly put
PC can be configured used a hyper terminal to read
into the transmit buffer without any modification.
the data received by the MSP430. On the other
At this point the RS-232 protocol was implemented
hand, while transmitting, the buffer used to

to make sure that the data is being accumulated in The ratio k/n is called the code rate of the encoder.
the transmitting buffer. Once the data was It represents the amount of information per coded
successfully exchanged between the PC and the bit. The integer K is called the constraint length of
MCU, the next step was to program the TRF6903 the code. It represents the number of k-tuple stages
to transmit the data as it is, without any encoding in the encoding shift register. An important
decoding. On the receiving side, the data is directly characteristic of convolutional codes, unlike block
stored in the receiving buffer until all 32 bytes are codes, is that the encoder has memory. The n-tuple
received. On arrival of all the 32 bytes, the data is emitted by the convolutional encoding procedure is
then sent via the RS-232 line to the receiving PC. not only a function of an input k-tuple, but is also a
This data is displayed on the GUI or the hyper function of the previous K-1 input k-tuples. In
terminal. practice n and k are small integers and K is varied
For this case the data is transmitted as it is, to control the capability and complexity of the
without any encoding. Measurements of BER were code.
taken for this case and the results were evaluated. The convolutional encoder used in this project
The results are summarized in latter sections. is shown in Figure 11. The figure illustrates a
convolutional encoder with a constraint length of K
10. Transmission using Encoding/Decoding = 3. There are n = 2 modulo-2 adders; thus the
code rate k/n is ½. At each input bit time, a bit is
The encoding scheme used for the project is shifted into the leftmost stage and the bits in the
Convolutional Encoding. The decoding scheme register are shifted one position to the right. Next,
used is Viterbi Decoding. A detailed explanation of the output switch samples the output of each
these schemes and their implementation will be modulo-2 adder (i.e. first the upper adder and then
discussed in this section. the lower adder), thus forming the code symbol
10.1. Convolutional Encoding
Convolutional Encoding is a Forward Error

Correction (FEC) technique used in continuous
one-way and real time communication links. It can
provide substantial improvement in BER so that
small, low power, inexpensive transmitters can be
used in such applications as satellites and hand- Figure 11: Convolutional Encoder
held communication devices. It is a method of
adding redundancy to a data stream in a controlled pair making up the branch word associated with
manner to give the destination the ability to correct the bit that was at the input. The sampling is
bit error without asking the source to retransmit. repeated for each input bit. The choice of
Convolutional codes add reliability to the link connections between the adders and the stages of
while eliminating the need for a reverse channel. register give rise to the characteristics of the code.
They are used in applications where retransmission Any change in the choice of connections results in
of data is impractical or impossible, such as in real a different code. The connections are, of course,
time speech transmissions. not chosen or changed arbitrarily. The problem of
choosing connections to yield good distance
A convolutional encoder is a linear finite state properties is complicated and has not been solved
machine described by three integers n, k and K. in general; however, good codes have been found

by computer search for all constraint lengths less state b=10, c=01 and d=11. At each unit of time
than about 20. the trellis requires 2k-1 nodes to represent the 2k-1
Now consider that input bits, m = 101 is possible encoder states. The trellis in this example
convolutionally encoded with the encoder shown assumes a fixed periodic structure after a trellis
in Figure 11. The three message bits are inputted, depth 3 is reached (at time t4). In the general case,
one at a time, at times t1, t2 and t3. Subsequently, the fixed structure prevails after a depth K is
(K-1) = 2 zeros are inputted at times t4 and t5 to reached. At this point and thereafter, each of the
flush the register and thus ensure that the tail end states can transition to one of the two states. Of the
of the message is shifted the full length of the two outgoing branches, one corresponds to an
register. The output sequence in this case will be input bit zero and the other corresponds to an input
11 10 00 10 11, where the leftmost symbol bit one. In Figure 12, the output branch words
represents the earliest transmission. The entire corresponding to the state transitions appear as
output sequence, including the code symbols as a labels on the trellis branches.
result of flushing, is needed to decode the message. One time-interval section of a fully formed
To flush the message from the encoder requires encoding trellis structure completely defines the
one less zero than the number of stages in the code. The only reason for showing several sections
register or (K-1) flush bits. is for viewing a code-symbol sequence as a
function of time. The state of convolutional
10.1.1. Trellis Diagram encoder is represented by the contents of the right
most (K-1) stages in the encoder register.
The convolution encoding process can be
represented using a diagram called the Trellis 10.1.2 . Implementation of Convolutional Encoding
diagram. This diagram will form the basis for
decoding of the sequence on the receiving side. The packet size of the coded system was 288 bytes
The trellis diagram for a convolutional encoder since the input data bytes per packet was chosen as
with code rate ½ and K=3 is shown in Figure 12. 96 bytes. For the tests, 2000 packets are sent from
the PC to the TRF6903 valuation kit through the
serial port using the RS-232 protocol. The total
number of user data bits sent over the air is 1.536
million. The convolutional encoding algorithm is
designed to work with a data size of 2 bytes. Rate
½ convolutional encoding results in data size of 4
bytes. The encoding also results in 4 flush bits (2
for each byte). The MSP430 registers operate in
Figure 12: Encoder Trellis Diagram (rate= ½, K=3) terms of 2 bytes or a word. Thus 2 additional bytes
are needed to store the flush bits. Encoding
In drawing the trellis diagram, we use the
operation results in generating an output of 6 bytes
convention – a solid line denotes the output
for every 2 bytes input, 2 bytes input => 4 bytes
generated by an input bit zero, and a dashed line
encoded output + 2 bytes flush bits.
denotes the output generated by input bit one. The
The flowchart for implementation of
nodes of the trellis characterize the encoder states;
convolutional encoding is shown in Figure 13. The
the first row nodes correspond to the state a=00,
program first waits for the 96 bytes of the data to
the second and subsequent rows correspond to the
be available. Once the buffer is full, the first two

bytes are taken into consideration. These bytes are of Viterbi decoding is that the complexity of the
convolutionally coded using the XOR function (see Viterbi decoder is not a function of the number of
the Appendix code) and the byte counter is symbols in the codeword sequence. The algorithm
incremented by two in order to keep a track of the involves calculating a measure of similarity, or
number of bytes that have been processed. The distance, between the received signal, at a time ti ,
byte counter is then checked to see if all 96 bytes and all the trellis paths that could not possibly be
are processed. In case all 96 bytes are processed, the candidates for maximum likelihood choice.
the packet counter is incremented and checked When two paths enter the same state then the one
until 2000 packets are transmitted. On the receiver having the best metric is chosen; this path is called
side the same process is carried out for decoding as the surviving path. This selection of surviving
and the BER is evaluated. paths is performed for all states. The decoder
continues in this way to advance deeper into the
trellis, making decisions by eliminating the least
likely paths. The early rejection of the unlikely
paths reduces the decoding complexity.
10.2.1. Decoding using Trellis diagram
In order to understand the decoding process using

the trellis diagram, let us consider an example. In
the decoding process the Hamming distance is used
as a measure of the likelihood of a code
word/symbol. Hamming distance is nothing but the
number of bits by which a code differs from
another. For example if we consider two code
words 00 and 01, then the hamming distance
between them is 1 since only one bit differs when
both are compared. On other hand the code words
00 and 11 will have a hamming distance of 2.
A trellis diagram similar to that shown in
Figure 12 can be used to represent the decoder.
This is shown in Figure 14. The figure shows how
a bit error is corrected using the viterbi decoding
algorithm. An input sequence of 1 1 0 1 1 is being
Figure 13: Flowchart for Convolutional Encoding
considered. On performing convolutional
encoding, the transmitted code word becomes 11
10.2 Viterbi Decoding
01 01 00 01. Assuming that due to channel
characteristics, a bit error is added to the
The Viterbi decoding algorithm was discovered
transmitted sequence and the received sequence is
and analyzed by Viterbi in 1967. The Viterbi
11 01 01 10 01. There is a bit error in the fourth
algorithm essentially performs maximum
code word.
likelihood decoding; however reduces the
Each branch in the decoder trellis diagram has
computational load by taking advantage of the
been labeled with the Hamming distance between
special structure in the code trellis. The advantage

been” received had the branch associated with that

branch been transmitted. In effect, these metrics
describe a correlation-like measure between a
received branch word and each of the candidate
branch words. We continue labeling the decoder
trellis this way as the symbols are received at each
time ti. The decoding algorithm uses these
hamming distance metrics to find the most likely
path through the trellis.
Figure 14: Decoder Trellis Diagram (rate= ½, K=3)
At time t1 the received code symbols are 11.
From the state 00 the only possible transition is to
the received code symbol and the branch word
state 00 or state 10. State 00 00 transition has
corresponding to the same branch from the encoder
branch metric 2; the state 00 10 transition has a
trellis. The branch words seen on the encoder
path metric 0. At t2 there are two possible branches
trellis branches are known a priori to both the
leaving each state. The corresponding metrics of
encoder and the decoder. The encoder branch
these transitions would be 3, 3, 2 and 0 (from top
words are the code symbols that would be expected
to down) as shown in Figure 15, corresponding to
to come from the encoder output as a result of each
of the state transitions. The labels on the decoder
trellis branches are accumulated by the decoder on
the fly i.e. as the code symbols are received; each
branch of the decoder is labeled with a metric of
similarity between the received code symbols and
each of the branch words for that time interval.
From the received sequence, shown in Figure 14,
we see that the code symbols received at time t1 are
11. In order to label the decoder branches at time t1
with the appropriate Hamming distance metric, we
Figure 15: Survivors at t3
look at the trellis of Figure 12 (encoder trellis).
Here we see that a state 00 00 transition yields
the terminating state. At time t3 there are again two
an output branch word of 00. But we received 11.
branches from each state. As a result there are two
Therefore, on the decoder trellis we label the state
paths entering each state at time t4. One path
00 00 transition with hamming distance
entering each state can be eliminated, namely the
between them, namely 2. Looking at the encoder
path having a higher metric. Should the metrics of
trellis again, we see that the state 00 10
two paths be same then one is chosen using an
transition yields an output branch word of 11,
arbitrary rule. At this point in the decoding
which corresponds exactly with the code symbols
process, there is only a single surviving path,
we received at time t1.
termed as the common stem, between the times t1
Therefore on the decoder trellis, we label the
and t2. Therefore the decoder can now decide that
state 00 10 transitions with a Hamming distance
the state transition, which occurred between times
of 0. In summary, the metric entered on a decoder
t1 and t2, was 00 01. Since this transition is
trellis branch represents the difference (distance)
produced by an input bit one, the decoder outputs a
between what was received and what “should have
one as the first decoded bit.

10.2.2. Implementation of Viterbi Decoding contain the identical decoded bit (symbol) ‘x’
branches back in time. That is, with high
Encoding is done in chunks of 2 bytes in order to probability, all surviving sequences at time t stem
perform optimum Viterbi Decoding. The delay in from the same node at t-x. The flowchart for
decoding a longer information sequence is usually Viterbi decoding is shown in Figure 16.
too long for most practical applications. Moreover, The first 6 bytes are processed at a time from
the memory required to store the entire length of the received packet and Viterbi decoding is
surviving sequences is large and expensive. The performed until all 288 bytes are processed. The
solution is to modify the Viterbi algorithm to decoded sequence is stored in a buffer in order to
produce a fixed decoding delay without compare it with the known transmitted sequence
significantly affecting the optimal performance of for determining the BER.
the algorithm. The modification is to retain at any
given time t only the most recent ‘x’ decoded 11. Transmission using Block Interleaving
information bits (symbols) in each surviving
sequence. As each new information bit is received, In case of bit errors, encoding and decoding
a final decision is made on the bit (symbol) schemes implement necessary error correction
received ‘x’ branches back on the trellis, by technique. However, in case there is burst of errors
comparing the metrics in the surviving sequences (like in a fading channel), then the encoding and
decoding schemes do not solve the problem.
Interleaving is implemented in order to distribute a
burst of errors over the bits and appear the error to
look like bit errors rather than a burst of errors. In
other words interleaving transforms these error
bursts into statistically independent errors. On the
receiving side de-interleaving takes place before
decoding the received data.
A simple block interleaver is utilized in this
project. The encoded symbols are written column
by column into a matrix of I rows and J columns.
The number of rows is termed the interleaving
depth and the number of columns is termed the
interleaving span. The channel symbols to be
transmitted are then read row by row, and the
received coded symbols are reordered in the
reverse manner. Thus, two adjacent coded symbols
are separated by (J-1) symbols during transmission.
Since the receiver must wait until it has full matrix
Figure 16: Flowchart for Viterbi decoding before reordering the symbols, interleaving
introduces a transmission delay.
and deciding in favor of the bit in the sequence
having the largest metric. It ‘x’ is chosen 11.1 Implementation of Block Interleaving
sufficiently large, all surviving sequences will
A simple 16X144 (2304 bits) block interleaver is

used to spread the burst errors. The entire coded 12.1. Implementation of BER measurement
packet of 288 bytes (2304 bits) is stores in RAM
and then block interleaved. This operation is The BER measurement was performed by running
illustrated in Figure 17. the program in a loop and comparing the received
data with a known transmitted data. Hyper
Terminal was used to transmit data in a loop for
number of iterations and the size of data was kept 3
times larger than the original data (3X 32 bytes=
96 bytes) in order to have a larger sample size. The
reason to have a large sample size is to determine
the BER of sufficient magnitude.
Figure 17: The 16X144 block interleaver
On the receiving side, each bit is compared
with the known data bits, bit by bit and a counter
The incoming data bits are stored in the matrix
keeps track of the number of error bits. So if there
form with 16 rows and 144 columns. The data bits
are 100 error bits for 2000 iterations of 96 bytes of
are written column by column. Then RF
data (288 bytes of coded data), then the BER
transmission takes place row by row. Thus the
would be 100/ (2000X288X8) = 21.7X10-6. Based
order of transmission of bits for the above
on this a code was written for measuring the BER
arrangement shown in the figure is 1, 17,
for various distances between the transmitter and
33…..2289, 2…etc. It can be seen that the adjacent
the receiver. The results are summarized in the
bits are separated by 144 bits when transmitted.
following section.
Exactly the reverse operation takes place at the de-
interleaver. The received bits are then written row
by row and read column-wise. 13. Results
Extensive measurements were conducted in an

12. Bit Error Rate
apartment complex building. The goals of the
measurement were to obtain a graph of the distance
The Bit Error Rate (BER) may be defined as the
between the transmitter and receiver against the bit
ratio of the number of error bits received over a
error rate. A Hyper Terminal software called
period of time to the total number of bits received
‘Eltima - Advanced Serial Port Software’ was used
over that period of time. It can be written in
to transmit the data bytes. The software had means
equation form as,
to set parameters such as the number of iterations
for which the data should be transmitted, the delay
BER = Number of error bits received over time T
between each iteration and definition of the data
Total number of bits received over time T
itself that has to be transmitted. The number of
iterations was set to 2000 and a data packet of 96
BER is being used in this project as a measure of
bytes was used for transmission. This data was
performance of the system because it is directly
encoded and the encoded data resulted into 288
proportional to the channel characteristics as
bytes. On the receiving side a small code was
channel characteristics are responsible for inducing
written that would compare the received data bit by
errors into a stream of bits transmitted over the
bit with the transmitted data (after decoding and
channel. External noise, interference etc are some
de-interleaving). A counter would keep track of the
of the channel characteristics.
number of bits differing from the original data.

This process was iterated for 2000 times, while the the coded signal and the BER of the coded +
counter maintaining the error bits count was interleaved signal is almost the same for distances
incremented outside this loop. At the end, the between 20m~5m. However, at greater distance we
number of error bits was extracted from the can see that the BER of the coded + interleaved
program. The measurements were made for an un- data is better than the BER of the coded data alone.
coded system, coded system and for coded + The reason for this is that at greater distance the
interleaved system. fading effects of the channel are more, hence
The BER values attained during the test affecting the S/N ratio of the system by a greater
measurement are shown in Table 4. factor, and hence increasing error bursts.
Therefore, with these results it can be clearly stated
Table 4: BER values at various distances for that communication scheme such as
different schemes encoding/decoding improve the BER by forward
Distance Un-coded Coded Coded +
error correction, when compared to the un-coded
(m) Interleaved
25 142.8X10-3 125X10-3 72.5X10-3 system where the BER is high. However,
-3 -3
20 50X10 21.7X10 11.1X10-3 interleaving technique adds more robustness to bit
-3 -3
15 12.5X10 4.5X10 1.72X10-3 errors by distributing the burst of errors as
-3 -3
10 5X10 1.08X10 1.15X10-3 statistically independent errors.
-3 -3
5 10 0.2X10 0.11X10-3
The BER vs. Distance plot is shown in Figure 18. 14. Conclusion
The nature of the various curves is as expected and
can be explained. The plot was generated using A wireless communication system for indoor
MATLAB program. The BER values have been channel was successfully implemented along with
plotted on a logarithmic scale in order to see the various schemes such as convolutional encoding,
change in BER more clearly. viterbi decoding and block interleaving. Successful
measurements of BER were made for different
schemes and the performance of the system was
evaluated. A good understanding of protocols such
as RS-232 and wireless protocol was achieved. The
project served as means to explore and learn
programming techniques for a wireless system
using a transceiver and a microcontroller.
During the course of project a lot of
amendments were made to the original proposed
plan, in order to consider practical situations. One
example was using distance as a measure for S/N
ratio due to lack of means to measure the S/N of
the received signal and due to its complexity.
However, the results obtained were very consistent
Figure 18: BER (vs.) Distance Plot with the theoretical counterparts and helped in
understanding the behavior of a practical wireless
From the plot it is clear that the BER for the un- system.
coded data would be the maximum, hence making
the system prone to higher error rate. The BER for

15. References
[1] Andrew H. Snelgrove, The Design of a

Programmable Convolutional Encoder using
VHDL and FPGA, Thesis Report – Naval
Postgraduate School, Monterey, California,
December 1994.
[2] Xun Liu, Marios C. Papaefthymiou, Design of

a High-Throughput Low Power IS95 Viterbi
Decoder, Advanced Computer Architecture
Laboratory, Dept. of Electrical Engineering and
Computer Science, University of Michigan, Ann
Arbor, Michigan, June 2002.
[3] Harsha Rao, Implementing a Bidirectional

Wireless UART Application with TRF6903,
Application Note, Digital Radio RF Applications,
Texas Instruments, September 2004.
[4] User Guide: TRF6903 with MSP430 –

Demonstration and Development Evaluation Kit
[5] User Guide: MSP430x4xx Family – Texas

Instruments.
[6] Data Sheet: MSP430x4xx Family – Texas

Instruments
[7] Data Sheet: TRF6903 Transceiver – Texas

Instruments

APPENDIX
Some parts of the code were provided by Texas Instruments
;*******************************************************************************************************
;;
; This code supports the transmition and reception of 32 data bytes and 2 checksum bytes.
; It supports an acknowledge.
; The data transmission rate is 38.4 kbit/s on the RF side
; The data transmission rate at the RS232 port is 19.2 kbit/s
;
; Written by: Ashutosh Jaiswal
; St. Mary's University, San Antonio
; Master Degree Project
; ;*******************************************************************************************************
#include "MSP430X14X.H"
RAM_orig EQU 00200h ; RAM start

FLASH_orig EQU 0F000h ; F1121 FLASH start
NAME TRF6903_EVK
RSEG CODE ; beginning of the code

START
;*********************************** main **************************************************************

; Calls all the subroutines
; Is the frame for the whole program
;*******************************************************************************************************
main
MOV #0300h,SP ; initialize system stack pointer
;;;;;;;;;;;;;;;;;;;;;;;
MOV #5468h,&0x0220
MOV #6973h,&0x021E
MOV #2069h,&0x021C
MOV #7320h,&0x021A
MOV #7465h,&0x0218
MOV #7374h,&0x0216
MOV #696Eh,&0x0214
MOV #6720h,&0x0212
MOV #6174h,&0x0210
MOV #2066h,&0x020E
MOV #756Ch,&0x020C
MOV #6C20h,&0x020A
MOV #7377h,&0x0208
MOV #696Eh,&0x0206
MOV #6720h,&0x0204
MOV #2020h,&0x0202
CALL #encode ; initialization of the TRF6900 and
DINT ; general Interrupt disable

MOV #WDTPW+WDTHOLD,&WDTCTL ; write with password 5A00h, WDT off
CALL #initialization ; initialization of the TRF6900 and
; MSP430 settings
loop_main

CALL #receive_RF ; receive 10x8bits

BIC #TAIE,&TACTL ; disable Timer_A interrupt
BIC #CCIE,&CCTL1 ; disable CCR1 interrupt
CLR counter ; set counter value to 0
CALL #rs232_send ; transmits the received data via RS232 Port
BIC #CCIFG,&CCTL1 ; reset interrupt flag
BIC #TAIFG,&TACTL ; reset interrupt flag
BIS #TAIE,&TACTL ; enable interrupt
BIS #CCIE,&CCTL1 ; enable interrupt
reset_wdt
JMP loop_main ; end of the main routine
end_main
;********************************* Intialization *******************************************************

; affects: clock settings
; intializes the hardware
; clearing oscillator fault flag !!! necessary for MSP430
;*******************************************************************************************************
initialization
;****************************** Clock Settings *********************************************************

; 1. LFXT1CLK-signal is driven by the external 2.4576Mhz crystal
; 2. ACLK is 1/8*LFXT1CLK
; 3. MCLK directly coupled to LFXT1CLK (used only for the CPU)
; 4. SMCLK directly coupled to LFXT1CLK (used for timer_A during code reception)
;*******************************************************************************************************
test
; BIS #OSCOFF, SR ; turn off

initialize_clock
MOV.B #0C0h,&BCSCTL1 ; ACLK/1
; high frequency oscillator selected

; oscillator on
MOV #000Fh,wait_r ; for programming purpose
; MSP430P112
CALL #wait_x_cycles ; wait routine, waits 3+x*13 cycles
;BIC #OSCOFF, SR ; turn on
MOV #0FFFh,wait_r ; for programming purpose

; MSP430P112
CALL #wait_x_cycles ; wait routine, waits 3+x*13 cycles
initialize_port1
MOV.B #txd,&P1OUT ; set TXD_MSP(P1.1), TXD_MSP by default high
; reset TXDATA(P1.4), DATA(P1.7), CLK(P1.6),
; STROBE(P1.5)
MOV.B #stdb_rs232+data+clk+tx+txd,&P1DIR ; switch DATA(P1.7), CLK(P1.6),
; TXDATA(P1.4), TXD(P1.1) and stdb_rs232(P1.0)
; to output dir.
MOV.B #rx+rxd,&P1SEL ; select the module function for P1.3 (TA2),
; RXD P1.2 (TA1)
initialize_port2
MOV.B #LED3,&P2OUT ; reset P2.0,CTS (-> CTS set!),
; STANDBY_TRF6903(P2.5), MODE(P2.1) ->
; receive, set LED3(P2.3), System Mode
MOV.B #stdb_trf6903+mode+cts+LED3,&P2DIR ; switch STANDBY_TRF6903(P2.5), MODE(P2.1),
; CTS(P2.0) to output, LOCKDET(P2.4) input
initialize_receive_status
CLR &data_rx_state ; reset receive status
oscillator_flag
BIC.B #02h,&IFG1 ; reset the oscillator fault flag
MOV #0Fh,wait_r ; wait 3 + Fx13 cycles
CALL #wait_x_cycles ; call the wait routine

BIT.B #02h,&IFG1 ; test the oscillator fault flag

JNZ oscillator_flag
BIC.B #02h,&IFG1 ; clear oscillator fault flag
initialize_Clock
BIS #SCG1,SR
MOV.B #0C8h,&BCSCTL2 ; SELS = 1 LFXT1CLK source for SMCLK
;-------------------------------------------------------------------------------------------------------
; programming the 4 words to TRF6903
CALL #program_DDS0_receive_learn
CALL #program_DDS1_send
CALL #program_send_FSK
CALL #program_receive_FSK_learn
initialize_CCR1_interrupt
MOV #CCIE+CAP+CMNEG,&CCTL1 ; interrupt enable, capture mode, neg. edge

; for RS232 reception
end_intialization
RET
;**************************** Programming the TRF6903 **************************************************
;******************************* program_DDS0_receive_learn ********************************************

; purpose: programs the DDS_0 for FSK Reception in learn mode (see further settings below)
; (Mode 0, A-word), changed settings for the US ISM band !!!
;
;*******************************************************************************************************
program_DDS0_receive_learn
MOV #023h,word_h
MOV #05029h,word_l ; frequency for Mode 0, receive FSK in learn
; mode, DDS_0 settings for 904.3MHz,
; 25.6MHz system crystal, 10.7MHz IF
CALL #program_TRF6903
end_program_DDS0_receive_learn
RET
;******************************* program_DDS1_send *****************************************************

; ; purpose: programs the DDS_1 for Transmision (see further settings below)
; (Mode 1, B-word), changed settings for the US ISM band !!!
;
;*******************************************************************************************************
program_DDS1_send
MOV #063h,word_h
MOV #0BB21h,word_l ; frequency for Mode 1, send
; DDS_1 settings for 915MHz,
; 25.6MHz system crystal, 10.7MHz IF
end_program_DDS1_send
RET
;******************************* program_send_FSK ******************************************************

; ; purpose: programs the module Mode 1 for FSK transmission (see further settings below)
; (Enable register for PLL, Data Slicer and Mode 1 settings, C-word)
;
;*******************************************************************************************************
program_send_FSK
MOV #0BCh,word_h
MOV #09E00h,word_l ; Module Mode 1, send
; 1_LNAM [bit 0..1] 00b disabled Low noise amplifier operation mode
; 1_MIX [bit 2] 0b disabled Enable Mixer
; 1_IF [bit 3] 0b disabled Enable 1st IF Amplifier
; 1_DEM [bit 4] 0b disabled Enable Limiter/Demodulator

; 1_RSSI [bit 5] 0b disabled Enable Limiter/RSSI

; 1_DSW [bit 6] 0b conn. to Demod. Data Switch (Demodulator or RSSI)
; 1_LPF [bit 7] 0b disabled Enable LPF Amplifier
; 1_SLC [bit 8] 0b disabled Enable Data Slicer
; 1_PA [bit 9..10] 11b 0dB att. Power Amplifier gain value in TX mode
; (see also MS bit)
; 1_VCO [bit 11] 1b enabled Enable VCO
; 1_PLL [bit 12] 1b enabled Enable PLL ( DDS System, RF divider,
; Phase Comparator and Chargepump)
; [bit 13..14] 00b not used
; SLCTL [bit 15] 1b learning mode Slicer mode select bit
; MS [bit 16] 0b FSK modulation mode select
; NPLL [bit 17] 0b 256 RF divider ratio for PLL
; APLL [bit 18..20] 111b 140 acceleration factor for the charge pump
end_program_send_FSK
RET
;******************************* program_receive_FSK_learn *********************************************

; purpose: programs the module Mode 0 for FSK reception in learn mode (see further settings below)
; (modulation and mode 0 settings, D-word)
;
;*******************************************************************************************************
program_receive_FSK_learn
; MOV #0C6h,word_h
; MOV #0D99Fh,word_l ; Modulation, Module Mode 0, receive
MOV #0C7h,word_h
MOV #0199Fh,word_l ; Modulation, Module Mode 0, receive
; 0_LNAM [bit 0..1] 11b normal Low noise amplifier operation mode
; operation
; 0_MIX [bit 2] 1b enabled Enable Mixer
; 0_IF [bit 3] 1b enabled Enable 1st IF Amplifier
; 0_DEM [bit 4] 1b enabled Enable Limiter/Demodulator
; 0_DSW [bit 6] 0b con. to Dem. LPF Amplifier input routed to Demodulator
; (FSK) or to RSSI (OOK)
; 0_LPF [bit 7] 1b enabled Enable LPF Amplifier
; 0_SLC [bit 8] 1b enabled Enable Data Slicer
; 0_PA [bit 9..10] 00b disabled Power Amplifier gain value in TX mode (see
; also MS bit)
; 0_PLL [bit 12] 1b enabled Enable PLL (DDS System, RF divider, Phase
; comparator and Chargepump)
; MR [bit 13..20] 0010 0110b FSK frequency deviation register (corresponds with
; 60kHz modulation)
end_program_receive_FSK_learn
RET
;******************************* program_receive_FSK_hold **********************************************

; purpose: programs the module Mode 1 for FSK reception in hold mode (see further settings below)
; (enable register for PLL, Data Slicer and Mode 1 settings, C-word)
;
;*******************************************************************************************************
program_receive_FSK_hold
MOV #0BCh,word_h
MOV #01E00h,word_l ; Modulation, Module Mode 1, receive
; 1_LNAM [bit 0..1] 00b disabled Low noise amplifier operation mode
; 1_MIX [bit 2] 0b disabled Enable Mixer
; 1_IF [bit 3] 0b disabled Enable 1st IF Amplifier
; 1_DEM [bit 4] 0b disabled Enable Limiter/Demodulator


; 1_DSW [bit 6] 0b conn. to Demod. Data Switch (Demodulator or RSSI)
; 1_LPF [bit 7] 0b disabled Enable LPF Amplifier
; 1_SLC [bit 8] 0b disabled Enable Data Slicer
; 1_PA [bit 9..10] 11b 0dB att. Power Amplifier gain value in TX mode
; (see also MS bit)
; 1_PLL [bit 12] 1b enabled Enable PLL ( DDS System, RF divider,
; Phase Comparator and Chargepump)
; [bit 13..14] 00b not used
; SLCTL [bit 15] 0b hold mode Slicer mode select bit
; MS [bit 16] 0b FSK modulation mode select
; NPLL [bit 17] 0b 256 RF divider ratio for PLL
; APLL [bit 18..20] 111b 140 acceleration factor for the charge pump
end_program_receive_FSK_hold
RET
;**************************** program_TRF6903 **********************************************************

; purpose:
; programs a word to A, B, C or D word register of the TRF6903
; gets the settings from the calling routine in R6 and R7
; suppresses the strobe pulse in receive_RF routine, to support shorter trainings sequence
;
;*******************************************************************************************************
program_TRF6903
init_high_byte
DINT
BIC.B #strobe,&P1OUT ; reset Strobe port
BIS.B #strobe,&P1DIR ; switch Strobe to output direction
MOV #02h,counter ; initialize the counter for high and low byte
MOV #08h,bits_r ; initialize bitcounter
MOV word_h,word_trf ; push the high byte to the programming buffer
SWPB word_trf ; push the low byte to the high byte, only the
; data in the low byte is relevant
JMP program_word
init_low_byte
MOV #010h,bits_r ; initialize bitcounter
MOV word_l,word_trf ; push the low byte to the programming buffer
program_word
RLC word_trf ; push the msb of the programming buffer to carry
JNC program_low
program_high
BIS.B #data,&P1OUT ; set data(P1.7)
program_clock
BIS.B #clk,&P1OUT ; generate a pulse on the clock line
BIC.B #clk,&P1OUT
program_next_bit
DEC bits_r ; decrement bit counter
JNZ program_word ; have already all bits been sent?
DEC counter ; decrement counter for low byte recognition
JNZ init_low_byte ; low byte is to be programmed
generate_strobe
BIC.B #data,&P1OUT ; reset data (P1.7)
BIT #08h,&data_rx_state ; shall the strobe pulse be suppressed?
JNZ end_program_TRF6903 ; yes suppress it
BIS.B #strobe,&P1OUT ; set strobe(P1.5)
BIC.B #strobe,&P1OUT ; clear strobe(P1.5)
BIC.B #strobe,&P1DIR ; set strobe(P1.5) to input direction

end_program_TRF6903
EINT
RET ; back to calling routine
program_low
BIC.B #data,&P1OUT ; clear data(P1.7)
JMP program_clock
;*********************************** send_RF ***********************************************************

; purpose: sends the received 40 bytes package from RS232 via RF as NRZ code, without receiving an
; acknowledge
; features a shorter training sequence
; counter value comes from the calling routine
;
;*******************************************************************************************************
send_RF
send_RF_init
DINT
BIS.B #stdb_rs232,&P1OUT ; RS232 driver in standby mode

BIC.B #rxd,&P1IE ; disable P1.2 Interrupt
BIS.B #stdb_trf6903,&P2OUT ; TRF6903 active, STANDBY(P2.5) is high
BIS.B #mode,&P2OUT ; Mode 1 is set -> Send mode
BIC.B #tx,&P1OUT ; TXDATA(P1.4) is reset
CALL #wait_lockdet ; wait for the lockdetect signal
MOV #WDTPW+WDTHOLD,&WDTCTL ; Password, Watchdog Timer hold
MOV 02FEh(counter),data_r ; push data to the send register
MOV.B #0C0h,&BCSCTL1 ; ACLK/1
MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 26,04µsec
BIS.B #01h,&IE1 ; enable Watchdog Timer interrupt
EINT
send_RF_training_sequence ; the entire length ca. 4ms, 154 pulses

; MOV #03Ch,tr_counter ; 1.56ms, 60 pulses
MOV #026h,tr_counter ; 1ms, 38 pulses
; MOV #09Ah,tr_counter ; initialize the training sequence counter
send_RF_toggle
BIS #CPUOFF+GIE,SR ; CPU off

;------------------ Start of the training sequence ----------------------------------------------------
XOR.B #tx,&P1OUT ; toggle TXDATA(P1.4)
DEC tr_counter ; decrement counter for the training sequence
JNZ send_RF_toggle ; length of the loop exactly 26,04µsec
send_RF_long_bit
;------------------ Start of the start bit -------------------------------------------------------------
BIS.B #tx,&P1OUT ; start of the long start-bit 78,12µsec
; (end by the transmission of the 1st data bit)
BIC #04h,&data_rx_state ; the RS232 buffer is ready for reception
;----------------- End of the start bit ----------------------------------------------------------------
BIC.B #tx,&P1OUT ; reset TXDATA(P1.4)
send_RF_data
MOV #010h,bits_r ; init bitcounter, transmit first 16 bits
send_RF_bit_test
RLC data_r ; push the next data bit to carry
JC send_RF_high

send_RF_low
;-------------------------------- Start of the Databit -------------------------------------------------
BIC.B #tx,&P1OUT ; reset TXDATA(P1.4)
send_RF_next_word?
JNZ send_RF_bit_test
DECD counter ; decrement word counter
JZ send_RF_LED3_on ; all data has been transmitted
JN send_RF_reset_ackn ; acknowledge has been transmitted
MOV 02FEh(counter),data_r ; get the next data word
JMP send_RF_data ; send next word
send_RF_high
;-------------------------------- Start of the Databit -------------------------------------------------
BIS.B #tx,&P1OUT ; set TXDATA(P1.4)
JMP send_RF_next_word?
send_RF_reset_ackn
BIC #020h,&data_rx_state ; reset acknoledge state
send_RF_LED3_on
BIS.B #LED3,&P2OUT ; LED3 on
end_send_RF
MOV #WDTPW+WDTHOLD,&WDTCTL ; stop Watchdog Timer
BIC.B #stdb_rs232,&P1OUT ; RS232 driver go active
BIC.B #tx,&P1OUT
BIC.B #stdb_trf6903,&P2OUT ; clear STDBY(P2.5), TRF6903 standby mode
; BIC.B #rxd,&P1IFG ; reset the interrupt flag
; BIS.B #rxd,&P1IE ; enable P1.2 Interrupt
RET
;********************************* receive_RF **********************************************************

; main routine for code reception
;
; purpose: receives the 20 bytes data package and saves it to memory
; the reception is also supported by several interrupt routines
; checksum checking implemented (for Flash reprogramming)
;
;*******************************************************************************************************
receive_RF
BIT #02h,&data_rx_state ; is the reception buffer full?
JNZ end_receive_RF ; yes the data has to be send to desktop first
CALL #program_send_FSK ; program the C-word for reception in
; learn mode
MOV #CCIE+CAP+CMNEG,&CCTL1 ; interrupt enable, capture mode, neg. edge
CLR data_r ; reset data_r
CLR wake_up_counter ; reset wake_up_counter
CLR RSTAT ; reset receive status register, RSTAT = 0,
CLR res_old_r ; detecting the Trainingssequence
BIC.B #mode,&P2OUT ; receive FSK in learn mode
BIS.B #stdb_trf6903,&P2OUT ; TRF6903 active, STANDBY(P2.5) is high
CALL #wait_lockdet
MOV.B #0C0h,&BCSCTL1
MOV #TAIE+CLEAR+CONTUP+TASSEL_1,&TACTL ; interrupt enable, clear Timer_A,
; continuous up mode, ACLK as clock source
MOV #CCIE+CAP+CMANY,&CCTL2
BIS #08h,&data_rx_state ; changed from BIS for suppressing strobe pulse at the end
; of the programming routine
BIS.B #LED3,&P2OUT ; switch on the system mode LED

CALL #program_receive_FSK_hold ; goto hold mode

BIC #08h,&data_rx_state ; reset the the "suppressing mode"
BIC.B #data,&P1OUT ; reset data 1919
loop_receive_training_seq
;--------------------- scanning the received signal for the training sequence --------------------------
CMP #08h,wake_up_counter ; 8 equal pulses in succession
JL loop_receive_training_seq ; no the result is less than 8 equal pulses
; in a row
BIC #022h,&TACTL ; stop Timer_A and disable interrupt
BIC #CCIE,&CCTL2 ; disable interrupt
INCD RSTAT ; RSTAT = 4
start_bit_reception ; waiting for the start_bit

BIS.B #strobe,&P1OUT ; set strobe(P1.5)
BIC.B #strobe,&P1OUT ; clear strobe(P1.5)
;MOV #0106h,&TACTL
;BIS #20h,&TACTL
MOV #TAIE+CLEAR+CONTUP+TASSEL_1,&TACTL ; interrupt enable, clear Timer_A, continious
; up mode, MCLK as clock source
;MOV #TAIE+CLEAR+CONTUP+MCLK,&TACTL ; interrupt enable, clear Timer_A,
; continuous up mode, MCLK as clock source
MOV #CCIE+CAP+CMANY,&CCTL2 ; interrupt enable, capture mode, both edges
loop_start_bit
CMP #04h,RSTAT ; has the start bit been detected?
JEQ loop_start_bit ; wait for the start bit
JN receive_RF ; the received sequence is invalid
BIC.B #rxd,&P1IE ; disable P1.2 interrupt
;----------------------------- start bit detected ------------------------------------------------------
init_data_reception ; RSTAT = 6, Start Bit detected, Data Reception

NOP ; insert for the right timing
NOP
MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 26µs
MOV #042h,counter ; Initialize counter
init_rx_bit_counter
CLR bits_r ; Reset bitcounter
word_reception_loop
BIS #CPUOFF+GIE,SR ; go to sleep!
; wake up from WDT (Timer Mode, every 26µs)
; NOP ; insert for timing
; NOP ;
; NOP ;
; NOP ;
; NOP ;
; NOP
; NOP
; NOP
; XOR.B #LED3,&P2OUT ; for test purpose
BIT.B #08h,&P1IN ; is RXDATA high or low?
read_data
RLC data_r ; push carry into the data register
INC bits_r
CMP #010h,bits_r ; receive 16 bits in row
JNE word_reception_loop ; haven't received 8bits yet
store_data
INV data_r ; the received data is inverted!
MOV data_r,02FEh(counter) ; store received data to RAM
DECD counter ; next storage register
JNZ init_rx_bit_counter ; receive the next word
BIC.B #LED3,&P2OUT ; system LED off for test purpose
BIS #02h,&data_rx_state ; 2 stands for data received,
; has to be send to desktop via RS232
BIS #020h,&data_rx_state ; initialize the acknowledge state

end_receive_RF
;CALL #checksum_r ; built checksum of received data
CALL #decode
BIC.B #stdb_trf6903,&P2OUT ; clear STDBY(P2.5), TRF6903 in standby mode
RET
;************************************ rs232_send *******************************************************

; purpose: the transmission of the received data from TRF6903 to the PC via RS232-Port
;
;*******************************************************************************************************
rs232_send
BIT #02h,&data_rx_state ; is there any data in the reception buffer,
; which hasn't been sent to the desktop?
JZ end_rs232_send ; no the reception buffer is empty
BIC.B #cts,&P2OUT ; reset CTS !!!!
BIC.B #stdb_rs232,&P1OUT ; activate RS232 driver
MOV #032Eh,wait_r ; initialize wait register for ca. 1ms
; waiting loop
CALL #wait_x_cycles ; wait for RS232 driver ready to transmit
MOV.B #0D0h,&BCSCTL1 ; set the divider for ACLK to 2,
; high frequency oscillator
MOV #020h,counter ; Initialize counter

MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 52.08µs
EINT ; general Interrupt enable
rs232_send_init
MOV.B 0223h(counter),data_r ; move the first received word into the output
; buffer
MOV #0Ah,bits_r ; send only 8bit in a row
BIS #0100h,data_r ; prepare stop bit
CLRC ; set carry, prepare startbit
RLC data_r ; prepare the output buffer for data
; transmission
rs232_send_loop
RRC data_r ; push next bit to carry for transmission
JNC rs232_send_low
rs232_send_high
BIS.B #txd,&P1OUT ; set TXD
DEC bits_r ; decrement bitcounter
JNZ rs232_send_loop
rs232_send_next_byte
DEC counter ; decrement byte counter
JNZ rs232_send_init ; get the next byte for transmission
BIC #02h,&data_rx_state ; the buffer is ready to receive from TRF6903
; the next data
JMP end_rs232_send_lp ;
rs232_send_low
BIC.B #txd,&P1OUT ; reset TXD
DEC bits_r ; decrement bitcounter
JNZ rs232_send_loop
JMP rs232_send_next_byte
end_rs232_send_lp ; generate the last change of the TXD

BIS.B #txd,&P1OUT ; TXD by default high, data toggles the TXD
end_rs232_send

DINT ;
BIS.B #LED3,&P2OUT ; set System LED for test purpose
RET
;************************************ checksum_s *******************************************************

; used to built the checksum of the received data package from RS232, for secure data transmission
; (Flash reprogramming via RF)
;
;*******************************************************************************************************
checksum_s
MOV #020h,counter ; initialize counter
CLR chcksum_s ; reset checksum
checksum_s_loop
ADD 0200h(counter),chcksum_s ; build checksum over all data to send
DECD counter
JNZ checksum_s_loop
MOV chcksum_s,&0222h ; save checksum
end_checksum_s
RET
;************************************ checksum_r *******************************************************

; used to built the checksum of the received data package from RF, for secure data transmission
; (Flash reprogramming via RF)
;
;*******************************************************************************************************
checksum_r
BIT #040h,&data_rx_state ; expecting acknowledge?
JNZ end_checksum_r ; no need to built the checksum
MOV #020h,counter ; initialize counter
CLR chcksum_r ; reset checksum
checksum_r_loop
ADD 0222h(counter),chcksum_r ; build checksum over all data to send
DECD counter
JNZ checksum_r_loop
MOV chcksum_r,&0200h ; save checksum
end_checksum_r
RET
;************************************ check_chcksm_s ***************************************************

; purpose: compares the received checksum from the receiver, with the checksum of the received data
; from the PC via RS232
;
;*******************************************************************************************************
check_chcksm_s ; renamed
BIT #040h,&data_rx_state ; check if waiting for an acknowledge
JZ end_check_chcksm_s ;
CMP &0222h,&0244h ; compare the both checksums
JNE end_check_chcksm_s ; no the received data isn't valid
check_chcksm_s_ok ; renamed
MOV #06F6Bh,&0242h ; move "ok" to the first word
MOV #06F6Bh,&0240h ; test
MOV #06F6Bh,&023Eh ; test
MOV #06F6Bh,&023Ch ; test
MOV #06F6Bh,&023Ah ; test
MOV #06F6Bh,&0238h
MOV #06F6Bh,&0236h
MOV #06F6Bh,&0234h
MOV #06F6Bh,&0232h
MOV #06F6Bh,&0230h
MOV #06F6Bh,&022Eh
MOV #06F6Bh,&022Ch
MOV #06F6Bh,&022Ah

MOV #06F6Bh,&0228h
MOV #06F6Bh,&0226h
MOV #06F6Bh,&0224h
BIS #02h,&data_rx_state ; set the data package received state

CALL #rs232_send ; send the "ok" to the PC
BIC #040h,&data_rx_state ; reset the state "waiting for acknowledge"
BIC #020h,&data_rx_state ; reset the state "acknowledge to send"
BIC #02h,&data_rx_state ; reset the state "data_package_received"
end_check_chcksm_s ; renamed
RET
;********************************** check_chcksm_r *****************************************************

; purpose: - Compares the received checksum, that was built by the sender of the received data
; package via RS232, with the checksum built on the receiver side of the received data
; package.
; - If the two checksums are equal, the received data package is send of via RS232, and the
; checksum is send as an acknowledge back to the sender.
; - IF the checksums aren't equal the package is not send via RS232 to the PC, and no
; acknowledge will be send to the sender.
;*******************************************************************************************************
check_chcksm_r
BIT #040h,&data_rx_state ; check if waiting for an acknowledge
JNZ end_check_chcksm_r
BIT #02h,&data_rx_state ; is there any data in the reception buffer,
; which hasn't been sent to the desktop?
JZ end_check_chcksm_r ; no, no new data package
CMP &0200h,&0244h ; are the checksums equal?
JEQ end_check_chcksm_r ; yes the data is valid
check_chcksm_r_inv
BIC #02h,&data_rx_state ; reset the data package received state
BIC #020h,&data_rx_state ; reset the acknowledge to send state
end_check_chcksm_r
RET
;************************************ wait loops *******************************************************

; used for various timings, e.g. NRZ reception and transmission
;
;*******************************************************************************************************
wait_x_cycles ; waits 13 + x times 3 cycles

DEC wait_r
JNZ wait_x_cycles
RET
end_wait_x_cycles
;************************************ wait for lockdetect **********************************************

; wait routine for the Lockdetect signal
;
;*******************************************************************************************************
wait_lockdet
BIT.B #lockdet,&P2IN ; is the LOCKDET(P2.4) set?
JZ wait_lockdet ; not yet
end_wait_lockdet
RET
;************************************** Timer_A Interrupt routine **************************************

; used by CC1_INT/RS232 reception and receive_RF
;*******************************************************************************************************
TA_INT
ADD &TAIV,PC
RETI

JMP CC1_INT ; RS232 reception -> falling edge of the

; startbit
JMP CC2_INT ; RF reception -> every edge of
; the rx-signal
RETI
RETI
RETI
;****************************** Capture Compare 1 Register *********************************************

;
; used for RS232-Reception
;
;*******************************************************************************************************
CC1_INT
BIT #04h,&data_rx_state ; is the RS232 buffer full?

JNZ end_CC1_INT ; yes, do not receive further data
MOV #08h,bits_r ; init bit counter
MOV #020h,counter ; init byte counter
BIC #CCIE,&CCTL2 ; disable interrupt
EINT
rs232_init_WDT
; MOV.B #clock_neu_3,&BCSCTL2 ; set the divider for ACLK to 2,
; high frequency oscillator
MOV.B #0D0h,&BCSCTL1
MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; Reset, Timer Mode, Password, every 52.08µs
rs232_rec_data
BIC.B #LED3,&P2OUT ; LED3 off
BIT.B #rxd,&P1IN ; is the rx line high, or low?
rs232_push_buffer
RRC data_r ; push carry to reception buffer
JNZ rs232_rec_data ; read the next bit
rs232_stop_bit
BIS #04h,&data_rx_state ; set the data reception state to received!
MOV #WDTPW+WDTHOLD,&WDTCTL ; stop watchdog timer
rs232_start_bit ; waits for the next start bit

BIT.B #rxd,&P1IN ; wait for the falling edge of the
; start bit for synchronization
JNZ rs232_start_bit
MOV #08h,wait_r ; init wait parameter
CALL #wait_x_cycles
MOV #WDTPW+WDTTMSEL+WDTCNTCL+07h,&WDTCTL ; 10h for aclk
MOV #08h,bits_r ; init bit counter
SWPB data_r ; swap high and low byte of the receive buffer
MOV.B data_r,0201h(counter) ; store the received data to RAM
; for RF-Transmission
DEC counter ; decrement the byte counter
JNZ rs232_rec_data ; get the next byte
end_CC1_INT
MOV #WDTPW+WDTHOLD,&WDTCTL ; stop watchdog timer
BIS #040h,&data_rx_state ; set the status on waiting for acknowledge
;CALL #checksum_s ; built checksum over received data

CALL #encode
MOV #042h,counter ; init counter
PUSH R7 ; STORE THE VALUE OF R7
MOV #400h,R7
;MODIFICATION TO SEND 128 BYTES 1024 TIMES

keep_sending
CALL #send_RF ; send the received data out
;BIS #04h,&data_rx_state ; the RS232 buffer is ready for reception
MOV #108h,counter ; init counter
MOV #0FFFFh,wait_r
CALL #wait_x_cycles
MOV #0FFFFh,wait_r
CALL #wait_x_cycles
MOV #0FFFFh,wait_r
CALL #wait_x_cycles
; MOV #0FFFFh,wait_r
; CALL #wait_x_cycles
DEC R7
JNZ keep_sending
POP R7
BIC #CPUOFF+GIE,0(SP) ; wake up from sleep mode

MOV #receive_RF,2(SP) ; do not return to the original address
; before the interrupt request, but start
; at the beginning of the receive_RF
; subroutine
RETI
;****************************** Capture Compare 2 Register *********************************************

;
; used for RF-Reception
;
;*******************************************************************************************************
CC2_INT
;MOV.B #0F0h,&BCSCTL1 ;ACLK/8
MOV.B #0C0h,&BCSCTL1 ;ACLK/1
MOV #WDTPW+07h+WDTCNTCL+WDTTMSEL,&WDTCTL ; ACLK, ca.106ms, Timer Mode, Reset
; MOV #WDTPW+WDT26MS+WDTCNTCL+WDTTMSEL,&WDTCTL ; ACLK, ca.106ms, Timer Mode, Reset
MOV RRFTAB(RSTAT),PC ; conditional jump depends on RSTAT
; RSTAT = 0, detecting the Trainingsequence
; RSTAT = 1, Trainingsquence detected, waiting
; for the Start Bit
; RSTAT = 2, Start Bit detected, Data Reception
RRFTAB DW RSTAT00
DW RSTAT01
DW RSTAT10
RSTAT00
MOV &CCR2,res_new_r ; save Reference Capture value
MOV res_new_r,res_r ; copy Timer_A value
SUB res_old_r,res_r ; subtract the current Timer_A value from the
; old one -> Bitwidth in cycles in res_r
MOV res_new_r,res_old_r ; current value now -> old value later
test_res_r00
SUB #038h,res_r ; subtract the average value from the
; measured value
CMP #010h,res_r ; is the detected signal 51-63 cycles long?
JHS no_valid_pulse
INCD RSTAT ; first valid pulse detected
INC wake_up_counter ; count this valid pulse
BIC #CPUOFF,0(SP) ; wake up!
RETI
no_valid_pulse
CLR RSTAT ; no the signal doesn't fit the wakeup sequence
CLR wake_up_counter ; reset the wake_up_counter, received an
; invalid pulse
;BIC #CPUOFF,0(SP) ; wake up!

RETI
RSTAT01
SUB res_old_r,res_r ; subtract the current Timer_A value from the
; old one -> Bitwidth in cycles in res_r
test_res_r01
SUB #038h,res_r ; subtract the average value from the
; measured value
CMP #010h,res_r ; is the detected signal 51-63 cycles long?
JHS no_valid_pulse
INC wake_up_counter ; next valid pulse
RETI
RSTAT10
SUB res_old_r,res_r ; subtract the current Timer_A value from
; the old one -> Bitwidth in cycles in res_r
test_res_r10
SUB #0ACh,res_r ; subtract the average value from the
; measured value
CMP #028h,res_r ; is the detected signal x cycles long?

JGE invalid_bit ; restart detection, this is not a valid
; sequence
JHS no_start_bit
INCD RSTAT ; go to RSTATE 2, Data Reception, Start Bit
; detected
no_start_bit
INC wake_up_counter ; count the pulses of the trainings sequence,
; to terninate at least after 8ms
CMP #02Fh,wake_up_counter ; compare the value of the counter with the 2.5.2000
; maximum value of the pulses of the trainings
; sequence
JGE invalid_bit ;
; BIC #CPUOFF,0(SP) ; wake up! 27.4.2000
RETI
invalid_bit
CMP #08h,wake_up_counter ; to avoid errors during the first run
27.4.2000
JEQ invalid_bit_end ; skip clearing RSTAT
27.4.2000
CLR RSTAT ; restart the detection, this is not a valid
; sequence
CLR wake_up_counter ; initialize the wake_up_counter
invalid_bit_end
; BIC #CPUOFF,0(SP) ; wake up! 27.4.2000
RETI
;*****************************************************************************************
;*****************************************************************************************
;*****************************************************************************************
;CONVOLUTIONAL ENCODING IMPLEMENTATION
;This routine implements convolutinal encoding before transmitting the data over the air
;*****************************************************************************************
;*****************************************************************************************
;*****************************************************************************************
encode
MOV SP, &9F6h ; preliminary housekeeping

MOV #9F6h, SP
PUSH SR
PUSH R4
PUSH R5
PUSH R6
PUSH R7
PUSH R8
PUSH R9
PUSH R10
PUSH R11
PUSH R12
PUSH R13
PUSH R14
PUSH R15
MOV #40h,R12
MOV #20h, R15
MOV #20h, R14
loop1
MOV 0200h(R15),R4
CMP R14, R15

JNE okay
MOV R4,R5 ; prep R5 4 XOR
RLA R5
MOV R4,R6 ; prep R6 4 XOR
RLA R6
RLA R6
XOR R4,R6 ; makes CO LSB in R6
XOR R6,R5 ; makes CO MSB in R5
JMP okay_1
okay
MOV R4, R5
MOV 0200h(R14),R13
DECD R14
RLA R5
RLC R13
ADC R5
MOV R5, R6
RLA R6
RLC R13
ADC R6
XOR R4, R6
XOR R6, R5
okay_1
MOV #8h,R11
loop2
RRC R6 ; makes 1st output word

RRC R7 ; in R7
RRC R5 ; R5 holds 7 encode
RRC R7 ; R6 holds 5 encode
DEC R11
JNZ loop2
MOV #8h, R11
loop3
RRC R6 ; makes 2nd output word
RRC R8 ; in R8
RRC R5
RRC R8
DEC R11
JNZ loop3
MOV R7,300h(R12) ; puts 1st OW in mem to send

;MOV R7,342h(R12)
DECD R12
MOV R8,300h(R12) ; puts 2nd OW in mem to send
;MOV R8,342h(R12)
DECD R12
DECD R15
JNZ loop1
; flush bits
MOV R4,R5 ; setting up to XOR for
MOV R4,R6 ; last 2 bits.
; RRA R4
; RRA R4
; RRA R5
CLRC
RRC R4
CLRC
RRC R4
CLRC
RRC R5
XOR R4,R6
XOR R6,R5
CLR R7 ; clearing R7 to recv flush bits
RLC R5 ; extracting 7 encoding
RLC R7
RLC R6 ; extracting 5 encoding
RLC R7 ; R5 holds 7 encode
RLC R5 ; R6 holds 5 encode
RLC R7 ; rotating left to put at front
RLC R6 ; of R7
RLC R7
MOV R7,&300h
;MOV R7,&342h
POP R15 ; wrapping up

POP R14
POP R13
POP R12
POP R11
POP R10
POP R9
POP R8
POP R7
POP R6
POP R5
POP R4
POP SR
POP SP
CALL #decode
RET
;*********************************** Viterbi Decoding **********************

;
;****************************************************************************
decode
MOV SP, &9F6h ; preliminary housekeeping

MOV #9F6h, SP
PUSH SR
PUSH R4
PUSH R5
PUSH R6
PUSH R7
PUSH R8
PUSH R9
PUSH R10
PUSH R11
PUSH R12
PUSH R13
PUSH R14
PUSH R15 ; end of housekeeping

CLR &9F8h
CLR &9FAh
CLR &9FCh
CLR &9FEh
MOV #0040h, R15 ; 18x words in memory counter
wloop
MOV 0300h(R15), R10 ; get encoded word to work on
MOV #0008h, R14 ; 8x per word counter
inner1
MOV #0002h, R13
inner2 ; begin calcuation of AE11(n+1)
MOV &09FCh, R4 ; get AE10(n) for calc AE11(n+1)

MOV &09FEh, R5 ; get AE11(n) for calc AE11(n+1)
CLR R8 ; empty R8, to rec C0(n) from R10
; then move it into R6.
;
;
RRC R10 ; extracting C0(n) into R6

RRC R6 ; *
RRC R10 ; *
RLC R8 ; *
RLC R6 ; *
RLC R8 ; *
MOV R8, R6 ; R8 collects AE 4 path 1 to AE11(n+1)
; C0(n) in R8 and R9
XOR #0001h, R8 ; counts digits diff w/ PW into R8
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *
ADD R4, R8 ; adds AE10(n)
; AE11(n+1) path1 in R8

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *
CMP R8, R9 ; selecting min AE11(n+1)

JL here0
RRC R8 ; saving AE11(n+1)
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; capturing pred state for state 11
RLA R11 ; *
ADD #0002h, R11 ; *
JMP here1
here0
RRC R7 ; *

RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0003h, R11 ; *
here1 ; begin calcuation of AE10(n+1)
MOV &09F8h, R4 ; get AE00(n) for calc AE10(n+1)

MOV &09FAh, R5 ; get AE01(n) for calc AE10(n+1)
;
; R6 holds CO(n)
MOV R6, R8 ; put in R8 for calc
;
; R8 collects AE 4 path 1 to AE10(n+1)
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here2
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0000h, R11 ; *
JMP here3
here2
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0001h, R11 ; *

;
; R6 holds CO(n)
;
CLR R12 ; *
RRC R8 ; *

ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here4
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0002h, R11 ; *
JMP here5
here4
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0003h, R11 ; *

;
; R6 holds CO(n)
;
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here6

RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0000h, R11 ; *
JMP here7
here6
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0001h, R11 ; *
here7
CLR R4 ; saving AE00(n+1)
RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9F8h ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9FAh ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9FCh ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9FEh ; *
DEC R13 ; counts 2 bytes per push

JNZ inner2
PUSH R11
DECD R14 ; counts 8 pushes per word
JNZ inner1
DECD R15 ; counts 18 words
JNZ wloop
MOV &342h, R10
inner_1
MOV #0002h, R13
inner_2 ; begin calcuation of AE11(n+1)

CLR R8 ; empty R8, to rec C0(n) from R10
; then move it into R6.
;
;
RRC R10 ; extracting C0(n) into R6

RRC R6 ; *

RRC R10 ; *
RLC R8 ; *
RLC R6 ; *
RLC R8 ; *
; C0(n) in R8 and R9
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here_0
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0002h, R11 ; *
JMP here_1
here_0
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0003h, R11 ; *
here_1 ; begin calcuation of AE10(n+1)

;
; R6 holds CO(n)
;
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *

ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here_2
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0000h, R11 ; *
JMP here_3
here_2
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0001h, R11 ; *

;
; R6 holds CO(n)
;
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here_4
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0002h, R11 ; *
JMP here_5
here_4

RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0003h, R11 ; *

;
; R6 holds CO(n)
;
CLR R12 ; *
RRC R8 ; *
ADC R12 ; *
RRC R8 ; *
ADC R12 ; *
MOV R12, R8 ; *

CLR R12 ; *
RRC R9 ; *
ADC R12 ; *
RRC R9 ; *
ADC R12 ; *
MOV R12, R9 ; *

JL here_6
RRC R7 ; *
RRC R8 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0000h, R11 ; *
JMP here_7
here_6
RRC R7 ; *
RRC R9 ; *
RRC R7 ; *
RLA R11 ; *
ADD #0001h, R11 ; *
here_7
RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9F8h ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *

MOV R4, &9FAh ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9FCh ; *

RLC R7 ; *
RLC R4 ; *
RLC R7 ; *
RLC R4 ; *
MOV R4, &9FEh ; *
DEC R13 ; counts 2 bytes per push

JNZ inner_2
PUSH R11
; This section handles the predecessor state vectors

; FLUSH BITS
MOV #0000h, R4
POP R5
MOV R5,R6
SWPB R6
AND #00FFh, R5
AND #00FFh, R6
CMP #0000h, R4
JNE yippee
AND #0003h, R5
MOV R5, R7
JMP woohoo
yippee
CMP #0001h, R4
JNE yippee1
RRA R5
RRA R5
AND #0003h, R5
MOV R5, R7
JMP woohoo
yippee1
CMP #0002h, R4
JNE yippee2
RRA R5
RRA R5
RRA R5
RRA R5
AND #0003h, R5
MOV R5, R7
JMP woohoo
yippee2
RRA R5
RRA R5
RRA R5
RRA R5
RRA R5
RRA R5
MOV R5, R7
woohoo
MOV R7, R4
CMP #0000h, R4
JNE yippee3

AND #0003h, R6
MOV R6, R7
JMP woohoo1
yippee3
CMP #0001h, R4
JNE yippee4
RRA R6
RRA R6
AND #0003h, R6
MOV R6, R7
JMP woohoo1
yippee4
CMP #0002h, R4
JNE yippee5
RRA R6
RRA R6
RRA R6
RRA R6
AND #0003h, R6
MOV R6, R7
JMP woohoo1
yippee5
RRA R6
RRA R6
RRA R6
RRA R6
RRA R6
RRA R6
MOV R6, R7
woohoo1
MOV R7, R4
; ENCODED BIT
MOV #0020h, R15 ; Set to total number of bytes of original uncoded message
MOV #0002h, R13
loopiest
MOV #0008h, R14
CLR R8
loopy POP R5
MOV R5, R6
SWPB R6
AND #00FFh, R5
AND #00FFh, R6
CMP #0000h, R4
JNE yippee_
AND #0003h, R5
MOV R5, R7
JMP woohoo_
yippee_
CMP #0001h, R4
JNE yippee1_
RRA R5
RRA R5
AND #0003h, R5
MOV R5, R7
JMP woohoo_
yippee1_
CMP #0002h, R4
JNE yippee2_
RRA R5
RRA R5
RRA R5
RRA R5

AND #0003h, R5
MOV R5, R7
JMP woohoo_
yippee2_
RRA R5
RRA R5
RRA R5
RRA R5
RRA R5
RRA R5
MOV R5, R7
; collecting info bits
woohoo_
CMP R7, R4
JNE not_equal
CMP #0000h, R7
JNE equals_3
CLRC
JMP done_is_done
equals_3
SETC
JMP done_is_done
not_equal
JL _less
SETC
JMP done_is_done
_less
CLRC
done_is_done
RLC R8
MOV R7, R4
; Repeat R5 process on R6
CMP #0000h, R4
JNE yippee3_
AND #0003h, R6
MOV R6, R7
JMP woohoo1_
yippee3_
CMP #0001h, R4
JNE yippee4_
RRA R6
RRA R6
AND #0003h, R6
MOV R6, R7
JMP woohoo1_
yippee4_
CMP #0002h, R4
JNE yippee5_
RRA R6
RRA R6
RRA R6
RRA R6
AND #0003h, R6
MOV R6, R7
JMP woohoo1_
yippee5_
RRA R6
RRA R6
RRA R6

RRA R6
RRA R6
RRA R6
MOV R6, R7
woohoo1_
CMP R7, R4
JNE not_equal_
CMP #0000h, R7
JNE equals_3_
CLRC
JMP done_is_done_
equals_3_
SETC
JMP done_is_done_
not_equal_
JL _less_
SETC
JMP done_is_done_
_less_
CLRC
done_is_done_
RLC R8
MOV R7, R4
DEC R14
JNZ loopy
MOV R8, 0222h(R13)
INCD R13
DECD R15
JNZ loopiest
wrap_up
POP R15 ; wrapping up
POP R14
POP R13
POP R12
POP R11
POP R10
POP R9
POP R8
POP R7
POP R6
POP R5
POP R4
POP SR
POP SP
RET
;**************************** WDT Interrupt Routine ****************************************************

; used for periodical wakeup during the listen phase
;
;*******************************************************************************************************
WDT_INT
BIC #CPUOFF,0(SP) ; reactivate CPU
RETI
;*********************************** Interrupt vector table ********************************************

;
;*******************************************************************************************************

reset
RSEG INTVEC
DW START ; 0FFE0h not used
DW START ; 0FFF4h P1_INT
DW START ; 0FFE6h I/O Port P2
DW TA_INT ; 0FFEAh timer A1(CC1,CC2)
DW START ; 0FFECh not used
DW START ; 0FFEEh not used
DW START ; 0FFF0h not used
DW START ; 0FFF2h CC0_INT
DW WDT_INT ; 0FFF4h Watchdog Timer in timer mode
DW START ; 0FFFAh not used
DW START ; 0FFFCh NMI, Oscillator fault
DW START ; 0FFFEh Power On Reset, WDTIFG
END main

FINAL REPORT Ashutosh Jaiswal

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FINAL REPORT Ashutosh Jaiswal

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Evaluation and Real Time Implementation of Different Techniques for a Wireless Indoor

Communication Channel and a Comparative Study of their effect on the BER

Abstract coding techniques and then comparative evaluation

1 St. Mary’s University, San Antonio

2 . TRF 6903 Transceiver common data rates, is provided by the TRF6903.

The transmitter consists of an integrated VCO and

2 St. Mary’s University, San Antonio

3.2. Protocol Definition

The RS-232 protocol used to transfer data to and

3.2.2. Wireless Protocol

The protocol used for wireless packet transmission

Table 1: Wireless Protocol used for Packed Data Transfer

The entire wireless protocol consists of three parts:

3 St. Mary’s University, San Antonio

The training sequence is a square wave signal 3.2.2.2. Start Bit

Figure 5: Data Packet- Sending 32 Bytes of Data

4. TRF6903 Register Setup

4 St. Mary’s University, San Antonio

5 St. Mary’s University, San Antonio

6.3. Configure the UART

The ports 2.4 and 2.5 of MSP430 are configured to

6 St. Mary’s University, San Antonio

7.3 Detection of Data Bits

7 St. Mary’s University, San Antonio

that services the DCLK trigger has latency of about

Figure 8: Receive data reception using DCLK

The BLUE arrow (point 1) indicates the time when

8 St. Mary’s University, San Antonio

10.1. Convolutional Encoding

Convolutional Encoding is a Forward Error

9 St. Mary’s University, San Antonio

10 St. Mary’s University, San Antonio

10.2.1. Decoding using Trellis diagram

In order to understand the decoding process using

11 St. Mary’s University, San Antonio

been” received had the branch associated with that

12 St. Mary’s University, San Antonio

13 St. Mary’s University, San Antonio

Extensive measurements were conducted in an

14 St. Mary’s University, San Antonio

15 St. Mary’s University, San Antonio

[1] Andrew H. Snelgrove, The Design of a

[2] Xun Liu, Marios C. Papaefthymiou, Design of

[3] Harsha Rao, Implementing a Bidirectional

[4] User Guide: TRF6903 with MSP430 –

[5] User Guide: MSP430x4xx Family – Texas

[6] Data Sheet: MSP430x4xx Family – Texas

[7] Data Sheet: TRF6903 Transceiver – Texas

16 St. Mary’s University, San Antonio

Some parts of the code were provided by Texas Instruments

RAM_orig EQU 00200h ; RAM start

RSEG CODE ; beginning of the code

;*********************************** main **************************************************************

CALL #encode ; initialization of the TRF6900 and

DINT ; general Interrupt disable

17 St. Mary’s University, San Antonio

CALL #receive_RF ; receive 10x8bits

;********************************* Intialization *******************************************************

;****************************** Clock Settings *********************************************************

; BIS #OSCOFF, SR ; turn off

; high frequency oscillator selected

;BIC #OSCOFF, SR ; turn on

MOV #0FFFh,wait_r ; for programming purpose

;* main ****************************

;* Intialization ***********************

; Clock Settings ***************************

; Programming the TRF6903 **********************

;* program_DDS0_receive_learn **************

;* program_DDS1_send ***********************

;* program_send_FSK ************************

;* program_receive_FSK_learn ***************

;* program_receive_FSK_hold ****************

; program_TRF6903 ******************************

;* send_RF *************************

;* receive_RF **************************

; rs232_send *******************

; checksum_s *******************

; checksum_r *******************

; check_chcksm_s ***************

; check_chcksm_r *******************

; wait loops *******************

; wait for lockdetect **********

; Timer_A Interrupt routine

; Capture Compare 1 Register ***************

; Capture Compare 2 Register ***************

;************* Viterbi Decoding