Lecture 28

Interconnections and Buses

Serial Port
Decreasing in importance since the release of the USB standard but it used to be employed extensively in the computer system, especially in modems. Still used in dedicated applications. The information is sent as a sequence of bits over a data line. The duration of each bit is compared against a clock base that determines the rate of the information flow. Need to be concerned about flow control between endpoints. The CPU receives interrupts from the serial port which indicate the data is ready.
Logic 1 start LSB Logic 0 stop MSB parity

DATA (7 bits)

Protocol: 7/8 bits, parity (even/odd), stop bit

Serial Port
Since the computer needs to communicate with each serial port, the operating system must know that each serial port exists and where it is (its I/O address). It also needs to know which wire (IRQ number) the serial port must use to request service from the computer's CPU. It requests service by sending an interrupt on this wire. Thus every serial port device must store in its non-volatile memory both its I/O address and its Interrupt ReQuest number: IRQ. For the PCI bus it doesn't work exactly this way since the PCI bus has its own system of interrupts. But since the PCI-aware BIOS sets up chips to map these PCI interrupts to IRQs, it seemingly behaves just as described above except that sharing of interrupts is allowed (2 or more devices may use the same IRQ number). I/O addresses are not the same as memory addresses. When an I/O addresses is put onto the computer's address bus, another wire is energized. This both tells main memory to ignore the address and tells all devices which have I/O addresses (such as the serial port) to listen to the address to see if it matches the device's. If the address matches, then the I/O device reads the data on the data bus. From http://www.howstuffworks.com

Memory Mapped I/O

Serial Port
Function of pins in a serial interface:
Carrier Detect - Determines if the modem is connected to a working phone line. Receive Data - Computer receives information sent from the modem. Transmit Data - Computer sends information to the modem. Data Terminal Ready - Computer tells the modem that it is ready to talk. Data Set Ready - Modem tells the computer that it is ready to talk. Request To Send - Computer asks the modem if it can send information. Clear To Send - Modem tells the computer that it can send information. Ring Indicator - Once a call has been placed, computer acknowledges signal (sent from modem) that a ring is detected.

TX RX

RX TX CTS RTS

RTS CTS

The serial port allows for easy networking between two parties. Theres no need for addressing: A knows that when it talks its B whos listening and vice-versa.

The Serial Port in the PC

CPU
Interrupt

Programmable Interrupt Controller

Interrupt Vector

IRQ n

Parallel data Receive Transmit Serial link

UART
Universal Asynchronous Receive and Transmit

Buses
I/O Device

They are all about moving data (and other signals) around the computer system.

I/O Device

Processor

Memory
We can interconnect components in a number of different ways, but how can we create an architecture that is general purpose, that is, flexible, expandable, and somewhat scalable?

I/O Device

Connecting CPU, I/O and Memory

Processor Interrupts

Cache

MemoryI/O bus Memory-I/O BUS I/O controller I/O controller I/O controller

Main memory

Disk

Disk

Graphics output

Network

Types of Buses
Processor-Memory Buses
Short, high-speed, matched to maximize bandwidth; often design specific.

I/O Buses
May be long, may interconnect many devices, wide range of data bandwidth in the devices involved. Dont go directly to the CPU, use an intermediary. Often general purpose.

Backplane Buses
Interconnect different devices and different buses. Built in to the chassis of the computer system: allow different circuit boards to be plugged in together. Often general purpose.

Matters of Protocol
In order for two components in the computer system to be able to exchange information, they must agree to use a sequence of operations, a protocol. Example: Ill give you an address, then Ill pulse your MEM READ line, wait for 20ns and then you will give me the data stored in that address.

Synchronous Buses
Use clocks in the control lines; use fixed communication protocols that take the clock as time base. The predetermined protocol allows for simple hardware implementation (FSM) and high speed. Drawbacks: 1) Every device in the bus must communicate using the same rate determined by the clock. 2) Signal paths cannot run long because clock skew will cause serious trouble.

Synchronous buses are often used for design specific applications involving few devices all of which can operate at high clock rates, such as processor and memory.

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Asynchronous Buses
No clocks in the control lines. Can accommodate a variety of devices which use different communication rates. Use a handshaking protocol: sender and receiver move from one step to another only when explicit agreement is reached. Drawbacks: 1) The handshaking protocol requires additional control lines. 2) Cannot accommodate the high speeds that synchronous buses can reach.

An asynchronous bus protocol behaves as two communicating FSMs where a change in state in one of them does not happen until the other one has reached a specific state.

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Example of an Asynchronous Bus Protocol

ReadReq Data 2 Ack DataRdy 2 4 4 5 7 6 1 3

1) Memory sees ReadReq, reads addr and responds with Ack. 2) I/O device sees Ack, releases ReadReq and addr lines. 3) Memory sees ReadReq is low, drops Ack. 4) When memory has data ready, it shows data and raises DataRdy.

5) I/O device sees DataRdy, reads data and raises Ack. 6) Memory sees Ack, drops DataRdy and releases data lines. 7) I/O sees DataRdy drop, and drops Ack. Exchange completed. Tristate buffers are used a lot in buses!

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Bus Arbitration: Four Classes

1) Daisy Chain: the higher priority device gets the bus. Its simple, but its not very fair.
Highest priority Device 1 Device 2 Grant Release Lowest priority Device n

Grant Bus arbiter Grant

Request

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Bus Arbitration: Four Classes

2) Centralized Parallel Arbitration: Multiple request lines go to a central arbiter. Centralization leads to bottlenecks.

Device 1

Device 2
Grant Request

Device N
Grant

Grant

Request

Bus Arbiter

Request

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Bus Arbitration: Four Classes

3) Distributed Arbitration by Self-selection: the devices put their id on the bus and they decide themselves who should be granted access first. Requires more lines for control signals.

Device 1
Req, 1

Device 2
Req, 2

Device N
Req, N

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Bus Arbitration: Four Classes

4) Distributed Arbitration by Collision Detection: each device listens to the bus, if the bus is free, then the device grabs it. Simultaneous requests will lead to collisions which will need to be resolved so that some device will eventually be able to use the bus.

Device 1
Req, 1

Device 2
Req, 2

Device N
Req, N

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