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EXPERIMENT-5
R 2
1 0 0 k
F r e q u e n c y 1 3 1 4 3 9
+ 5 V 1 6
2 . 2
u f
n d
4 0 4 6
1 1 6 7 5
P L L
8
8 k
1 n
n d
n d
+ 5 V
6 f o / 1 0 0 1 4 7 8
1 0
1 6 1 f o = f r e q u e n c y * 1 0 0
I C
9
4 5 1 8
1 5
n d
Features of IC 4046: 1) Wide voltage range:3V to 18V. 2) VCO frequency:1.3 MHz 3) High VCO linearity: typically 1% 4) Low frequency drift:0.06%/degree C 5) Low dynamic power consumption:70uW at Fo=10kHz Features of IC 4518: 1) Supply Voltage Range:3V to 16V 2) Noise Immunity:45% typically. 3) Diode protection for all inputs. 4) Low input capacitance:5pF 5) Counting rate is around 6MHz. Procedure: 1) Before wiring the circuit, check all the components using multimeter and IC tester. 2) Make connections as shown in the circuit diagram. 3) Vary the input frequency with input voltage around 5-8V and note down the output frequency which is 100 times the corresponding input frequency. Tabular Column: Input frequency in Hz 10 50 75 100 Output period in seconds Output frequency in Hz
Result: The PLL characteristics are studied and PLL is used as frequency multiplier.
EXPERIMENT-6
4) 5) 6) 7)
High linearity triangle wave output. Wide operating frequency range 0.001Hz to 300 kHz. High level outputs-TTL to 28V. Easy to use-just a handful of extension components required
Circuit Diagram:
+ 1 0 V ( V + ) R 1
5 . 6 5 . 6 k
R 4
R L
4 . 7 k
C 1 2 V ( p - p )
V 1 0 . 2 2 u f
4 8 7
6 . 8 k
6 9
I C
1 0
0 . 0 0 2
8 0 3 8
1 1 1 2
3 2
1 k H z
G
m ( t )
n d
t r i a n g u l a r w a v e s i n e w a v e
C 2
u f
R 6
8 2 k
- 1 0 V
Design: Fc=25 kHz, R1=R2=R Fc= 0.3/RC Let C=0.02mF, then R=6k. Take R=5.6k. For fc=4v pk-pk Fcmax=? Fcmin=? Frequency deviation(fd)= (fcmax-fcmin)/2 Mod. Index=fd/fm BW=2(fd + fm) From the Bessel function table for BW=2 *n * fm Where n= no of sidebands the determined value of mod. Index
Draw the normalized amplitude spectrum using Bessel function table Procedure: 1) 2) 3) 4) 5) 6) 7) 8) Before wiring the circuit, check all the components using multimeter. Make the connections as shown in circuit diagram. Apply +ve (+12V) voltage to the IC as Vcc. Observe the waveform at pin 9, 3 and 2 on CRO that is square, triangular and sine wave respectively. Measure sine wave amplitude and frequency. It will be the frequency of carrier wave. Switch on the function generator and apply modulating signal of Vm(p-p)=4V(pp) and frequency in the range of 1 kHz through RC circuit as shown. Observe FM wave output at pin 2. Draw output waveform and note down fmax and fmin. Calculate modulation index and transmission bandwidth Br.
Waveforms:
Result: The designing of frequency modulation using IC 8038 and different frequency modulation waves has been verified.
EXPERIMENT-8
PRE-EMPHASIS
Aim: To realize a pre-emphasis circuit and draw its characteristics. Components and Equipments Required: Resistors, capacitor, breadboard, CRO, etc.
Theory: Pre-emphasis refers to a system process designed to increase, within a band of frequencies, the magnitude of some (usually higher) frequencies with respect to the magnitude of other (usually lower) frequencies in order to improve the overall signal-tonoise ratio by minimizing the adverse effects of such phenomena as attenuation distortion or saturation of recording media in subsequent parts of the system. The frequency curve is decided by special time constants. The cutoff frequency can be calculated from that value. Pre-emphasis is commonly used in telecommunications, digital audio recording, record cutting, in FM broadcasting transmissions, and in displaying the spectrograms of speech signals. In high speed digital transmission, pre-emphasis is used to improve signal quality at the output of a data transmission. In transmitting signals at high data rates, the transmission medium may introduce distortions, so pre-emphasis is used to distort the transmitted signal to correct for this distortion. When done properly this produces a received signal which more closely resembles the original or desired signal, allowing the use of higher frequencies or producing fewer bit errors.
Circuit Diagram:
Formulae:
f 1 = 1`
DE-EMPHASIS
Aim: To realize a de-emphasis circuit and draw its characteristics.
Theory: De-emphasis is a system process designed to decrease, within a band of frequencies, the magnitude of some (usually higher) frequencies with respect to the magnitude of other (usually lower) frequencies in order to improve the overall signal-tonoise ratio by minimizing the adverse effects of such phenomena as attenuation differences or saturation of recording media in subsequent parts of the system. It is the complement of pre-emphasis, and the whole system is called emphasis. The frequency curve (response) is decided by special time constants, from which one can calculate the cutoff frequency. Formulae:
2RC Rf Gain = 1 + R1
Procedure: 1) Before wiring the circuit checks all the components. 2) Make the connection as shown in circuit diagram. 3) With suitable amplitude of i/p change the frequency of i/p and note down the o/p voltage. 4) Plot the graph of gain v/s frequency.
f = 1`
Result: The de-emphasis characteristics are studied and the graph of gain v/s frequency is plotted.
EXPERIMENT 7
FREQUENCY DEMODULATION
Aim: To check frequency demodulation characteristics. Equipments and Apparatus Required: IC 565, resistors, capacitors, potentiometer, CRO, signal generator, DC power supply. Pin diagrams: include Features: Circuit Diagram:
+ 1 0 V
1 0 k 2 n f
8 F M i / p
R 1
1 0 7 o u t p u t
1 5 k 0 . 0 1 u f
4 . 7 k
I C
5 6 55
4
3 9
1 n f
- 1 0 V
Theory: Frequency demodulation or detection can be obtained directly by using the PLL circuit. When the centre frequency of the PLL is selected or designed at the FM carrier frequency, the filtered or output voltage in the circuit shown in figure, is obviously the desired demodulated voltage, that varies in magnitude in proportion to the signal frequency. PLL unit contains a phase comparator PC, amplifier, and VCO, PC, amplifier and VCO are only partially connected internally. If the signal feedback is not equal to the input sgnal the difference signal will change the value of signal feedback until it is equal to the input signal. The error signal is used to adjust the VCO frequency such that the instantaneous phase angle comes close to the incoming signal. At this point 2 signals are in sync. And PLL is locked to the incoming frequency.
Procedure: 1) Check the components before making circuit connections. 2) Connections are made as shown in the circuit diagram. 3) Vary the 10k pot and note down the output frequency.
Result: