9th International Conference on Environment and Electrical Engineering EEEIC 2010

FPGA based Cascaded Multilevel Pulse Width M d l i f Si l P l Wid h Modulation for Single Phase Inverter
Poster P t presentation by t ti b KARUPPANAN P, National I tit t f T h l N ti l Institute of Technology, Rourkela, India-769008.

Introduction
The development of FPGA based controller for conventional and cascaded multilevel PWM single phase inverter The conventional multilevel inverter is constructed by the Hbridge and cascaded inverter constructed by two full H-bridges. VHDL language is used to model the inverter switching strategies. The proposed controller generates 4 and 8 control signals for conventional and cascaded inverter to 3-level and 7- level output voltages. Matlab/System generator and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA FPGA. These inverter topologies with filters would have reduced harmonics and can operate at high efficiency

System design using xilinx blockset/Matlab for FPGA based controlled 8-channel gate signal generator
6000 0 6000 5000 5000 4000 4000 3000 3000 2000 2000 1000 1000 0 Sine wave Sawtooth wave > > > > > > XOR NOT NOT XOR NOT NOT Sa Sb SA SB Sd Sc SD SC

Flow chart of FPGA design and embedded single chip

System design using Matlab/Xilinx Block set VHDL coding generated using system generator Verification and simulation RTL schematic and synthesis Place and Route XILINX/ SPARTAN3E (Embedded in FPGA chip) Gate Signal Verification and simulation Load Single phase PWM inverter

Optoisolator and Driver

Three-level multilevel PWM single phase inverter

Sc R L

Sa Vdc

Sb

Sd

VHDL coding for 4-gate switching signals

4

60

output voltage
3 40 2 20 1

output current

-1 -20 -2 2 -40 -3

-60 0

Output voltage

5 x 10

6
4

-4 0

5 x 10

6
4

Output Current

Cascaded PWM single phase inverter

Sa Vdc/2 Vd /2 Sb Sd R Sc V2

SA Vdc SB

SC V1 SD

VHDL coding for switching signals

8 gate 8-gate

Cascaded PWM single phase inverter output waveforms

80

output voltage
60

40

20

-20 0

Output voltage g
1 2 3 4 5 x 10
x 10
-3

-40

-60

-80 0

6
4

8 6

output current

-2

-4

Output Current
1 2 3 4 5 x 10 6
4

-6

-8 0

Order of harmonic measured the fundamental frequency

single phase conventional multilevel VSI g p

single phase Cascaded multilevel VSI i l h C d d ltil l

THD Voltage current

Multilevel inverter 84.05% 12.05%

Cascaded Multilevel inverter 18.92% 5.04%

CONCLUSIONS
The FPGA based controller switching patterns are adopted and g p p applied to the multilevel and cascaded multilevel inverter switches to generate 3-level and 7-level output voltages. The FPGA enables to make easy, fast and flexible design of the p y control circuit for hardware implementation. It can effectively extend the modulation index range that facilitates a better quality output voltage with minimal distortion.

The experimental and simulation results demonstrate quality voltage and current waveform shapes at the output of the inverter. These inverter topologies with proposed control circuit can be used for speed control of induction motor and other industrial applications and would be attempted as a future work.

REFERENCES
Keith Corzine and Yakov Familiant A New Cascaded Multilevel H-Bridge DriveIEEE Trans on power electronics, Vol.17, no.1, Jan-2002 John N. Chiasson, Burak zpineci, and Leon M. Tolbert A Five-Level Three-Phase Hybrid Cascade Multilevel Inverter Using a Single DC Source for a PM Synchronous Motor Drive- 2007 IEEE. Zhong Du, Burak Ozpineci, and Leon M. Tolbert Modulation Extension Control of Hybrid Cascaded H-bridge Multilevel Converters with 7-level Fundamental b id d d b id l il l ih l l d l Frequency Switching Scheme Oak Ridge National Laboratory, Oak Ridge M.I. Ahmad, Z. Husin, R. B. Ahmad, H. Rahim, M.S. M I Ahmad Z Husin R B Ahmad H A Rahim M S Abu Hassan M N Md Isa Hassan, M.N. FPGA based control IC for Multilevel Inverter Proceedings of the International Conference on Computer and Communication Engineering 2008 S. Mekhilef d Masaoud Xili FPGA B d M l il l PWM Si l Ph S M khil f and M d Xilinx Based Multilevel Single Phase Inverter Engineering e-Transaction, Vol.1, No 2, pp 40-45, 2006 http://www.xilinx.com http://www xilinx com http://www.mathworks.com